Yamaha Ls 9 Service Manual
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![Page 46
LS9-16/LS9-32
46
Fig. 15
¢
$£ [22L]: Bind Head Tapping Screw-B
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[32]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[42C]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[52E]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[62D]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[66]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[42C]
[52E]
[42C]...](http://img.usermanuals.tech/thumb/83/98063/w64_d_1507181543-yamaha-ls-9-service-manual_d-45.png "Page 46
LS9-16/LS9-32
46
Fig. 15
¢
$£ [22L]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 IT (WE997400)
[32]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[42C]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[52E]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[62D]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[66]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[42C]
[52E]
[42C]...")
![Page 47
47 LS9-16/LS9-32
Photo 11
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£Photo 12
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£
[10c]: Button L (White)](http://img.usermanuals.tech/thumb/83/98063/w64_d_1507181543-yamaha-ls-9-service-manual_d-46.png "Page 47
47 LS9-16/LS9-32
Photo 11
¢ø
£Photo 12
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£
[10c]: Button L (White)")
![Page 48
LS9-16/LS9-32
48
E. Disassembly Procedure of LCD Assembly
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ür£
[22M]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[32E]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
[52]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 IT (WE997400)
[62E]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
YAMAHA
PNMS
PNDA
INV
LCD
¢÷ ¥ÃŸµÓè £[110] [120]
[22Q][140]
[130] [150]
ENC
LCD holder assembly
¢-$%{...](http://img.usermanuals.tech/thumb/83/98063/w64_d_1507181543-yamaha-ls-9-service-manual_d-47.png "Page 48
LS9-16/LS9-32
48
E. Disassembly Procedure of LCD Assembly
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[22M]: Bind Head Tapping Screw-B
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[32E]: Bind Head Tapping Screw-B
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[52]: Bind Head Tapping Screw-B
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[62E]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X8 MFZN2B3 (WE774400)
YAMAHA
PNMS
PNDA
INV
LCD
¢÷ ¥ÃŸµÓè £[110] [120]
[22Q][140]
[130] [150]
ENC
LCD holder assembly
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![Page 49
49 LS9-16/LS9-32
Photo 13
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£
Photo 14
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£
[110][110][110][72D][72D][72D]
E-1. ENC Circuit Board, PNMS Circuit Board
E-1-1 LS9-16: Remove the LCD assembly 16.
(See procedure B-1)
LS9-32: Remove the LCD assembly 32.
(See procedure D-1)
E-1-2 Tie a string or the like to the encoder knob marked
[110]. Then, pull the string to remove the encoder
knob marked [110] from the control panel side.
(Photo 13)
E-1-3 Remove the encoder knob marked [120], three (3)
encoder knobs...](http://img.usermanuals.tech/thumb/83/98063/w64_d_1507181543-yamaha-ls-9-service-manual_d-48.png "Page 49
49 LS9-16/LS9-32
Photo 13
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£
Photo 14
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£
[110][110][110][72D][72D][72D]
E-1. ENC Circuit Board, PNMS Circuit Board
E-1-1 LS9-16: Remove the LCD assembly 16.
(See procedure B-1)
LS9-32: Remove the LCD assembly 32.
(See procedure D-1)
E-1-2 Tie a string or the like to the encoder knob marked
[110]. Then, pull the string to remove the encoder
knob marked [110] from the control panel side.
(Photo 13)
E-1-3 Remove the encoder knob marked [120], three (3)
encoder knobs...")
![Page 50
LS9-16/LS9-32
50
Photo 15
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£
Photo 16
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£
E-2. INV Circuit Board, LCD
E-2-1 LS9-16: Remove the LCD assembly 16.
(See procedure B-1)
LS9-32: Remove the LCD assembly 32.
(See procedure D-1)
E-2-2
INV Circuit Board (Time required: About 7 minutes):
E-2-2-1
Remove the four (4) screws marked [62E]. The
INV circuit board can then be removed. (Fig. 16)
E-2-3 LCD (Time required: About 7 minutes each):
E-2-3-1 Remove the screw marked [52F] and the screw
marked [52G]. The LCD...](http://img.usermanuals.tech/thumb/83/98063/w64_d_1507181543-yamaha-ls-9-service-manual_d-49.png "Page 50
LS9-16/LS9-32
50
Photo 15
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£
Photo 16
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£
E-2. INV Circuit Board, LCD
E-2-1 LS9-16: Remove the LCD assembly 16.
(See procedure B-1)
LS9-32: Remove the LCD assembly 32.
(See procedure D-1)
E-2-2
INV Circuit Board (Time required: About 7 minutes):
E-2-2-1
Remove the four (4) screws marked [62E]. The
INV circuit board can then be removed. (Fig. 16)
E-2-3 LCD (Time required: About 7 minutes each):
E-2-3-1 Remove the screw marked [52F] and the screw
marked [52G]. The LCD...")
![Page 51
51 LS9-16/LS9-32
Photo 17
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£
LCD
¢÷ ¥ÃŸµÓè £A
LCD holder assembly
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LCD panel
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B
[42D]
Fig. 17
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E-3. PNDA Circuit Board
(Time required: About 7 minutes)
E-3-1 LS9-16: Remove the LCD assembly 16.
(See procedure B-1)
LS9-32: Remove the LCD assembly 32.
(See procedure D-1)
E-3-2 Remove the four (4) screws marked [32E]. The
PNDA circuit board can then be...](http://img.usermanuals.tech/thumb/83/98063/w64_d_1507181543-yamaha-ls-9-service-manual_d-50.png "Page 51
51 LS9-16/LS9-32
Photo 17
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£
LCD
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LCD holder assembly
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LCD panel
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B
[42D]
Fig. 17
¢
$£ [42D]: Bind Head Tapping Screw-B
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E-3. PNDA Circuit Board
(Time required: About 7 minutes)
E-3-1 LS9-16: Remove the LCD assembly 16.
(See procedure B-1)
LS9-32: Remove the LCD assembly 32.
(See procedure D-1)
E-3-2 Remove the four (4) screws marked [32E]. The
PNDA circuit board can then be...")
![Page 52
LS9-16/LS9-32
52
LSI PIN DESCRIPTION（LSI端子機能表）
HD6433682C08FPV (X6660B00) CPU (E-FDC)........................................................................\
..........52
HD6417727F160CV (X2890B00) CPU (SH3-DSP).........................................................................\
.....53
M38034M4H-224HP (X6983A00) CPU (EC-PNS1).........................................................................\
.....54
M38034M4H-225HP (X6984A00) CPU...](http://img.usermanuals.tech/thumb/83/98063/w64_d_1507181543-yamaha-ls-9-service-manual_d-51.png "Page 52
LS9-16/LS9-32
52
LSI PIN DESCRIPTION（LSI端子機能表）
HD6433682C08FPV (X6660B00) CPU (E-FDC)........................................................................\
..........52
HD6417727F160CV (X2890B00) CPU (SH3-DSP).........................................................................\
.....53
M38034M4H-224HP (X6983A00) CPU (EC-PNS1).........................................................................\
.....54
M38034M4H-225HP (X6984A00) CPU...")
51 LS9-16/LS9-32
Photo 17
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£
LCD
¢÷ ¥ÃŸµÓè £A
LCD holder assembly
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LCD panel
¢-$%ÍÉç£
B
[42D]
Fig. 17
¢
$£ [42D]: Bind Head Tapping Screw-B
¢#» Ä´#*/%£3.0X12 MFZN2W3 (WE987400)
E-3. PNDA Circuit Board
(Time required: About 7 minutes)
E-3-1 LS9-16: Remove the LCD assembly 16.
(See procedure B-1)
LS9-32: Remove the LCD assembly 32.
(See procedure D-1)
E-3-2 Remove the four (4) screws marked [32E]. The
PNDA circuit board can then be removed. (Fig. 16)
* The PNDA circuit board contains the following
buttons. (Photo 17)
· [30a]: Button S (Red) 4 pcs.
· [30b]: Button S (Blue) 4 pcs.
· [30c]: Button S (Light Blue) 4 pcs.
· [30d]: Button S (Violet) 4 pcs.
· [30e]: Button S (White) 4 pcs.
· [30f]: Button S (Gray) 8 pcs.
& 1/%
LS9-16/LS9-32 52 LSI PIN DESCRIPTION（LSI端子機能表） HD6433682C08FPV (X6660B00) CPU (E-FDC)........................................................................\ ..........52 HD6417727F160CV (X2890B00) CPU (SH3-DSP).........................................................................\ .....53 M38034M4H-224HP (X6983A00) CPU (EC-PNS1).........................................................................\ .....54 M38034M4H-225HP (X6984A00) CPU (EC-EXP).........................................................................\ .......54 YSS919B-HZ (XZ693B00) DSP7 (Digital.Signal.Processor)................................................................55 YSS919C-FZ (XZ693C00) DSP7 (Digital.Signal.Processor)................................................................55 YSS910-V (XV988B00) DSP6 (Digital.Signal.Processor).....................................................................56 YSS910C-VZ (XV988C00) DSP6 (Digital.Signal.Processor)................................................................56 TMS320DA150PGE16D (X3803A00) DSP.(Digital.Signal.Processor).................................................57 YTD442-RZ (X7197A00) VIP1.........................................................................\ ......................................58 S1L51252F32S200 (X3775A00) PLLP2 (Gate.Array).........................................................................\ .59 LC4032V-75TN48C (X7109A00) CPLD (Complex.Programmable.Logic.Device)................................60 AK4393VF-E2 (XW029A00) DAC (Digital.to. Analog.Converter)...........................................................60 AK5385BVF-E2 (X5364B00) ADC (Analog.to.Digital.Converter).........................................................60 LC4064V-75TN100C (X8315A00) CPLD (Complex.Programmable.Logic.Device)..............................61 YM3437C-FZE2 (XW060A00) DIT2 (Digital.audio.Interface. Transmitter.2)..........................................61 MBCG46183-129-PFV (XV833A00) SIO4 (Gate.Array)........................................................................62 YM3436D-FZ (XG948E00) DIR2 (Digital.Format.Interface.Receiver)...................................................62 KSZ8721SL (X5621A00) PHY.........................................................................\ .....................................63 AK4124VF (X7613A00) SRC.........................................................................\ .......................................63 MD1333N (X6154A00) DC-DC CONVERTER.........................................................................\ .............63 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 1234567891011121314151617181920212223242526272829303132 AN6AN7AVCCX2X1VCLRESTESTVSSOSC2OSC1VCCP50P51P34P35P36P37P52P53P54P55P10P11P12SDASCLP74P75P76P24P63 II–OI–II–OI–I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O Analog input Analog power supply +5 VSub clock outSub clock inInternal step-down power supply ResetTest pinGroundSystem clock outSystem clock inPower supply +5 V I/O port IIC data I/O IIC clock I/O I/O port 3334353637383940414243444546474849505152535455565758596061626364 P62P61NMIP60P64P65P66P67P85P86P87P20P21/RXDP22/TXDP23SCK3_2RXD_2TXD_2P14/IRQ0P15/IRQ1P16P17P33P32P31P30AN3AN2AN1AN0AN4AN5 I/OI/OII/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OIOI/OI/OI/OI/OI/OI/OI/OI/OIIIIII I/O port Non-maskable interrupt request I/O port I/O port / Receive data input I/O port / Transmit data output I/O portClock I/O Receive data inputTransmit data output I/O port / External interrupt request input I/O port Analog input HD6433682C08FPV (X6660B00) CPU(E-FDC)FD:IC101, 201FD2 (LS9-32 only): IC101, 201
53
LS9-16/LS9-32
PINNO.123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120
Vcc-RTCXTAL2EXTAL2Vss-RTCMD1MD2NMIIRQ0/IRL0_/PTH[0]IRQ1/IRL1_/PTH[1]IRQ2/IRL2_/PTH[2]IRQ3/IRL3_/PTH[3]IRQ4/PTH[4]VEPWCVCPWCMD5/BREQ/BACKVssQCKIO2VccQD31/PTB[7]D30/PTB[6]D29/PTB[5]D28/PTB[4]D27/PTB[3]D26/PTB[2]D25/PTB[1]D24/PTB[0]VssQD23/PTA[7]VccQD22/PTA[6]D21/PTA[5]D20/PTA[4]VssD19/PTA[3]VccD18/PTA[2]D17/PTA[1]D16/PTA[0]D15VssQD14VccQD13D12D11D10D9D8D7D6VssQD5VccQD4D3D2D1D0A0A1A2VssQA3VccQA4A5A6A7A8A9A10A11VssQA12VccQA13A14A15A16A17A18A19A20VssQA21VccQA22A23VssA24VccA25BS_/PTK[4]RD_WE0_/DQMLLWE1_/DQMLU/WEWE2_/DQMUL/ICIORD_/PTK[6]VssQWE3_/DQMUU/ICIOWR_/PTK{7}VccQRD/WR_PTE[7]/PCC0RDY/AUDSYNC_/CS0/CS2/CS3/CS4/PTK[2]/CS5/CE1A_/PTK[3}/CS6/CE1B_CE2A_/PTE[4]CE2B_/PTE[5]AFE_HC1/USB1d_DPLS/PTK[0]AFE_RLYCNT_/USB1d_DMNS/PTK[1]VssQAFE_SCLK/USB1d_TXDPLSVccQPTM[7]/PTINT[7]/AFE_FS/USB1d_RCVPTM[6]/PTINT[6]/AFE_RXIN/USB1d_SPEEDPTM[5]/PTINT[5]/AFE_TXOUT/USB1d_TXSE0
-------IIIIIO-------I/OI/OI/OI/OI/OI/OI/OI/O-I/O-I/OI/OI/O-I/O-I/OI/OI/O------------------------------------------------------O-OOO-O-OO---OOOOOOO-I-III
Power supply for RTC (1.9V)Not in use (XTAL for internal RTC)Power supply for RTC (0V)Clock mode settingNot in use (Non-maskable interrupt request)
External interrupt request
VEE control pin for LCD panelVCC control pin for LCD panelBig endian settingNot in use (bus request)Bus acknowledgeVssQSystem clock outputVccQ
Data bus
VssQData busVccQ
Data bus
VssData busVcc
Data bus
VssQData busVccQ
Data bus
VssQData busVccQ
Data bus
Address bus
VssQAddress busVccQ
Address bus
VssQAddress busVccQ
Address bus
VssQAddress busVccQAddress busVssAddress busVccAddress busNot connected (bus cycle start signal)Read strobeWrite 0 signalWrite 1 signalWrite 2 signalVssQWrite 3 signalVccQRead/WriteI/OChip Select 0Chip Select 2Chip Select 3Chip Select 4Chip Select 5Chip Select 6Output port (SWP50 Reset)Output port (PLG Board Reset)SPD DATASPD CLVssQNot in use (USB1 D+ transmission)VccQ
Not in use
PINNO.121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240
PTM[4]/PINT[4]/AFE_RDET_/USB1d_TXDMNSReserved/USB1d_SUSPENDUSB1_ovr_crnt/USBF_VBUSUSB2_ovr_crnt_RTS2_/USB1d_TXENLPTE[2]/USB1_pwr_enPTE[1]/USB2_pwr_enCKE/PTK[5]/RAS3/PTJ[0]Reserved/PTJ[1]Reserved//CAS/PTJ[2]VssQReserved/PTJ[3]VccQReserved/PTJ[4]Reserved/PTJ[5]VssPTD[5]/CL1VccPTD[7]/DONPTE[6]/M_DISPPTE[3]/FLMPTE[0]/TDOPCC0RESET/DRACK0PCC0DRV_/DACK0_/WAIT/RESETM/ADTRG/PTH[5]/IOIS16/PTG[7]/ASEMD0PTG[5]/ASEBRKAK_PTG[4]PCC0BVD2/PTG[3]/AUDATA[3]PCC0BVD1/PTG[2]/AUDATA[2]VssPCC0CD2/PTG[1]/AUDATA[1]VccPCC0CD1/PTG[0]/AUDATA[0]VssQPTF[7]/PINT[15]/TRST_VccQPTF[6]/PINT[14]/TMSPTF[5]/PINT[13]/TDIPTF[4]/PINT[12]/TCKPTF[3]/PINT[11]/ReservedPCCREG_/PTF[2]/ReservedPCC0VS1_/PTF[1]/ReservedPCC0VS2_/PTF[0]/ReservedMD0Vcc-PLL1CAP1Vss-PLL1Vss-PLL2CAP2Vcc-PLL2PCC0WAIT_/PTH[6]/AUDCKVssVccXTALEXTALLCD15/PTM[3]/PINT[10]LCD14/PTM[2]/PINT[9]LCD13/PTM[1]/PINT[8]LCD12/PTM[0]STATUS0/PTJ[6]STATUS1/PTJ[7]CL2/PTH[7]VssQCKIOVccQTxD0/SCPT[0]SCK0/SCPT[1]TxD_SIO/SCPT[2]SIOMCLK/SCPT[3]TxD2/SCPT[4]SCK_SIO/SCPT[5]SIOFSYNC/SCPT[6]RxD0/SCPT[0]RxD_SIO/SCPT[2]VssRxD2/SCPT[4]VccSCPT[7]/CTS2_/IRQ5LCD11/PTC[7]/PINT[3]LCD10/PTC[6]/PINT[2]LCD9/PTC[5]/PINT[1]VssQLCD8/PTC[4]/PINT[0]VccQLCD7/PTD[3]LCD6/PTD[2]LCD5/PTC[3]LCD4/PTC[2]LCD3/PTC[1]LCD2/PTC[0]LCD1/PTD[1]LCD0/PTD[0]DREQ0_/PTD[4]LCK/UCLK/PTD[6]/RESETPCAMD3MD4/Scan_testenAvcc_USBUSB1_PUSB1_MAvss_USBUSB2_PUSB2_MAvcc_USBAvssAN[2]/PTL[2]AN[3]/PTL[3]AN[4]/PTL[4]AN[5]/PTL[5]AvccAN[6]/PTL[6]/DA[1]AN[7]/PTL[7]/DA[0]Avss
IOI-OOOOOOO-O-OO-O-OOOOOO--II-
III-I-I-I-IIIIIII-------I----IIIIOOO---OOOOOOOii-i-IOOO-O-OOOOOOOOII------IOIO-IOIO--IIII-IO-
Not in useUSB function VBUSUSB2_HOST2 over current detectionNot in useUSB1 voltage controlUSB2 voltage controlEnable (SDRAM)RAS for SDRAMNot in useCAS for SDRAMVssQOutput port (DAC Reset)VccQOutput port (SIO Reset)Output port (DAC Mute)VssLCD line clockVccLCD DISPLAY ONLCD alternaterLCD frame line markerJTAG (test data output)DMA request acceptanceDMA acknowledgeHardware wait requestManual reset requestAnalog A/D trigger
Not in use
VssNot in useVccNot in useVssQNot in useVccQ
Not in use
Clock mode settingPower supply for Vcc_PLL1 - PLL1(1.9V)External capacitance for CAP1 _ PLL1Power supply for Vss_PLL1 _ PLL1(0V)Power supply for Vss_PLL2 _ PLL2 (0V)External capacitance for CAP2 _ PLL2Power supply for Vcc_PLL2 _ PLL2 (1.9V)Not in useVssVccClock oscillatorExternal clock
Not in use
Input port (Flash ROM RY/BY)Output port (Flash ROM write protect)Output port (Flash ROM ACC)LCD clock outputVssQSystem clock input/output (for SDRAM)VccQOutput port for SCI
Not in use
Output port for SCINot in useReceiving data 0Not in useVssReceiving data 2VccNot in useOutput port (PLG CLOCK ON/OFF)Not in useVssQNot in useVccQLCD DATA7LCD DATA6LCD DATA5LCD DATA4LCD DATA3LCD DATA2LCD DATA1LCD DATA0DMA requestUSB clockPower on reset requestHardware standby requestBus width setting for area0Test pin (fixed to 3.3V)USB analog power supply (3.3V)USB1 data input/output (+)USB1 data input/output (-)USB analog power supply (0V)USB2 data input/output (+)USB2 data input/output (-)USB analog power supply (3.3V)A/D analog power supply (0V)
AD converter input
A/D analog power supply (3.3V)AD converter inputDA converter output (LCD contrast)A/D analog power supply (0V)
I/OI/ONAMEFUNCTIONFUNCTIONNAME
HD6417727F160CV (X2890B00) CPU(SH3-DSP)CPU: IC002
LS9-16/LS9-32 54 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 1234567891011121314151617181920212223242526272829303132 P62/AN2P61/AN1P60/AN0P57/INT3P56/PWMP55/CNTR1P54/CNTR0P53/SRDY2P52/SCLK2P51/SOUT2P50/SIN2P47/SRDY1/CNTR2P46/SCLK1P45/TXD1P44/RXD1P43/INT2P42/INT1CNVSSRESETP41/INT00/XCINP40/INT40/XCOUTXINXOUTVSSP27/(LED7)P26/(LED6)P25/(LED5)P24/(LED4)P23/(LED3)P22/(LED2)P21/(LED1)P20/(LED0) I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O–II/OI/OIO–I/OI/OI/OI/OI/OI/OI/OI/O Port 6 / Analog input Port 5/ Interrupt inputPort 5 / PWM outputPort 5 / Timer Y functionPort 5 / Timer X function Port 5 / Serial I/O2 function Port 4 / Serial I/O1 / timer Z function Port 4 / Serial I/O1 function Port 4 / Interrupt input Reset Port 4/ Interrupt input / Sub-clock generating I/O Clock inClock outGround Port 2 3334353637383940414243444546474849505152535455565758596061626364 P17P16P15P14P13P12P11/INT01P10/INT41P07/AN15P06/AN14P05/AN13P04/AN12P03/AN11P02/AN10P01/AN9P00/AN8P37/SRDY3P36/SCLK3P35/TXD3P34/TXR3P33P32P31/DA2P30/DA1VCCVREFAVSSP67/AN7P66/AN6P65/AN5P64/AN4P63/AN3 I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O–––I/OI/OI/OI/OI/O Port 1 Port 1 / Interrupt input Port 0 / A/D converter output Port 3 / Serial I/O3 function Port 3 Port 3 / D/A converter output Power supply +5 VPower supply +5 V Analog ground Port 6 / A/D converter output M38034M4H-224HP (X6983A00) CPU(EC-PNS1) FD: IC301PNMS: IC102PNIN: IC101 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 1234567891011121314151617181920212223242526272829303132 P62/AN2P61/AN1P60/AN0P57/INT3P56/PWMP55/CNTR1P54/CNTR0P53/SRDY2P52/SCLK2P51/SOUT2P50/SIN2P47/SRDY1/CNTR2P46/SCLK1P45/TXD1P44/RXD1P43/INT2P42/INT1CNVSSRESETP41/INT00/XCINP40/INT40/XCOUTXINXOUTVSSP27/(LED7)P26/(LED6)P25/(LED5)P24/(LED4)P23/(LED3)P22/(LED2)P21/(LED1)P20/(LED0) I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O–II/OI/OIO–I/OI/OI/OI/OI/OI/OI/OI/O Port 6 / Analog input Port 5/ Interrupt inputPort 5 / PWM outputPort 5 / Timer Y functionPort 5 / Timer X function Port 5 / Serial I/O2 function Port 4 / Serial I/O1 / timer Z function Port 4 / Serial I/O1 function Port 4 / Interrupt input Reset Port 4/ Interrupt input / Sub-clock generating I/O Clock inClock outGround Port 2 3334353637383940414243444546474849505152535455565758596061626364 P17P16P15P14P13P12P11/INT01P10/INT41P07/AN15P06/AN14P05/AN13P04/AN12P03/AN11P02/AN10P01/AN9P00/AN8P37/SRDY3P36/SCLK3P35/TXD3P34/TXR3P33P32P31/DA2P30/DA1VCCVREFAVSSP67/AN7P66/AN6P65/AN5P64/AN4P63/AN3 I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O–––I/OI/OI/OI/OI/O Port 1 Port 1 / Interrupt input Port 0 / A/D converter output Port 3 / Serial I/O3 function Port 3 Port 3 / D/A converter output Power supply +5 VPower supply +5 V Analog ground Port 6 / A/D converter output M38034M4H-225HP (X6984A00) CPU(EC-EXP)HAAD2: IC903
55 LS9-16/LS9-32 DSP (LS9-16): IC201, 202,205, 206DSP32 (LS9-32): IC201-206 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104 PLLEN/TEST AVddVssVdd/IC/MUTE/SSYNCMCKSXIBTYP/CS/WR/RDCA7CA6CA5CA4CA3CA2VssVddCD31/CA1CD30CD29CD28CD27CD26CD25CD24VddVssCD23CD22CD21CD20CD19CD18CD17CD16VssVddCD15CD14CD13CD12CD11CD10CD09CD08VssCD07CD06CD05CD04CD03CD02CD01CD00/WAITVddVssVddSIO00SIO01SIO02SIO03SIO04SIO05SIO06SIO07 SIO08SIO09SIO10SIO11SIO12SIO13SIO14SIO15 SIO16SIO17SIO18SIO19SIO20SIO21SIO22SIO23 SIO24SIO25SIO26SIO27SIO28SIO29SIO30SIO31 Vss VssVdd Vss Vss Vdd Vdd II I Analog ground Power supply (3.3 V) 105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208 SIO32SIO33SIO34SIO35SIO36SIO37SIO38SIO39 SIO40SIO41SIO42SIO43SIO44SIO45SIO46SIO47 SIO48SIO49SIO50SIO51SIO52SIO53SIO54SIO55 SIO56SIO57SIO58SIO59SIO60SIO61SIO62SIO63 VssVdd VssVdd Vss Vss VssVdd VssVdd VddVss /WE/CASSDCKCKE/RASVddVssBA1BA0A12A11A10A09A08 A07A06A05A04A03A02A01A00 VssVdd Vss YSS919B-HZ(XZ693B00)DSP7 (Digital Signal Processor) YSS919C-FZ(XZ693C00)DSP7 (Digital Signal Processor) AVssCPO VddDA00DA01DA02DA03DA04DA05DA06DA07VssDA08DA09DA10DA11DA12DA13DA14DA15 DA16DA17DA18DA19DA20DA21DA22DA23 DA24DA25DA26DA27DA28DA29DA30DA31 Vdd Test mode setting (0: TEST, 1: Normal)PLL enable input (0: PLL unuse, 1: PLL use) PLL filter Initial clear Power supply (2.5 V)Ground IMute control (0: SIO mute, 1: SIO normal in-out)Serial I/O Sync. signal inputSerial I/O master clock input (128 x Fs)System master clock input (60 MHz or 15 MHz)Data bus type select (0: 16 bits, 1: 32 bits)Chip selectWrite enable inputRead enable input CPU data bus / CPU address bus CPU data bus Wait output I/O Power supply (2.5 V)Ground Memory write enable signalColumn address strobeOClock (SDRAM)OCKE (SDRAM)Row address strobe OO Power supply (3.3 V)Ground Ground Power supply (2.5 V) Power supply (3.3 V)Ground Ground GroundPower supply (3.3 V) Power supply (2.5 V)Ground Power supply (3.3 V)Ground Power supply (2.5 V)Ground Power supply (3.3 V)Ground Ground GroundPower supply (3.3 V) GroundPower supply (2.5 V) GroundPower supply (3.3 V) Ground GroundPower supply (2.5 V) Power supply (3.3 V) Ground GroundPower supply (3.3 V) Power supply (2.5 V)Ground GroundPower supply (3.3 V) I I I IIIIIII I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/OO I CPU address bus I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/O I/OI/O I/OI/O I/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/O CPU data bus CPU data bus CPU data bus Serial data bus Serial data bus Serial data bus Serial data bus Serial data bus I/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/O I/O I/OI/OI/OI/O I/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/O I/O I/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O OO I O OOOOO OOOOOOOO I Serial data bus Serial data bus Serial data bus Memory data bus Memory data bus Memory data bus Memory data bus Memory address (SDRAM, DRAM) Memory address (SDRAM, DRAM) Bank select (SDRAM)
LS9-16/LS9-32 56 DSP (LS9-16): IC351, 352DSP32 (LS9-32): IC351, 352 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788 VddVssXIXOVdd5/SYNCI/SYNCOVdd5CKICKOCKSELVssMCKS/SSYNC/IC/TESTBTYP/IRQTRIGVdd5Vss/CS/WR/RDCA7CA6CA5CA4CA3CA2CA1VssVddCD15CD14CD13CD12CD11CD10CD09CD08CD07CD06VssVddVdd5CD05CD04CD03CD02CD01CD00/WAITVssSI0SI1SI2SI3SI4SI5SI6SI7VssVdd5SO0SO1SO2SO3SO4SO5SO6SO7VssDB00DB01DB02DB03DB04DB05DB06DB07DB08DB09DB10DB11DB12Vdd5Vdd IO IO IOI IIIIIOI/O IIII/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OO IIIIIIII OOOOOOOO I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O Power supply (3.3 V)GroundSystem master clock input (60 MHz or 30 MHz)System master clock output (High or 30 MHz)Power supply (5 V)Sync. signal inputSync. signal outputPower supply (5 V)System clock input (30 MHz)System clock output (30 MHz)System master clock select (0: 60 MHz, 1: 30 MHz)GroundSerial I/O master clock input (128 x Fs)Serial I/O Sync. signal outputInitial clear (RESET)Test mode setting (0: Test, 1: Normal)Data bus type select (0: 8 bit, 1: 16 bit)IRQ outputTrigger signal input/outputPower supply (5 V)Groundchip select signal inputWrite signal inputRead signal input Address bus of internal register GroundPower supply (3.3 V) Data bus of internal register GroundPower supply (3.3 V)Power supply (5 V) Data bus of internal register WAIT outputGround Serial data input GroundPower supply (5 V) Serial data output Ground Parallel data bus Power supply (5 V)Power supply (3.3 V) 8990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176 VssDB13DB14DB15DB16DB17DB18DB19DB20DB21DB22VssVddDB23DB24DB25DB26DB27DB28DB29DB30DB31TIMO/DBOBVssVdd5DA00DA01DA02DA03DA04DA05DA06DA07VssDA08DA09DA10DA11DA12DA13DA14DA15VssVdd(n.c)Vdd5DA16DA17DA18DA19DA20DA21DA22DA23VssDA24DA25DA26DA27DA28DA29DA30DA31Vdd5VssA00A01A02A03A04A05A06A07A08A09VssVddA10A11A12A13A14A15/RASA16/CASA17/CE/WE/OEVdd5 I/OI/OI/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O I/OI/OI/OI/OI/OI/OI/OI/O OOOOOOOOOO OOOOOOOOOO Ground Parallel data bus GroundPower supply (3.3 V) Parallel data bus Timing signal output/ Parallel data bus output/ inputGroundPower supply (5 V) Memory data bus Ground Memory data bus GroundPower supply (3.3 V)Not usedPower supply (5 V) Memory data bus Ground Memory data bus Power supply (5 V)Ground Memory address (SRAM, PSRAM, DRAM) GroundPower supply (3.3 V) Memory address (SRAM, PSRAM, DRAM) Memory address (SRAM, PSRAM) Memory address (SRAM, PSRAM), /RAS (DRAM)Memory address (SRAM, PSRAM), /CAS (DRAM)Memory address (SRAM), /CE (PSRAM)Memory write enable signalMemory output enable signalPower supply (5 V) YSS910-V(XV988B00) DSP6 (Digital Signal Processor) YSS910C-VZ(XV988C00) DSP6 (Digital Signal Processor)
57 LS9-16/LS9-32 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172 CVSSA22CVSSDVDDA10HD7A11A12A13A14A15CVDDHASDVSSCVSSCVDDHCSHR/WREADYPSDSISR/WMSTRBIOSTRBMSCXFHOLDAIAQHOLDBIOMP/MCDVDDCVSSBDR1BFSR1CVSSBCLKR1HCNTL0DVSSBCLKR0BCLKR2BFSR0BFSR2BDR0HCNTL1BDR2BCLKX0BCLKX2CVSSHINTCVDDBFSX0BFSX2HRDYDVDDDVSSHD0BDX0BDX2IACKHBILNMIINT0INT1INT2INT3CVDDHD1CVSSBCLKX1DVSS –I/O––I/OI/OI/OI/OI/OI/OI/O–I–––IIIOOOOOOOOOOIII––II/O–I/OI–I/OI/OI/OI/OIIII/OI/O–O–I/OI/OO––I/OOOOIIIIII–I/O–I/O– GroundAddress busGroundPower supply +3.3 VAddress busBidirectional data bus Address bus Power supply +1.6 VAddress strobe.GroundGroundPower supply +1.6 VChip select.Read/write.Data ready. Data, program, and I/O space select signals. Read/write signal.Memory strobe signal.I/O strobe signal.Microstate complete.External flag output (latched software-programmable signal).Hold acknowledge.Instruction acquisition signal.Hold input.Branch control.Microprocessor/microcomputer mode select.Power supply +3.3 VGroundSerial data receive inputFrame synchronization pulse for receive input.GroundReceive clock input.Control inputs.Ground Receive clock input. Frame synchronization pulse for receive input. Serial data receive inputControl inputs.Serial data receive input Transmit clock. GroundInterrupt output.Power supply +1.6 V Frame synchronization pulse for transmit input/output. Ready output.Power supply +3.3 VGroundBidirectional data bus Serial data transmit output. Interrupt acknowledge signal.Byte identification.Nonmaskable interrupt. External user interrupt inputs. Power supply +1.6 VBidirectional data busGroundTransmit clock.Ground 737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144 BFSX1BDX1DVDDDVSSCLKMD1CLKMD2CLKMD3HPI16HD2TOUTEMU0EMU1/OFFTDOTDITRSTTCKTMSCVSSCVDDHPIENADVSSCLKOUTHD3X1X2/CLKINRSD0D1D2D3D4D5A16DVSSA17A18A19A20CVSSDVDDD6D7D8D9D10D11D12HD14D13D14D15HD5CVDDCVSSHDS1DVSSHDS2DVDDA0A1A2A3HD6A4A5A6A7A8A9CVDDA21DVSS I/OO––IIIII/OOI/OI/OOIIII––I–OI/OOIII/OI/OI/OI/OI/OI/OI/O–I/OI/OI/OI/O––I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O––I–I–I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O–I/O– Frame synchronization pulse for transmit input/output.Serial data transmit output.Power supply +3.3 VGround Clock mode select signals. HPI16 mode selectionBidirectional data busTimer output.Emulator 0 pin.Emulator 1 pin/disable all outputs.IEEE standard 1149.1 test data output.IEEE standard 1149.1 test data input.IEEE standard 1149.1 test reset.IEEE standard 1149.1 test clock.IEEE standard 1149.1 test mode select.GroundPower supply +1.6 VHPI module select.GroundClock output signal.Bidirectional data busOutput pin from an internal oscillator for the crystal.Clock/oscillator input.Reset. Data bus Address busGround Address bus GroundPower supply +3.3 V Data bus Bidirectional data bus Data bus Bidirectional data busPower supply +1.6 VGroundData strobe.GroundData strobe.Power supply +3.3 V Address bus Bidirectional data bus Address bus Power supply +1.6 VAddress busGround TMS320DA150PGE16D (X3803A00) DSP (Digital Signal Processor)DSP (LS9-16): IC402DSP32 (LS9-32): IC402
LS9-16/LS9-32 58 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788 TDOTCKTMSRTCKVCC3FVCCFVSS_IOTX_ENTX_ERTXD[3]TXD[2]VSSTXD[1]TXD[0]TX_CLKVDD_IORX_CLKRXD[0]RXD[1]RXD[2]RXD[3]RX_ERRX_DVVSSFVDDCRSCOLMDIOMDCsel_BOOTTEST2TEST1TEST0VSSVSS_IOXIXOVDD_IOAVSS18DAVDD18DAVSS18AVBBAAVDD18APLL_CAPPCMSELMASTERVDD_IOnRESETVSS_IOHWSIHWSOHWBCKHWWCKHWWCK2VDDBGPIO[19]BGPIO[18]BGPIO[17]BGPIO[16]VSSBGPIO[15]BGPIO[14]BGPIO[13]BGPIO[12]BGPIO[11]BGPIO[10]BGPIO[9]BGPIO[8]BGPIO[7]BGPIO[6]VDD_IOBGPIO[5]BGPIO[4]VDDBGPIO[3]BGPIO[2]VSSBGPIO[1]BGPIO[0]VDD_IOS8068nHD[7]nHD[6]nHD[5]nHD[4]nHD[3]nHD[2]nHD[1] OIIO–––OOOO–OOO–IIIIIII––III/OOIIII––IO–––––––II–I–IOI/OI/OO–I/OI/OI/OI/O–I/OI/OI/OI/OI/OI/OI/OI/OI/OI/O–I/OI/O–I/OI/O–I/OI/O–I/OI/OI/OI/OI/OI/OI/OI/O JTAG outputJTAG inputJTAG inputJTAG outputPower supply (+3.3 V)Power supply (+1.8 V)GroundTransmit enableTransmit error Transmit data Ground Transmit data Transmit clockPower supply (+3.3 V)Receive clock Receive data Receive errorReceive data validGroundPower supply (+1.8 V)Carrier senseCollision detectionManagement data input and outputManagement clockFix the pin to ‘L’ level. Fix the pin to ‘L’ level. GroundGroundInput for X’tal resonatorOutput for X’tal resonatorPower supply (3.3 V)GroundPower supply (1.8 V)GroundBulk bias pinPower supply (1.8 V)Capacitor connection pin for the built-in PLLFix the pin to ‘L’ level.Master mode, slave mode setting. Fix the pin to ‘L’ level.Power supply (3.3 V)System resetGroundCODEC interface data-inCODEC interface data-outCODEC interface bit clockCODEC interface word clockCODEC interface word clock2Power supply (1.8 V) General-purpose input and output General-purpose input and output / RINGERGeneral-purpose input and outputGround General-purpose input and output Power supply (3.3 V)General-purpose input and output / Input of UART: RXD1General-purpose input and output / Output of UART: TXD1Power supply (3.3 V)Input of UART: RXD0 / General-purpose input and outputOutput of UART: TXD0 / General-purpose input and outputGroundGeneral-purpose input and output / Clock input and output of I2C interfa\ ce: I2C_SCLGeneral-purpose input and output / Data input and output of I2C interfac\ e: I2C_SDAPower supply (3.3 V)Access mode setting Data input and output 8990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176 nHD[0]nHA[11]VDD_IOnHA[10]nHA[9]nHA[8]nHA[7]nHA[6]nHA[5]VSS_IOVSSnHA[4]nHA[3]VDDnHA[2]nHA[1]nHA[0]nHCSnHWRnHRDVDD_IOINTnCS3nCS2VSS_IOVSSnCS1nRDVDDDQM1DQM0nCS0VDD_IOnRASnCASnWESCKESCLKVSS_IOA[20]A[19]A[18]A[17]A[16]A[15]A[14]VDD_IOA[13]A[12]A[11]A[10]VSS_IOVSSA[9]A[8]A[7]A[6]A[5]VDDA[4]A[3]A[2]A[1]A[0]VSS_IOD[15]D[14]D[13]D[12]VDD_IOD[11]D[10]D[9]D[8]VSS_IOVSSD[7]D[6]VDDD[5]D[4]VDD_IOD[3]D[2]D[1]D[0]nTRSTTDI I/OI/O–I/OI/OI/OI/OI/OI/O––I/OI/O–I/OI/OI/OI/OI/OI/O–OOO––OO–OOO–OOOOI/O–OOOOOOO–OOOO––OOOOO–OOOOO–I/OI/OI/OI/O–I/OI/OI/OI/O––I/OI/O–I/OI/O–I/OI/OI/OI/OII Data input and outputAddress inputPower supply (3.3 V) Address input GroundGround Address input Power supply (1.8 V) Address input Chip select 80 family–Write enable 68 family–Read/Write80 family–Read enable 68 family–Adress enablePower supply (3.3 V)Interrupt request signal output to host CPUChip select3Chip select2GroundGroundChip select1Read enablePower supply (1.8 V) SDRAM DQ Mask/Write enable SDRAM chip selectPower supply (3.3 V)SDRAM row adress strobeSDRAM column adress strobeSDRAM wite enableSDRAM clock enableSDRAM clockGround Adress Power supply (3.3 V) Adress GroundGround Adress Power supply (1.8 V) Adress Ground Data Power supply (3.3 V) Data GroundGround Data Power supply (1.8 V) Data Power supply (3.3 V) Data JTAG unputJTAG unput YTD442-RZ(X7197A00) VIP1JK: IC409
59 LS9-16/LS9-32 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104 --OO--OIIIIIOIIIIIO----IIIIIIII----I/OI/OI/OI/OI/OI/O--I/OI/OI/OI/O-----I/OI/OI/OI/OI/OI/O-OOOOOO-OOOOO-OOO--II---O-OOOOOI-OOOOOO-OOOOOO 105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208 (NC)(NC)PB8PB9VDDVSSPA0NCSIN6NCSIN5NRDNWRHNWRLPA1ADH1ADH2ADH3ADH4ADH5PA2VSSVDDVDDVSSADL1ADL2ADL3ADL4ADL5ADL6ADL7ADL8VSSVDDVDDVSSDT0DT1DT2DT3DT4DT5VDDVSSDT6DT7DT8DT9VDDVSS(NC)(NC)(NC)DT10DT11DT12DT13DT14DT15VSSPA3NTCWAITNCSIO3VNCSIO5VNCSJK1NCSCONTVDDNCSSLOT1NCSSLOT2NCSSIO4NCSREC2NCSMTLEDVDDNCSUSBNCSSMPTENCSUARTVSSVDDNRESCPUCLK(NC)VSSVSSNCSATSC1VDDNCSATSC2PA4PA5PA6NCTSYNCONCTSYNCIVDDNCSDSP71NCSDSP72NCSDSP73NCSDSP74NCSDSP75NCSDSP76VDDPA7PA8NCSDSP61NCSDSP62NCSDSP63NCSDSP64 (NC)VDD(NC)(NC)VSSVDDNCSDSP7NCSDSP6PA9MCK256OMCK256MIMCK256SIVSSVDDICK45ICK49DIR2XIPA10VSSVDDEXTWC1EXTWC2EXTWC3EXTWC4VSSVDDEXTWC2561EXTWC2562PA11DIRMCADIRMCBDIRWCVSSVDDDIRMCCDIRSYNCEXTWCSELDIRWCSELPA12PLLOUTVSSVDDPCPOUTPA13M256FSM128FSVSSVDD(NC)(NC)(NC)(NC)M64FSMWCMSYNCPA14WCO_BNCPA15FS256_SLOT1FS256_SLOT2VDDSYNC_SLOT1SYNC_SLOT2PB0SLOT_12MSLOT_6MVSSSLOT_3MPB1SLOT_48KSLOT_48SPB2ANA256FSVDDNLOCKNDIRLOCKVSSSCANENATPGENTSTENVDDTRRERR1TRRERR2VSSPB3NMLOCKSELNLOCKRTNPB4MUTEINVDDMUTEOUT1MUTEOUT2MUTEOUT3MUTEOUT4MUTEOUT5NMUTEOUT6VDDPB5DOUBLEK48K96PB6SLOT1_16CHSLOT2_16CHPB7(NC) ------OOOOII--IIOO--IIII--IIOIII--IIOOOI--OOOO------OOOOOOOO-OOOOO-OOOOOO-II-III-II-OOIOI-OOOOOO-OOOOOOO (Connected to VSS on P.C.B.)(Pulled up on P.C.B.)Output port B8Output port B9IO power supply (3.3V)GroundOutput port A0CPU chip select 6CPU chip select 5CPU read enableCPU write enable HCPU write enable LOutput port A1CPU address bus 11CPU address bus 12CPU address bus 13CPU address bus 14CPU address bus 15Output port A2GroundInternal power supply (2.5V)IO power supply (3.3V)GroundCPU address bus 1CPU address bus 2CPU address bus 3CPU address bus 4CPU address bus 5CPU address bus 6CPU address bus 7CPU address bus 8GroundInternal power supply (2.5V)IO power supply (3.3V)GroundCPU data bus 0CPU data bus 1CPU data bus 2CPU data bus 3CPU data bus 4CPU data bus 5IO power supply (3.3V)GroundCPU data bus 6CPU data bus 7CPU data bus 8CPU data bus 9Internal power supply (2.5V)Ground(Connected to VDD on P.C.B.)(Connected to VDD on P.C.B.)(Pulled up on P.C.B.)CPU data bus 10CPU data bus 11CPU data bus 12CPU data bus 13CPU data bus 14CPU data bus 15GroundOutput port A3CPU wait signalChip select (103V)Chip select (105V)Chip select (JK1)Chip select (CONT)Power supplyChip select (SLOT1)Chip select (SLOT2)Chip select (S104)Chip select (REC2)Chip select (MTLED)Power supplyChip select (USB)Chip select (SMPTE)Chip select (UART)GroundPower supplySystem resetCPU clock(Connected to VSS on P.C.B.)GroundGroundChip select (ATSC1)Power supplyChip select (ATSC2)Output port A4Output port A5Output port A6Internal counter synchronous signal outputInternal counter synchronous signal inputPower supplyChip select (DSP7_1)Chip select (DSP7_2)Chip select (DSP7_3)Chip select (DSP7_4)Chip select (DSP7_5)Chip select (DSP7_6)Power supplyOutput port A7Output port A8Chip select (DSP6_1)Chip select (DSP6_2)Chip select (DSP6_3)Chip select (DSP6_4) (Pulled up on P.C.B.)Power supply(Connected to VSS on P.C.B.)(Connected to VSS on P.C.B.)GroundPower supplyChip select (DSP7_ALL)Chip select (DSP6_ALL)Output port A9256FS synchronous clock output256FS synchronous clock input (Master)256FS synchronous clock input (Slave)GroundPower supplyFor internal clock 88.2k, 44.1kFor internal clock 96k, 48kClock for X1 of DIR2 Output port A10GroundPower supplyExternal word clock input 1External word clock input 2External word clock input 3External word clock input 4GroundPower supplyExternal WC (256FS) input 1External WC (256FS) input 2Output port A11MCA input of DIR2MCB input of DIR2WC input of DIR2GroundPower supplyMCC input of DIR2SYNC input of DIR2EXTWC clock select outputDIRWC clock select outputOutput port A12PLL VCO OUT inputGroundPower supplyEXT WC SEL to MWC comparison circuit outputOutput port A13Master clock (256FS)System clock (128FS)GroundPower supply(Connected to VDD on P.C.B.)(Connected to VSS on P.C.B.)(Pulled up on P.C.B.)(Pulled up on P.C.B.)System clock (64FS)Word clock Synchronous signalOutput port A14WC output for BNC connectorOutput port A15Clock (256FS) for MY SLOT1Clock (256FS) for MY SLOT2Power supplySynchronous signal for MY SLOT1Synchronous signal for MY SLOT2Output port 80Clock (12MHz) for MY SLOTClock (6MHz) for MY SLOTGroundClock (3MHz) for MY SLOTOutput port B1Word clock (48/44) for MY SLOTSynchronous signal (48/44) for MY SLOTOutput port B2Clock for analog circuitPower supplyPLL lock detect signalDIR2 PLL lock signalGroundScan test inputATPG test inputTest mode selectionPower supply2TR DIN UNLOCK input2TR DIN UNLOCK inputGroundOutput port B3Lock select outputLock delay inputOutput port B4Mute inputPower supplyMute output 1Mute output 2Mute output 3Mute output 4Mute output 5Mute output 6Power supplyOutput port B5Register setting value outputRegister setting value outputOutput port B6SLOT1 16/8 ch selectionSLOT2 16/8 ch selectionOutput port B7 S1L51252F32S200 (X3775A00) PLLP2 (Gate Array)DSP (LS9-16): IC153DSP32 (LS9-32): IC153
LS9-16/LS9-32 60 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 123456789101112131415161718192021222324 TDIA5A6A7GND0VCCO0A8A9A10A11TCKVCCGNDA12A13A14A15CLK1/ICLK2/IB0B1B2B3B4 II/OI/OI/O––I/OI/OI/OI/OI––I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O Test data in Input/Output GroundPower supply +3.3 V Input/Output Test clock inputPower supply +3.3 VGround Input/Output CLK input / Input Input/Output 252627282930313233343536373839404142434445464748 TMSB5B6B7GND1VCCO1B8B9B10B11TDOVCCGNDB12B13B14B15/GOE1CLK3/ICLK0/IA0/GOE0A1A2A3A4 II/OI/OI/O––I/OI/OI/OI/OO––I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O Test mode select Input/Output GroundPower supply +3.3 V Input/Output Test data outPower supply +3.3 VGround Input/Output Input/Output / Global output enable input CLK input / Input Input/Output / Global output enable input Input/Output LC4032V-75TN48C (X7109A00)CPLD(Complex Programmable Logic Device)CPU: IC014 AK5385BVF-E2(X5364B00) ADC (Analog to Digital Converter)HAAD2: IC106, 306, 506, 706 PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 1234567891011121314 VREFLAVSSVCOMLIN+LIN–CKS0DVDDDVSSOVFPDNDIFM/SLRCKBICK I–OIII––OIIII/OI/O Lch voltage reference inputAnalog groundCommon voltage outputLch analog positive inputLch analog negative inputMaster clock select 0Digital power supply (3.0 - 5.25 V)Digital groundAnalog input overflow detectPower down modeAudio interface formatMaster / Slave modeOutput channel clockAudio serial data clock 1516171819202122232425262728 SDTOCKS1MCLKDFS0HPFEDFS1BVSSAVSSAVDDRIN–RIN+TESTAVSSVREFR OIIIII–––III–I Audio serial date outputMaster clock select 1Master clock inputSampling speed select 0High pass filter enableSampling speed select 1Substrate groundAnalog groundAnalog power supply (4.75 - 5.25 V)Rch analog negative inputRch analog positive inputTest pinAnalog groundRch voltage reference input PINNO.I/OFUNCTIONNAMEPINNO.I/OFUNCTIONNAME 1234567891011121314 DVSSDVDDMCLK/PDBICKSDATALRCKSMUTE//CSDFSDEM0/CCLKDEM1/CDTIDIF0DIF1DIF2 --IIIIIIIIIIII Digital groundDigital power supplyMaster clockPower down modeAudio serial data clockAudio serial data inputL/R clockSoft muteDouble speed sampling mode De-emphasis enable Digital input format 1516171819202122232425262728 BVSSVREFLVREFHAVDDAVSSAOUTR-AOUTR+AOUTL-AOUTL+VCOMP//SCKS0CKS1CKS2 -II--OOOOOIIII Substrate groundLow level voltage referenceHigh level voltage referenceAnalog power supply +5 VAnalog groundRch negative analog outputRch positive analog outputLch negative analog outputLch positive analog outputCommon voltage outputParallel/serial select Master clock select AK4393VF-E2(XW029A00) DAC (Digital to Analog Converter)DA: IC903-906PHN: IC904