Motorola Astro Digital Mobile Radio Xtl5000 Detailled 6881096c74 B Manual

							6881096C74-BMay 25, 2005
Theory of Operation: Receiver Front-End3-15
3.4.1.5  Mixer (D3258)
The received signal is down-converted by a double-balanced mixer to an Intermediate Frequency 
(IF) of 109.65 MHz. The mixer is designed to provide low conversion loss and high intermodulation 
performance. The injection buffer provides a 20 dBm LO signal to the mixer. High-side injection is 
used.
3.4.2 UHF Range 1 (380–470 MHz) Band
The receiver circuits primary duties are to detect, filter, amplify, and demodulate RF signals in the 
presence of strong interfering noise and unintended signals. The receiver (see Figure 3-14) is 
broken down into the following blocks:
• Front-end, which includes:
- High pass fIlter and first low-noise amplifier (LNA)
- Preselector filter
- Switchable 15 dB attenuator
- Second LNA
- Image Filter
- First mixer
• Back-end, which includes:
- Intermediate Frequency (IF)
- ABACUS III IC
Figure 3-14.  Receiver Front-End and Back-End (UHF Range 1)
Ant. SW.
Harm. FLTPre-Amp 
SwitchPre-Amp 
SwitchPre-Amp 
SwitchPre-Amp 
SwitchMixer Preselector15 dB
Att.Low Pass 
Filter RF Input
Crystal
24dBm
1st LO
Backend A/D ConverterSSI Dec.
Filter
CLK
Synth. LO
Synth. 2nd
LO
18MHz
CLK
IF Amp Crystal
109.65MHz
A
10 dB
Att.
380-470MHz
LNA High Pass 
FilterLNA
ADC
ABACUS III IC
A 
						

							May 25, 20056881096C74-B
3-16Theory of Operation: Receiver Front-End
3.4.2.1  Highpass Filter and First Low-Noise Amplifier
The highpass filter and first low-noise amplifier (LNA) (11 dB gain) can be switched in and out of the 
signal path by diode switches. When switched into the signal path, the sensitivity of the radio is 
improved at the cost of degraded intermodulation performance. This can be necessary in fringe 
areas when strong interference that can lead to intermodulation problems are not present and the 
desired signal is weak. 
The preamplifier version of the radio must be purchased to be able to control this option. If it has not 
been purchased, the direct path created by the diode switches is the only one available, giving the 
radio standard model performance with enhanced intermodulation rejection. Purchasing the 
preamplifier option allows the user to select either mode with the CPS.
3.4.2.2  Preselector Filter
The front-end operates in the 380 to 470 MHz band. The front-ends primary function is to optimize 
half IF rejection, image rejection, and selectivity while providing the first conversion. The front-end 
uses a varactor-tuned filter that is tuned by the controller. The tuning signal is a DC control voltage 
between 0 and 9V that come from the PA power control section. Low voltages are for lower 
frequencies and higher voltages correspond to the higher frequencies. This filter is aligned in the 
factory and can also be aligned using the Tuner software.
3.4.2.3  Switchable 15 dB Attenuator
This circuit block can provide 0 dB or 15 dB of attenuation in the signal path. Normally, it is set for 
0 dB and does not affect the received signal. When strong signals are detected, the radio controller 
can choose to activate this attenuator to provide protection to the back end circuits, and to enhance 
high level intermodulation performance. Proprietary algorithms are used to control the switching.
3.4.2.4  Low-Noise Amplifier (LNA, U5302)
A diode (D5281) located after the varactor preselector and before the LNA protects the receiver from 
strong RF signals by limiting the signal amplitude going into the amplifier. The LNA is a low-noise 
monolithic IC providing ~ 15 dB of gain to the receiver. It is biased with 5 V and can be bypassed by 
the radio software under very strong signal conditions. 
The UHF receiver also has a second LNA based on Q5252 that can be activated or bypassed by the 
radio software. This amplifier is protected by D5280 and provides 11 dB of gain. This is available 
only if the preamplifier option has been purchased.
3.4.2.5  Image Filter 
Following the LNA (U5302), the signal goes through a bandpass filter before it is sent to the mixer. 
The passband is from 380 to 470 MHz with an insertion loss of about 2 dB, while the image rejection 
is 55 dB. There is a trap on the input side of this filter to attenuate the 109.65 MHz IF.
3.4.2.6  Mixer
A passive double-balanced diode ring mixer is used to down-convert the received signal to an 
Intermediate Frequency (IF) of 109.65 MHz. The mixer is designed to provide low conversion loss (< 
7.0 dBm) and high intermodulation performance and requires a strong injection signal. The mixer is 
driven by the receiver injection buffer, a two-stage LDMOS IC design, that amplifies the +3 dBm 
high-side injection signal from the Frequency Generation Unit (FGU) to +24 dBm. 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Receiver Front-End3-17
3.4.3 UHF Range 2 (450–520 MHz) Band
The receiver circuits primary duties are to detect, filter, amplify, and demodulate RF signals in the 
presence of strong interfering noise and unintended signals. The receiver (see Figure 3-15) is 
broken down into the following blocks:
• Front-end, which includes:
- High pass fIlter and first low-noise amplifier (LNA)
- Preselector filter
- Switchable 15 dB attenuator
- Second LNA
- Image Filter
- First mixer
• Back-end, which includes:
- Intermediate Frequency (IF)
- ABACUS III IC
Figure 3-15.  Receiver Front-End and Back-End (UHF Range 2)
3.4.3.1  Highpass Filter and First Low-Noise Amplifier
The highpass filter and first low-noise amplifier (LNA) (11 dB gain) can be switched in and out of the 
signal path by diode switches. When switched into the signal path, the sensitivity of the radio is 
improved at the cost of degraded intermodulation performance. This can be necessary in fringe 
areas when strong interference that can lead to intermodulation problems are not present and the 
desired signal is weak. 
The preamplifier version of the radio must be purchased to be able to control this option. If it has not 
been purchased, the direct path created by the diode switches is the only one available, giving the 
radio standard model performance with enhanced intermodulation rejection. Purchasing the 
preamplifier option allows the user to select either mode with the CPS.
Ant. SW.
Harm. FLTPre-Amp 
SwitchPre-Amp 
Switch
Mixer Preselector15 dB
Att.Low Pass 
Filter RF Input
Crystal
24dBm
1st LO
Backend A/D ConverterSSI Dec.
Filter
CLK
Synth. LO
Synth. 2nd
LO
18MHz
CLK
IF Amp Crystal
109.65MHz
A
10 dB
Att.
450-520MHz
LNA High Pass 
Filter
LNA
ADC
ABACUS III IC
A 
						

							May 25, 20056881096C74-B
3-18Theory of Operation: Receiver Front-End
3.4.3.2  Preselector Filter
The front-end operates in the 450 to 520 MHz band. The front-ends primary function is to optimize 
half IF rejection, image rejection, and selectivity while providing the first conversion. The front-end 
uses a varactor-tuned filter that is tuned by the controller. The tuning signal is a DC control voltage 
between 0 and 9V that come from the PA power control section. Low voltages are for lower 
frequencies and higher voltages correspond to the higher frequencies. This filter is aligned in the 
factory and can also be aligned using the Tuner software.
3.4.3.3  Switchable 15 dB Attenuator
This circuit block can provide 0 dB or 15 dB of attenuation in the signal path. Normally, it is set for 
0 dB and does not affect the received signal. When strong signals are detected, the radio controller 
can choose to activate this attenuator to provide protection to the back end circuits, and to enhance 
high level intermodulation performance. Proprietary algorithms are used to control the switching.
3.4.3.4  Low-Noise Amplifier (LNA, U5302)
A diode (D5281) located after the varactor preselector and before the LNA protects the receiver from 
strong RF signals by limiting the signal amplitude going into the amplifier. The LNA is a low-noise 
monolithic IC providing ~ 15 dB of gain to the receiver. It is biased with 5 V. 
The UHF receiver also has a second LNA based on Q5252 that can be activated or bypassed by the 
radio software. This amplifier is protected by D5280 and provides 11 dB of gain.
3.4.3.5  Image Filter 
Following the LNA (U5302), the signal goes through a bandpass filter before it is sent to the mixer. 
The passband is from 450 to 520 MHz with an insertion loss of about 2 dB, while the image rejection 
is 55 dB. There is a trap on the input side of this filter to attenuate the 109.65 MHz IF.
3.4.3.6  Mixer
A passive double-balanced diode ring mixer is used to down-convert the received signal to an 
Intermediate Frequency (IF) of 109.65 MHz. The mixer is designed to provide low conversion loss (< 
7.0 dBm) and high intermodulation performance and requires a strong injection signal. The mixer is 
driven by the receiver injection buffer, a two-stage LDMOS IC design, that amplifies the +3 dBm 
high-side injection signal from the Frequency Generation Unit (FGU) to +24 dBm. 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Receiver Front-End3-19
3.4.4 700–800 MHz Band
The receiver circuits primary duties are to detect, filter, amplify, and demodulate RF signals in the 
presence of strong interfering noise and unintended signals. The receiver (see Figure 3-16) is 
broken down into the following blocks:
• Front-end, which includes:
- Preselector filters
- Low-noise amplifier (LNA)
- First mixer
•IF
• Back-end
Figure 3-16.  Receiver Front-End and Back-End (700–800 MHz)
3.4.4.1  Preselector Filters
The front-end operates in the 700 MHz and 800 MHz bands. The front-ends primary function is to 
optimize image rejection and selectivity while providing the first conversion. The front- end uses fixed 
ceramic-filter technology. There are two sets of filters: (B6250 and B6252) for the 800 MHz band and 
(B6251 and B6253) for the 700 MHz band. These filters are switched between bands by a network of 
diode switches (D6251 thru D6257) biased by RLC networks (C6254, C6260, R6254, and L6254) 
that also act as RF chokes. The first filter is a dual-switched filter that reduces the image-frequency 
response and limits some of the out-of-band interferers. The second filter following the monolithic 
low-noise amplifier (LNA) provides additional image rejection.
3.4.4.2  Low-Noise Amplifier (LNA, U6250)
A diode (D6258) located after the first preselector and before the LNA protects the receiver from 
strong RF signals by limiting the signal amplitude going into the amplifier. The LNA is a low-noise 
monolithic IC providing ~ 16 dB of gain to the receiver. It is biased with 5 V at pins 1 and 6. The input 
matching consists of an LC network (C6288, L6258) for optimal gain.
LNA Ant. SW.
Harm. FLT
Mixer Preselect 2
Preselect 1 RF Input
Crystal
15dBm
1st LO
Backend A/D ConverterSSI Dec.
Filter
CLK
Synth. LO
Synth. 2nd
LO
18MHz
CLK
IF Amp Crystal
73.35MHz
A
700MHz
800MHz
MAEPF-27905-O
ADC
ABACUS III IC 
						

							May 25, 20056881096C74-B
3-20Theory of Operation: Receiver Back-End
3.4.4.3  Mixer (U6251)
The monolithic, passive mixer IC down-converts the received signal to an Intermediate Frequency 
(IF) of 73.35 MHz. The mixer is designed to provide low conversion loss (< 7.0) and high 
intermodulation performance. To improve the performance of the mixer in both bands, a shunt 9.1 pF 
capacitor (C6297) along with a resistive PI network (R6278, R6280, R6281) is designed at the IF 
port (pin 5) of the mixer. The mixer is driven by the receiver injection buffer, a two-stage discrete/IC 
design used with the VCO to efficiently drive the mixer over temperature with minimum power 
variation. The injection buffer provides 15 dBm to the mixer. The VCO does high-side injection for 
the 800 MHz band and low-side Injection for the 700 MHz band.
3.5 Receiver Back-End
This section discusses the receiver back-end (RXBE) components and detailed theory of operation. 
The receiver back-end processes the down-converted, filtered IF signal to produce digital data for 
final processing by the Patriot microcontroller IC.
3.5.1 VHF (136-174 MHz) Band
The receiver back-end contains the following major components:
• Intermediate frequency (IF) section.
• ABACUS III IC
3.5.1.1  Intermediate Frequency (IF) Section
The XTL 5000 radio uses two leadless, surface-mount, two-pole, third-overtone, quartz crystal filters 
(Y3400, Y3401) separated by a 21 dB gain IF amplifier. The filters are centered at 109.65 MHz. This 
narrowband bandpass filter contributes to the radio’s adjacent-channel and alternate-channel 
rejection performance. Components L3401, L3403, L3404, L3405, C3421, C3414, C3409, C3416, 
C3420, C3418 and C3415 are used as impedance-matching networks. Components Q3400, R3409, 
R3401, R3402, R3405, R3407, and R3413 are used for biasing and stabilizing the transistor Q3400. 
Components C3424, C3404 bypass the DC supply. L3400 is RF choke. Diode D3400 and Inductor 
L3408 protect the Abacus and the second IF filter from strong In-band signals.
3.5.1.2  ABACUS III IC
The receiver back-end is designed around the ABACUS III (AD9874 IF digitizing subsystem) IC and 
its associated circuitry. The AD9874 (Figure 3-17 on page 3-21) is a general-purpose, IF subsystem 
that digitizes a low-level, 10–300 MHz IF input with a bandwidth up to 270 kHz. The signal chain of 
the AD9874 consists of a variable gain, low-noise amplifier, a mixer; a bandpass, sigma-delta, A/D 
converter; and a decimation filter with programmable decimation factor. An automatic gain control 
(AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment. The high dynamic 
range and inherent anti-aliasing provided by the bandpass, sigma-delta converter allow the AD9874 
to cope with blocking signals 80dB stronger than the desired signal. Auxiliary blocks include clock 
and LO synthesizers, as well as an SPI port. Input signal RXIF is the 109.65 MHz IF from the IF 
section in the receiver front-end.
Components C3000, C3038, and L3002 match the input impedance from 50 ohms (IF Filter 
terminating impedance) to the ABACUS III IC input IFIN. Formatted SSI data is output to the Patriot 
microcontroller IC for DSP processing on ports FS, DOUTA, and CLKOUT. Control logic is sent to 
the ABACUS III IC from the Patriot microcontroller via the SPI lines (PC, PD, PE). 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Receiver Back-End3-21
Figure 3-17.  ABACUS III (AD9874) IC Functional Block Diagram from Data Sheet (VHF)
3.5.1.2.1  Second Local Oscillator
The ABACUS III IC local oscillator (LO) synthesizer controls the second LO. Signal FREF is the 
16.8 MHz reference from the frequency generation unit (FGU). The second LO frequency is 
107.4 MHz by default, or 111.9 MHz in special cases as necessary to avoid radio self-quieters. The 
second LO signal mixes with IFIN to produce a 109.65 MHz final IF. The external VCO consists of 
transistor Q3000, together with its bias and instability network and tank elements. Darlington 
transistor Q3001 along with C3035 and C3017 form an active DC filter. The second-order loop filter 
is comprised of C3044, C3005, and R3009.
3.5.1.2.2  Sampling Clock Oscillator
The ABACUS III IC sampling clock synthesizer, at Fclk=18 MHz (IF2=Fclk/8, where Fclk is the clock 
rate), utilizes a negative-resistance core that is internal to the ABACUS III IC which, when used in 
conjunction with an external LC tank (made up of L3003 and C3039) and a varactor (D3001), serves 
as the VCO.
3.5.2 UHF Range 1 (380-470 MHz) Band
The receiver back-end (see Figure 3-14 on page 3-15) contains the following major components:
• Intermediate frequency (IF) filter
• ABACUS III IC
IFIN
FREF-16dB
LNA
LO
Synth.Sample Clock
Synthesizer
CLK VCO and
Loop Filter LO VCOand
Loop FilterVoltage
Reference DAC AGC
ADCDecimation
FilterFormatting/SSI
Control Logic f
CLK = 13-26MHz
SPIDOUTB DOUTA
FS
CLKOUT
MXON MXOP
IF2P
IF2N
GCP
GCN LOP IOUTL
LON
IOUTC
CLKP
CLKN
VREFP
VCM
VREFN
PC
PD
PE
SYNCB
MAEPF-27817-O
AD9874 
						

							May 25, 20056881096C74-B
3-22Theory of Operation: Receiver Back-End
3.5.2.1  Intermediate Frequency (IF) Filter
The XTL 5000 radio uses two leadless, surface-mount, two-pole, third-overtone, quartz crystal filters 
(Y5400, Y5401) separated by a 20 dB gain IF amplifier. The filter is centered at 109.65 MHz. This 
narrow-bandpass filter gives the radio part of its adjacent-channel and alternate-channel rejection 
performance. Impedance-matching networks are located at the input and output of each crystal. The 
IF amplifier is made with Q5401. The 10 dB attenuator (U5400) located after the second crystal filter 
is controlled by the software to limit the signal gain in front of the ABACUS III IC.
3.5.2.2  ABACUS III IC (U5002)
The receiver back-end is designed around the ABACUS III (AD9874 IF digitizing subsystem) IC and 
its associated circuitry. The AD9874 (Figure 3-18) is a general-purpose, IF subsystem that digitizes a 
low-level, 10-300 MHz IF input with a bandwidth up to 270 kHz. The signal chain of the AD9874 
consists of a variable gain, low-noise amplifier, a mixer; a bandpass, sigma-delta, A/D converter; and 
a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit 
provides the AD9874 with 12 dB of continuous gain adjustment. The high dynamic range and 
inherent anti-aliasing provided by the bandpass, sigma-delta converter allow the AD9874 to cope 
with blocking signals 80 dB stronger than the desired signal. Auxiliary blocks include clock and LO 
synthesizers, as well as an SPI port. Input signal RXIF is the 109.65 MHz IF from the IF filter.
Components C5002, C5007, and L5002 match the input impedance from 50 ohms (IF Filter 
terminating impedance) to the ABACUS III IC input IFIN. Formatted SSI (synchronous serial 
interface) data is output to the Patriot microcontroller IC for DSP processing on ports FS, DOUTA, 
and CLKOUT. Control logic is sent to the ABACUS III IC from the Patriot microcontroller via the SPI 
lines (PC, PD, PE).
Figure 3-18.  ABACUS III (AD9874) IC Functional Block Diagram from Data Sheet (UHF Range 1)
IFIN
FREF-16dB
LNA
LO
Synth.Sample Clock
Synthesizer
CLK VCO and
Loop Filter LO VCOand
Loop FilterVoltage
Reference DAC AGC
ADCDecimation
FilterFormatting/SSI
Control Logic f
CLK = 13-26MHz
SPIDOUTB DOUTA
FS
CLKOUT
MXON MXOP
IF2P
IF2N
GCP
GCN LOP IOUTL
LON
IOUTC
CLKP
CLKN
VREFP
VCM
VREFN
PC
PD
PE
SYNCB
MAEPF 27817 O
AD9874 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Receiver Back-End3-23
3.5.2.2.1  Second Local Oscillator (LO)
The ABACUS III IC local oscillator (LO) synthesizer controls the second LO. Signal FREF is the 
16.8 MHz reference from the frequency generation unit (FGU). The second LO frequency is 
107.4 MHz by default, or 111.9 MHz in special cases as necessary to avoid radio self-quieters. The 
second LO signal mixes with IFIN to produce a 2.25 MHz final IF. The external VCO consists of 
transistor Q5002, together with its bias and instability network and tank elements. Darlington 
transistor Q5001 along with C5018 and C5050 form an active DC filter. The 2nd order loop filter is 
comprised of C5044, C5045, and R5013.
3.5.2.2.2  Sampling Clock Oscillator
The ABACUS III IC sampling clock synthesizer, at Fclk=18 MHz (IF2=Fclk/8, where Fclk is the clock 
rate), utilizes the clock VCO built around Q5003.
3.5.3 UHF Range 2 (450-520 MHz) Band
The receiver back-end (see Figure 3-15 on page 3-17) contains the following major components:
• Intermediate frequency (IF) filter
• ABACUS III IC
3.5.3.1  Intermediate Frequency (IF) Filter
The XTL 5000 radio uses two leadless, surface-mount, two-pole, third-overtone, quartz crystal filters 
(Y5400, Y5401) separated by a 20 dB gain IF amplifier. The filter is centered at 109.65 MHz. This 
narrow-bandpass filter gives the radio part of its adjacent-channel and alternate-channel rejection 
performance. Impedance-matching networks are located at the input and output of each crystal. The 
IF amplifier is made with Q5401. The 10 dB attenuator (U5400) located after the second crystal filter 
is controlled by the software to limit the signal gain in front of the ABACUS III IC.
3.5.3.2  ABACUS III IC (U5002)
The receiver back-end is designed around the ABACUS III (AD9874 IF digitizing subsystem) IC and 
its associated circuitry. The AD9874 (Figure 3-19 on page 3-24) is a general-purpose, IF subsystem 
that digitizes a low-level, 10-300 MHz IF input with a bandwidth up to 270 kHz. The signal chain of 
the AD9874 consists of a variable gain, low-noise amplifier, a mixer; a bandpass, sigma-delta, A/D 
converter; and a decimation filter with programmable decimation factor. An automatic gain control 
(AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment. The high dynamic 
range and inherent anti-aliasing provided by the bandpass, sigma-delta converter allow the AD9874 
to cope with blocking signals 80 dB stronger than the desired signal. Auxiliary blocks include clock 
and LO synthesizers, as well as an SPI port. Input signal RXIF is the 109.65 MHz IF from the IF filter.
Components C5002, C5007, and L5002 match the input impedance from 50 ohms (IF Filter 
terminating impedance) to the ABACUS III IC input IFIN. Formatted SSI (synchronous serial 
interface) data is output to the Patriot microcontroller IC for DSP processing on ports FS, DOUTA, 
and CLKOUT. Control logic is sent to the ABACUS III IC from the Patriot microcontroller via the SPI 
lines (PC, PD, PE). 
						

							May 25, 20056881096C74-B
3-24Theory of Operation: Receiver Back-End
Figure 3-19.  ABACUS III (AD9874) IC Functional Block Diagram from Data Sheet (UHF Range 2)
3.5.3.2.1  Second Local Oscillator (LO)
The ABACUS III IC local oscillator (LO) synthesizer controls the second LO. Signal FREF is the 
16.8 MHz reference from the frequency generation unit (FGU). The second LO frequency is 
107.4 MHz by default, or 111.9 MHz in special cases as necessary to avoid radio self-quieters. The 
second LO signal mixes with IFIN to produce a 2.25 MHz final IF. The external VCO consists of 
transistor Q5002, together with its bias and instability network and tank elements. Darlington 
transistor Q5001 along with C5018 and C5050 form an active DC filter. The 2nd order loop filter is 
comprised of C5044, C5045, and R5013.
3.5.3.2.2  Sampling Clock Oscillator
The ABACUS III IC sampling clock synthesizer, at Fclk=18 MHz (IF2=Fclk/8, where Fclk is the clock 
rate), utilizes the clock VCO built around Q5003.
3.5.4 700–800 MHz Band
The receiver back-end (see Figure 3-16 on page 3-19) contains the following major components:
• Intermediate frequency (IF) filter
• ABACUS III IC
IFIN
FREF-16dB
LNA
LO
Synth.Sample Clock
Synthesizer
CLK VCO and
Loop Filter LO VCOand
Loop FilterVoltage
Reference DAC AGC
ADCDecimation
FilterFormatting/SSI
Control Logic f
CLK = 13-26MHz
SPIDOUTB DOUTA
FS
CLKOUT
MXON MXOP
IF2P
IF2N
GCP
GCN LOP IOUTL
LON
IOUTC
CLKP
CLKN
VREFP
VCM
VREFN
PC
PD
PE
SYNCB
MAEPF 27817 O
AD9874