Motorola Astro Digital Mobile Radio Xtl5000 Detailled 6881096c74 B Manual

							6881096C74-BMay 25, 2005
Theory of Operation: Controller Section3-65
3.8.2 Controller DC Power Distribution
Figure 3-45 illustrates the controller DC power distribution circuitry.
The A+ power for the radio is derived from the 12-V battery, which is applied to the main board 
through connector J0950. This A+ voltage is routed to the control-head connector, J0401, pins 19 
and 21, to the control head.
A power FET (Q51) provides the means of controlling the main power source (SWB+) by the on/off 
switch. SWB+ is routed back to the main board through connector J0401-17 and out the rear 
connector, J2-24.
SW_B+ turns on controller FET switch Q0503, which supplies SW_A+ to regulator U0500. This 9.3-
V regulator powers up the main 5-V controller regulator U0503. The 5-V supply powers on all four 
controller regulators:
• U0962 (3.0 V) for the power control section
• U0503 (2.85 V) for the controller and daughtercard I/O
• U0507 (1.85 V) for the memory
• U0502 (1.55 V) for the microprocessor core.
The SW+5-V regulator is the main power source for the controller.
Figure 3-45.  B+ Routing for Controller Section
On the secure interface board, U800, Q802, and Q803 provide SWB+ to the encryption module (if 
equipped). The SWB+ and UNSWB+ encryption voltages both originate from the secure interface 
board and are fed to the encryption module via J0701 and J0501.
It should also be noted that a system reset is provided by the undervoltage detector, U0504. This 
device brings the system out of reset on power-up, and provides a system reset to the 
microcomputer on power-down.
3V, 2.8V,
1.8V, 1.5V
Regulators PATRIOT
CORE
U100
PATRIOT
EIM
U1008MB
FLASH
U102IMB
SRAM
U103VIP’s SB9600
CircuitRS232
Transceiver
U0305 Audio PA
Digital POT
U0206
5V
Regulator
U0503
FET (Q0952),
Power Ctrl
Loop
VCORX/FGU
5V Reg
9V
Regulators
U0950, U0951
U0500 Rear Acc’y  Conn
(J2/J0402), Radio Turn
On/Off (Q0503 circuit),
Secure IF Board (J0501)
Audio PA
U0204Control
HeadSecure IF
Board
J0500SW_A+
FET
Q0503
A+SW_A+
SW_B+9.3V - FGU 9.3V - Controller
9.3V - TX
Unsw 5V = 5.0V Vcc = 3.0VVcc2.8 = 2.85V Vcc1.8 = 1.85VVcc1.5 = 1.55V
Vcc5 = 5.0V
ADC
U0953
EMERG
Timer
U0506 Secure IF
Board
J0500USB
XCVR
U0304Mic Amp  Ckt
U0201, U0202,
Codec-U0200
Patriot I/O
SSI, SPI,
BBP, UARTs
U100Misc. gates,
buffers, etc.Modulation
DAC-U0900,
Urchin-U0901
DAC
U0959Power Control
Digital POT
U0952
MAEPF-27892-O 
						

							May 25, 20056881096C74-B
3-66Theory of Operation: Controller Section
The various voltages used by the ICs on the main board are shown in Table 3-13.
3.8.3 Encryption Voltages 
The secure interface board produces two voltages sourced by A+ and SW_B+ through J0501, pins 
10 and 9, that are used by the encryption module: UNSW_B+_ENC (7 V) and SW_B+_ENC (7 V). 
The constant 7 V is generated using U800, Q802, and Q803 and is fed to J0701. At the secure 
interface board, the 7 V provides continuous unswitched voltage when the vehicular battery is 
connected to the radio and is also switched to provide SWB+ to the encryption module. A 5-V 
storage circuit, C810 (0.47-farad capacitor), provides +5 Vdc to the encryption module via J0701, pin 
12, to hold encryption keys for a period of three days with no A+ voltage present. The 5 V and 2.85 V 
controller supplies are used to provide logic translation between the legacy keyloader data (5 V) and 
the universal crypto module (UCM) (3 V). The secure interface board also supplies the UCM chip-
select logic line and the other control lines, clocks, and other components, to the main board 
microprocessor.Table 3-13.  Integrated Circuits Voltages
Integrated CircuitUNSW5VSW 5VA+3.0 V2.85 V9.3 V_T
X1.85 V1.55 V
Patriot 
MicroprocessorU100U100U100
FlashU102
SRAMU103
A/DU0953-28
D/AU0959-4
Modulation D/AU0900-3
FL0900-4
UrchinU0901
RS-232 XCVRU0305-16
USB XCVRU0304-7
Audio PAU0204-7
CODECU200-6
Amplifiers, EPOTsU0201-4
U0202-3
555 TimerU0506-4
SB9600 MUXU606-16
Vo l u m e  Po tU0206-7
32K CrystalY0100-5
Modulation MUXU0902-16
Power ControlU0956-4
U0957-4
U0960-4
Keyed 9.1 V SwitchQ0952 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Controller Section3-67
3.8.4 Reset Circuits
The reset circuits consist of the power-on reset (POR*) circuit (Figure 3-46), SW_B+ sense circuit, 
and SB9600 bus reset circuit. These circuits allow the microprocessor to recover from an unstable 
condition, such as removing battery A+ from the radio while it is on, battery voltage too low, and 
miscommunication to remote devices on the SB9600 bus, as well as generally monitoring the power 
on/off condition.
Figure 3-46.  Power-On Reset Circuit
The SW_B+ and A+ voltage levels are sensed by the comparator circuit consisting of U0604, Q0505, 
and R0505, R0506, R0508, and R0509. When SW_B+ goes below 8.5 V or SW_A+ goes below 
10 V, U0604-7, SW B+ Sense, goes low. When this occurs, the radio completes its soft power-down 
and eventually drives the Soft_Turn_Off line low, which turns off Q0502 and FET Q0503. This turns 
off SW_A+ and eventually turns off the 9-V, 5-V, 3-V, 2.85-V, 1.85-V, and 1.55-V regulators.
The POR* circuit consists of a wired-OR circuit of the error output lines from the 2.85-V, 1.85-V, and 
1.55-V regulators, which indicates a failure of either of these regulators; and a reset output from a 
4.2-V detector IC U0504. When either of the regulators fails or the 5-V supply begins to drop below 
4.2 V, POR* is asserted low, resetting the microprocessor U100 at U001, LV_DETECT.
When the radio is operating correctly (A+ > 10 V and SW_B+ > 8.5 V), SW_A+ and VOCON 
regulators U0501, U0502, and U05007 are at normal voltage. The POR* line and SW_B+_Sense are 
high (2.85 V).
1.85V
Reg. Out
U05072.85V
Reg. Out
U05011.55V
Reg. Out
U0502
5VSW_A+
SW_B+U0604 SW_B+
Soft_Turn_Off
EmergencyQ0505SW_A+
A+
B+_CNTLTo 9.3V Regulators
(U0500......)
SWB+ _Sense
To Microprocessor
To Microprocessor 2.85V
POR
(LV_DETECT)
+
-
MAEPF-27826-O
4.2V
Detector
U05
FET 
						

							May 25, 20056881096C74-B
3-68Theory of Operation: Controller Section
The other signal that can cause a processor/radio reset is the SB9600 RESET line. The RESET line 
is driven high (5 V) by a remote device that is having problems communicating with the processor.
3.8.5 Power-Up/Power-Down Sequence
The XTL 5000 radio power is cycled via SW_B+ (battery voltage level). This voltage is supplied by 
the control head via J0401, pin 17, when the On/Off button is cycled.SW_B+ is derived from the 
battery A+ voltage via a power FET in the control head (W5 and W7 models).
3.8.5.1  Power Turn-On
When SW_B+ is active at turn-on time, the voltage turns on Q0501, Q0504, and Q0505, which then 
turns on SW_A+ via the power FET Q0503. SW_A+ then supplies all radio power (9.3-V regulators 
and controller regulators). SW_A+ is derived the same way SW_B+ is at the control head.
SW_B+ is also sent to the comparator circuit, U0604, which allows the processor to monitor its level 
via SW_B+_Sense (active high). When SW_B+ is sensed “on” by the processor, it asserts high an 
output line, Soft_Turn_Off, to the wired-OR turn-on circuit at Q0502. This active-high processor 
output is required for performing a soft power-down. 
3.8.5.2  Power Turn-Off
At turn-off, SW_B+ becomes inactive at the control heads. As this voltage falls below 8.5 V, the 
U0604 comparator circuit drives SW_B+_Sense low, telling the processor to power down the radio. 
The processor eventually de-asserts low the SOFT_TURN_OFF signal after keeping the wired-OR 
turn-on circuit, and thus SW_A+ and all radio power, on long enough to perform a soft power-down, 
which includes deaffiliating on a trunked system, saving radio status parameters, etc. Once the 
SW_B+ and SOFT_TURN_ON lines are both low, Q0502 and Q0504 turn off, which provides a low 
at power FET Q0503. This turns off SW_A+, which removes all radio power.
3.8.5.3  Emergency Power-Up/-Down Sequence
The emergency input is provided to enable the radio transceiver to be activated, regardless of the 
state of the control head’s On/Off switch. The emergency input is activated by opening the normally 
grounded footswitch connected to either J0401, pin 18, or J0402, pin 28, of the controller. This input 
is routed to Q0501 and to the same wired or turn-on circuit and SW_A+ FET.
Under normal configurations, the output of Q0501 goes low to trigger pin 2 of a monostable vibrator 
U0506 causing the output pin 3 to go high. This enables the regulators through D0501 and Q0502. It 
also enables the EMERG_SENSE line to the MCU through U0508-1. The monostable vibrator is a 
timeout timer that holds the regulators on for 300 ms. This delay is required to allow the MCU to 
initiate its start-up vectors and poll the EMEG_SENSE line J17 of U0001. The MCU takes control of 
the regulators through D0501 and Q0502 by holding SOFT_TURN_OFF high.
The emergency active state depends on the emergency polarity into the timer. Normally with Q0501 
present, emergency is active with the footswitch open. Removing Q0501 and adding R0527 causes 
the emergency to go active with the switch closed.
3.8.6 MCU and DSP System Clocks
The MCU within the Patriot IC (U100) needs two clocks for proper operation. A 16.8 MHz sine-wave 
reference is provided at the CKIH (A6) pin of the Patriot IC. The source of this clock is a 16.8 MHz 
oscillator and its associated filtering circuitry. This clock is also provided to the Urchin IC (U0901). 
The MCU has the capability of running at higher clock rates, which are programmable and based on 
this 16.8 MHz reference. The DSP within the Patriot IC also uses the 16.8 MHz provided at the CKIH 
(A6) pin as a reference. 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Controller Section3-69
The Patriot IC also requires a 32 kHz square-wave clock, provided at the CKIL (J7) pin. This clock is 
generated by a 32 kHz crystal (Y0100), with supporting circuitry for oscillation. This clock is utilized 
only for the Patriot IC, and is used for reset capability and other Patriot IC functions.
Four additional clocks are also supplied to the daughtercard: a 20 kHz RX frame-sync clock, a 
48 kHz TX frame-sync clock, a 1.2 MHz RX data clock, and a 2.4 MHz TX data clock. The 
microprocessor also generates the digital audio bus clocks: a 512 kHz data clock and an 8 kHz 
frame-sync clock.
3.8.7 RS-232 USB Bus
The XTL 5000 microcontroller in the Patriot IC (U100) has two internal UARTS that can be 
configured for RS-232 data communication: UARTA and UARTB (Figure 3-47).
Figure 3-47.  Patriot IC (U100) UART Configuration
UARTA is configured for RS-232 data transmission by default, and its data transmission is routed 
through an on-board RS-232 transceiver (U0305) to bring the data voltage levels up to EIA RS-232 
standards before the data exits the front and rear of the radio. The U0305 is a two-driver, two-
receiver device, protected against ±15 kV electrostatic discharges.
For data output, UARTA transmits data from the microcontroller at 0-V and 2.85-V levels. This data is 
sent on an asynchronous serial bus, which is routed to an on-board RS-232 transceiver (U0305) that 
converts these low-voltage levels to -9 V and +9V signal levels. This RS-232-formatted data is 
routed out the front of the radio (J0401-27, J0401-28, J0401-29, J0401-30) and to the rear of the 
radio (J0402-7, J0402-8, J0402-9, J0402-10).
For data input, U0305 can accept up to ±30-V signal levels. These high levels are converted inside 
the U0305 down to 0-V and 5-V levels. Next these data levels are routed thru a buffer stage (U0303) 
which lowers the data to 0-V and 2.85-V levels. This is the required voltage levels for the input into 
the microcontroller.
PATRIOT
U100
UART A UART  B
MUX
SWITCHSB9600
Circuit
Rear connector
(26-pin) - J2
Front connector
(50-pin) - J0401USB
XCVR
U0304
RS232
XCVR
U0305
Pins 31, 31, 33, 34
Pins 27, 28, 29, 30Pins 25, 26Pins 2, 3, 9, 8
Pins 7, 6, 12
Pins 4, 5, 10, 11 BUS+, BUS-, BUSY, RESET
USB+, USB-, USB_PWR
TXD, RXD, CTS, RTS Boot_TX, Boot_RX
MAEPF-27702-O 
						

							May 25, 20056881096C74-B
3-70Theory of Operation: Controller Section
This radio meets EIA compatibility with external data accessory devices. The naming scheme (see 
Table 3-14 and Table 3-15) used for the microcontrollers RS-232 lines sometimes conflict with EIA 
RS-232 naming schemes. This is due to the microcontrollers pin names versus I/O direction, 
compared to the EIA pin names versus I/O direction. Therefore, a matching naming scheme has 
been developed. If the pin is coming from the UART, the pin name has UART in the name. However, 
if you want to know how the EIA standard identifies the pin, a chart exists that provides the naming 
conversion. The shipping rear data cable automatically routes the pins according to the EIA 
standard, so interfacing to external data devices, such as computers, is done correctly. The naming 
scheme information is only needed when the rear connector is opened and the wires need to be 
identified for connection to a custom device. Note that the correct interfacing of RS-232 lines is 
output line to input line. For example, the TX pin of one device connects to the RX pin of the other 
device, and the RTS pin of one device connects to the CTS pin of the other device. Never connect 
TX to TX, RX to RX, and so on.
Table 3-14.  Rear Connector Naming Scheme
Radio Pin 
DirectionJ2 
Pin 
No.J2 Pin NamePin Alternate 
Name
EIA-
Compatible 
Name at 
Rear Conn. 
J2P2 Rear 
Accessory Cable 
DB9 (Female) = 
DCE InterfaceDB9 (Male) Serial 
Port Connector = 
DTE InterfaceData 
Device Pin 
Direction
Output 4 UARTA_TX No Change TX_DCE TX_DCE = pin 2
pin 2 = RX_DTE Input
Input 5 UARTA_RX No Change RX_DCE RX_DCE = pin 3
pin 3 = TX_DTE Output
Output 10 UARTA_CTS Becomes RTS RTS_DCE RTS_DCE = pin 8
pin 8 = CTS_DTE Input
Input 11 UARTA_RTS Becomes CTS CTS_DCE CTS_DCE = pin 7
pin 7 = RTS_DTE Output
Note: Connecting to a computer = DTE device
TX to RX and RTS to CTS
Table 3-15.  Remote-Mount Interconnect Board Connector Naming Scheme
Radio 
Pin 
Direc-
tionJ6 
Pin 
No.J2 Pin NamePin 
Alternate 
NameEIA-
Compatible 
Name at 
Rear Conn. 
J2P2 Rear 
Accessory Cable 
DB9 (Female) = 
DCE InterfaceHKN6122 Data 
Cable DB9 
(Female) = DCE 
InterfaceDB9 (Male) 
Serial Port 
Connector = 
DTE InterfaceData 
Device 
Pin 
Direc-
tion
Output 2 RS232_RXD Becomes 
TXTX_DCE pin 2 = TX_DCE TX_DCE = pin 2
pin 2 = RX_DTE Input
Input 3 RS232_TXD Becomes 
RXRX_DCE pin 3 = RX_DCE RX_DCE = pin 3
pin 3 = TX_DTE Output
Output 17 RS232_CTS Becomes 
RTSRTS_DCE pin 17 = RTS_DCE RTS_DCE = pin 8
pin 8 = CTS_DTE Input
Input 4 RS232_RTS Becomes 
CTSCTS_DCE pin 4 = CTS_DCE CTS_DCE = pin 7
pin 7 = RTS_DTE Output
Note: Connecting to a computer = DTE device
TX to RX and RTS to CTS 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Controller Section3-71
3.8.8 Serial Communications on the External Bus (SB9600)
The SB9600 bus is an asynchronous serial communication bus using a Motorola-proprietary 
protocol. It provides a means for the microcontroller within the Patriot IC (U100) to communicate with 
other hardware devices. In the radio, it communicates with hardware accessories connected to the 
accessory connector and the remote interface board. Serial communications on this external bus 
uses three of the four SB9600 lines: BUS+ (J0401-31), BUS- (J0401-32), and BUSY (J0401-33) data 
lines originating from the microcontrollers secondary UART.
These three lines are bidirectional; therefore, numerous devices can be in parallel on the bus. All 
devices monitor the bus while data is being transmitted at a 9600-baud rate. The transmitted data 
includes the address of the device for which the data is intended. Examples of the different types of 
data are: Button press/release data, sent to and from the radios microprocessor; control-head 
display data; and the existence of accessories on the bus, such as Siren or VRS. The use of these 
accessories requires the existence of SB9600 protocol on one of the radios data buses.
The microcontroller sends the data transmission from UARTB, onto the bus at 0-V and 2.85-V levels. 
Next, the software sets microcontroller SB96_RS232_EN to a logic HIGH. Buffers (U0602 and 
U0603) are now powered and the data is changed to the SB9600 format via pull-up and pull-down 
logic circuitry. SB96_RS232_EN also sets the data MUX (U0606) to route the new SB9600-
formatted data to the correct lines at the front of the radio (J0401-31, J0401-32, J0401-33, and 
J0401-34) and to the rear of the radio (J0402-3, J0402-4, J0402-5, and J0402-6). Since 
SB96_RS232_EN is kept HIGH as the default state, the UARTB default function is for SB9600 data 
traffic only. This is true for the radio in either dash- or remote-mount configuration.
When the microcontroller sends data onto the bus, the microcontroller monitors the transmitted data 
as a collision-detection measure. If a collision is detected as a result of receiving a different data 
pattern, the microcontroller will stop transmission and try again; that is, when the RESET line 
(J0401-34) is used.
Data bus drivers for the BUS+ and BUS- lines are differentially driven, having BUS- inverted from the 
state of BUS+. The drivers are so designed that any of the devices on the bus can drive these lines 
to their non-idle state without loading problems.
In a typical data transmission, the microcontroller examines the BUSY line. If the BUSY line is in the 
idle state, the microcontroller sets the BUSY line HIGH, and then it transmits using BUS+ and BUS-. 
At the end of the transmission, the microcontroller returns the BUSY line to idle.
The idle states for the SB9600 lines are: BUS+ = logic HIGH, BUS- = logic LOW, BUSY = logic LOW, 
and RESET = logic LOW.
3.8.9 Serial Peripheral Interface (SPI) Bus
The microcontroller (U100) utilizes an SPI bus for configuring and operating specific ICs in the 
controller and RF sections of the radio. The SPI bus is a synchronous serial bus made up of four 
lines (see Figure 3-48 on page 3-72). The CLK line is used to control the speed of the data to/from 
the IC and the microcontroller. If necessary, this clock speed can be adjusted to a different value for 
each IC.
The Data-OUT pin receives a data string from the microcontroller. The Data-IN pin sends a serial 
data string to the microcontroller, usually to indicate what the current programmed values are of the 
IC. The Chip Select pin is used to select which single IC is currently being programmed. Each ICs 
Chip Select pin is hardwired to a specific SPI bus and can only be controlled by that bus. The 
microcontroller pulls the ICs chip-select line LOW to enable the IC for receiving configuration data, 
for programming, or for sending out its existing configuration state. Additional SPI buses allow chip 
selecting to occur in parallel. Therefore, the operations on each SPI bus do not add any delay to the 
activities occurring on another SPI bus. 
						

							May 25, 20056881096C74-B
3-72Theory of Operation: Controller Section
Figure 3-48.  Serial Peripheral Interface (SPI) Block Diagram
The following ICs are controlled and programmed by SPI_A:
• ABACUS III (U6000): Sigma Delta A/D converter and 2nd LO frequency adjust. The 
ABACUS III IC has a single pin for both input and output. Therefore, additional circuitry (U0103 
and U0105) handles the SPI_MISO or the SPI_MOSI data lines from the microcontroller and 
allows a read or write operation to occur with the ABACUS III IC via a single bidirectional data 
line.
• A/D (U0953): monitors temperature, source voltage, PA current, feedback-voltage loop, 
forward-detected voltage, and reverse-detected voltage
• D/A (U0959) (microcontroller only writes to IC): controls bias stages 1-4, sets current limit, 
monitor thermistors, tuner overall RF power, and adjusts RX filter
• LV Frac-N (U6751) (microcontroller only writes to IC): scales the frequency from the VCO, 
control RX, and TX feedback loops
• EPOT (U0206) (microcontroller only writes to IC): controls the 32 steps of audio volume (vol=0: 
low to 15: high) that is routed to audio PA
3.8.10 Receive Audio
The controller processes all received signals digitally. This requires a unique back-end from a 
standard analog radio. This unique functionality is provided by the ABACUS III IC as the interface to 
the DSP. The ABACUS III IC (in the receive back-end section of the transceiver) provides a digital 
back-end for the receiver. It provides digital output data words at a 20 kHz sampling rate (refer to 
section “3.5. Receiver Back-End” for more details on ABACUS III IC operation). This data is passed 
to the DSP through the RX Baseband Interface Port (BBP). The SPI bus is used to configure the 
operation of the ABACUS III IC and is driven by the Patriot IC. ABACUS_DIN is the data line on 
which the RX data words are transferred from ABACUS III IC to the Patriot IC (refer to Figure 3-49 
on page 3-73).
PATRIOT
U100
QSCKA
MOSIA
SPICS8
MISOA
SPICS4
SPICS6SPICS9
SPICS5SCKA
MOSIA
SCKA
MISOA MOSIA
SYN_SEL* ABACUS3_CS*
 LV FRAC-N
 U6751 ABACUS
U6000
SCKA
MOSIA
MISOA
AD_EN*
A/D
U0953
SCKA
MOSIA
SCKA
EEPOT_3_CS* MOSIADA_EN*
LOG POT
U0206D/A
U0959
MAEPF-27820-O 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Controller Section3-73
Figure 3-49.  XTL 5000 RX Signal Path
The ABACUS III data is transferred to the Patriot IC at a 1.2 MHz bit rate, which is a synchronous 
clock provided by the ABACUS III IC. The 20 kHz interrupt clock, also provided by the ABACUS III 
IC, signals the arrival of a data packet and represents the sampling rate of the received data.
The DSP then processes this data to extract audio and signaling, perform filtering, alert-tone 
generation, etc. The DSP performs de-emphasis and discrimination before sending the discriminator 
data to the audio CODEC (U0200) via the SAP SSI bus. This bus is the digital audio bus consisting 
of the 512 kHz master bit clock (SAP_DCLK), and the 8 kHz frame sync (SAP_FSYNC). These 
clocks represent the data bit rate and sampling rate, respectively, for both the transmit and receive 
digital audio. For secure messages, the digital signal data must be passed to the secure module for 
decryption prior to DSP processing of the speaker data. The DSP transfers the data to and from the 
secure module through the SAP SSI port TXD and RXD signals. Configuration and mode control of 
the secure module is performed by the MCU through this bus.
The CODEC D/A analog output signal is routed to the RX_FILT_AUDIO line at both J0401 and 
J0402/J2 for legacy accessories and special applications products at an amplitude of 100 mV per 
kHz of deviation. The signal amplitude is independent of volume setting. This output is also routed to 
a multiplex switch, U0210, which is one source of audio to the audio PA speaker output. The 
alternate PA source, AUX_RX, is an input from J0401 and is used with vehicular repeater systems 
(VRS). The multiplexer output, normally received speaker audio, is routed to a volume control digital 
programmable potentiometer, U0206, and then to the audio PA (U0204) input. The audio PA output 
then drives the external speaker.
Patriot
U100
SPI
SAPBBP
RF IN
SPKR+
SPKR - 
CODEC
U0200ABACUS III
U6000
Volume Pot
U0206Audio PA
U0204
SCKA
SRDA
SCKASC0B
SRDB
SC1B S PI_SC
SPI_MOSI
SPI_MISO
MCLK
DT
FSRRO NEG1.2MHz
RX Data
20kHzABA_CLK
ABA_RXD
ABA_FSYNC
(J0401-4)
(J0401-4) 512kHz
TX Data
8kHzPDPC
MAEPF-27891-O 
						

							May 25, 20056881096C74-B
3-74Theory of Operation: Controller Section
The audio power amplifier (U0204), is a DC-coupled-output, bridge-type amplifier. The gain is 
internally fixed at 40 dB. Speaker audio leaves U0204 on pins 4 and 6. For dash-mount radios, the 
audio is routed to the speaker via J0402, pins 19, 21, 23, and 25, and then to J2, pins 20 and 26. The 
amplifier is biased to one-half of the A+ voltage. An audio isolation transformer must be used if 
grounded test equipment, such as an audio analyzer or service monitor, is to be connected to the 
speaker outputs.
Normally, R0220 pulls up U0204, pin 8, to SW_B+ to enable the audio PA. When the radio is 
squelched, the audio PA is muted by the microprocessor. Q0200 is enabled to provide approximately 
4.5 V through a voltage divider (Q0200 and R0222) to U0204, pin 8, which mutes the audio PA. 
When SW_B+ is turned off, the voltage from SW_A+ on U0204 falls below 2 V, placing the audio PA 
in standby, which turns off the U0204 output transistors to the speaker. Table 3-16 shows the 
voltages present at U0204, pin 8, during its various conditions.
3.8.11 Transmit Audio
The mobile microphone connects to the front of the control head through connector P104. 
Microphone audio (MIC_HI) enters the main board via J0401, pin 4, and is routed to multiplexer 
U0209 (refer to Figure 3-50 on page 3-75). Resistors R0200 and R0204 provide 9.6 Vdc bias voltage 
for the microphones internal circuitry.
The multiplexer allows TX modulation audio to be routed from one of 3 possible sources: mobile 
microphone (MIC_HI), AUX_MIC (audio sourced from the J2 rear accessory connector in motorcycle 
configuration), or AUX_TX (audio from a VRS). The resulting audio source is then sent to a two-
stage, programmable gain/attenuation circuit comprised of U0201 and U0202. The gain is 
accomplished via a programmable digital potentiometer in the amplifier circuit. This gain is 
adjustable via CPS and is programmed in ±3 dB steps. After passing through an anti-aliasing filter, 
audio is sent to the input of the CODEC (U0200) where it is digitized via its internal A/D converter. 
The digital audio data is then sent via the SAP SSI bus to the DSP at the Patriot IC. As with speaker 
data samples, the DSP reads the microphone audio samples and processes, pre-emphasizes, 
filters, and adds signaling information to this data. As with the received trunking data, low-speed 
transmit data is processed by the MCU and returned to the DSP. For secure messages, the digital 
signal data can be passed to the secure module prior to DSP processing and modulation. The DSP 
transfers the data to and from the secure module through the SAP SSI transmit (TXD) and receive 
(RXD) lines.The speaker outputs must NOT be grounded in any way.
Table 3-16.  PA Condition Voltages at U0204, Pin 8
Power Amplifier 
ConditionU0204 Pin 8
(Vdc)
Standby 0-2
Mute 3.3-6.4
Enabled 8.5-17
!
C a u t i o n