Motorola Astro Digital Mobile Radio Xtl5000 Detailled 6881096c74 B Manual

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-35
Power Detector
The power detector consists of a main microstrip transmission line that transfers power from the 
harmonic filter to the antenna and two parallel lines that are used to detect the forward and reverse 
power. The forward power detection line is terminated via R5707 and R5708. RF energy coupled 
onto this line is rectified and filtered via D5704 and C5715 to provide a DC voltage to the power 
control circuitry that is proportional to the forward transmitted power level. The detected forward 
voltage is approximately 1.5 Vdc when the radio is putting out 44 watts. Thermister R5704 
compensates for temperature changes in D5704 to maintain constant DC voltage versus detected 
forward power over temperature.
The reverse power detection line is terminated via R5705-06. RF energy coupled onto this line is 
rectified and filtered via D5705 and C5718 to provide a DC voltage to the power control circuitry that 
is proportional to the reverse power level reflected back from the antenna. Thermister R5712 
compensates for temperature changes in D5705 to maintain constant DC voltage versus detected 
reverse power over temperature.
3.6.2.4  Power Control (for 40W and 100W Transmitter)
The power control section is comprised of a control loop to level forward power, and protection 
mechanisms to reduce power to a safe level for the given environmental conditions (see Figure 3-28 
on page 3-36). 
						

							May 25, 20056881096C74-B
3-36Theory of Operation: Transmitter
Figure 3-28.  Power Control Components (UHF Range 1)
Power Control Loop
VFORWARD from the ON is buffered via the non-inverting, variable-gain stage U0956-2 whose gain 
is set by EPOT U0952. The proper gain is determined during power-detection calibration tuning. 
Buffered VFORWARD (U0956-2, Pin 7) is added to PWR_SET via R0971 and R0972 and then 
compared to a reference determined by R0974 and R0975. PWR_SET is supplied by the digital-to-
analog converter (DAC) U0959, Pin 2. Comparator stage U0956-3 increases or decreases 
RFPA_CNTRL so that the voltage at U0956-3, Pin 9 in the same at the reference voltage at U0956-
3, Pin 10. When the PWR_SET voltage is decreased, U0956-3 increases RFPA_CNTRL to increase 
VFORWARD which is proportional to forward power thus increasing the power level. When the 
PWR_SET voltage is increased, U0956-3 decreases RFPA_CNTRL to decrease VFORWARD, thus 
decreasing the power level. The microprocessor initiates the loop through U0958-1 and Q0954. 
Loop timing is set via software together with R0977 and C0973.
EEPOT
U0952
Q0954RFPA_CNTRL
(TO RFPA) U0957-4
U0957-4 U0956-3
Q0955 TEMP_2
(U0959, PIN 10)VTEMP
(FROM RFPA)PA_EN
CURR_LIM_SET
(U0959, PIN1)
VCURRENT
(FROM RFPA) 9.3V
9.3V
9.3V9.3V 9.3V9.3V
9.3V
VFORWARD
(FROM ON)PWR_SET
(U0959, PIN 2)D0950
D0951
1.5V
D0952
U0957-1 U0956-2
U0957-2 TEMP_1
(U0959, PIN 9)
+- +-+-
+- +- +-
+
-
MAEPF-27889-O 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-37
Protection Mechanisms
Final-stage temperature is sensed in the RFPA resulting in VTEMP, which is proportional to 
temperature. VTEMP is compared against a reference voltage TEMP_1 (U0959, pin 9) via U0957-1. 
When VTEMP exceeds TEMP_1, the U0957-1, pin 1, voltage increases and forward biases one of 
the D0951 diodes, which cuts back power. Power continues to cut back with rising temperature until 
the voltage level at the junction of R0978 and R0983 is high enough to forward bias D0952, thus 
clamping the cut back so that the radio meets its duty cycle specification while providing protection 
against high-temperature conditions. The clamping level is set via TEMP_2 (U0959, pin 10) and 
U0957-2. U0957-3 is used to sense if a high A+ battery voltage condition exists and, if it does, the 
Q0955 gate is biased on, which increases the clamp voltage allowing for additional power cutback 
for a high A+, high temperature condition.
Final-stage current is also monitored via VCURRENT, which is proportional to current. VCURRENT 
is compared against a reference CURR_LIM_SET (U0959, pin 1) which is tuned after power 
characterization. If VCURRENT exceeds CURR_LIM_SET, then U0957-4, pin 14, voltage rises and 
forward biases one of the D0951 diodes, which limits power.
Finally, control voltage is limited by U0956-4 and D0950. RFPA_CNTRL can rise to the control 
voltage limit set by R0942-4. U0965 provides protection against supply voltage transients. When 
transients on the A+ voltage exceed 24 volts U0965 pin 1 is pulled high thus turning on Q0954 via 
TX_DISABLE, R0932, U0958 disabling the control voltage to the PA first stage and momentarily 
turning off the transmitter. In addition, Q0900 is turned on, forward biasing one of the D0950 diodes 
and thus reducing the control voltage. When the voltage transient drops back below 20 volts, U0965 
pin 1 goes low thus enabling the control loop and turning the transmitter on again.
3.6.3 UHF Range 2 (450-520 MHz) Band
3.6.3.1  45-Watt Transmitter
The following text discusses the 45-W transmitter.
3.6.3.1.1  RF Power Amplifier (RFPA)
The RFPA consists of three gain stages, which are shown in Figure 3-29.
Figure 3-29.  45-Watt RF Power Amplifier (RFPA) Gain Stages (UHF Range 2)
First Stage
The RFPA first stage provides gain that is determined by the control voltage, RFPA_CNTRL. This 
control voltage is generated in the power control section and is a function of the final-stage output 
power, temperature, and current, as well as the control and A+ voltage levels. See “3.6.3.1.3. Power 
Control” on page 3-39 for a detailed explanation of the power control section.
FIRST
STAGE
0.5mW
U5501
C65250mW
Q5502
15183.5W
Q5503
157051W
To Antenna
Switch
RFPA_CNTRLK9.1V
TRANSMIT
BUFFER
TX_INJ
From
FGU2mW
Q5501
C65
K9.1V
VGBIAS3A+
DRV_9.3V
VGBIAS1 VGBIAS2
FINAL
STAGE
RFPA_OUT DRIVER
STAGE 
						

							May 25, 20056881096C74-B
3-38Theory of Operation: Transmitter
The 0.5 mW TX_INJ signal is routed to the U5501 first stage device (Pin 16, RFIN) via C5508 to an 
integrated, wide-band input match. U5501 is a two-stage LDMOS device with a bandpass interstage 
match consisting of L5503, C5507, and C5509 routed between VD1 (pin 14) and G2 (pin 11). L5502 
and L5505 provide the K9.1V drain bias voltage for the first and second stages to VD1 (pin 14) and 
RFOUT1/2 (pins 6 and 7), respectively. The RFPA_CNTRL gate bias is provided to both stages 
internally via VCNTRL (pin 1). Both U5501 stages are operated Class A and the second-stage output 
power is approximately 250 mW.
Driver Stage
C5566, C5516, C5518 and a transmission line form a low-pass, interstage match that transfers 
power to the Q5502 LDMOS transistor. R5511-R5515 provide device stability, and R5527, C5556, 
C5525 and R5516 supply the VGBIAS3 gate bias. L5508, C5527, R5517, E5501 and C5526 form 
the 9.3 V drain bias circuit. The 9.3 V drain voltage is supplied from regulator U5570. The 9.3 V 
supply to the driver is only present during transmit and is disabled during receive via the K9.1V 
signal and Q5570. Q5502 is operated Class AB and its output power is approximately 3.5 W. 
Final Stage
C5559, C5560, C5535, C5538, and transmission lines form a low pass, splitter match that transfers 
power to the LDMOS final-stage transistor Q5503. Q5503 contains two transistors in a single 
package, each with its own gate and drain lead. R5530, R5533, R5534, R5536, R5538-R5545 
provide stability for Q5503. R5525, C5557, C5539 and R5520 supply the VGBIAS1 gate bias to 
Q5503-7 via U5504-2 pin7. R5526, C5558, C5540 and R5521 supply the VGBIAS2 gate bias to 
Q5503-6 via U5504-1 pin 1. Gate bias voltage to the final is adjusted dependant on the temeprature 
of Q5503. The output voltage from the temperature sensing IC, U5502-2,  is summed via R5550 and 
R5555 respectively with the gate bias voltage VGBIAS1 and VGBIAS2, via R5549 and R5554 
respectively. As the temeprature of the final device decreases the bias voltage applied to the gates of 
U5503 is reduced. L5510, C5549, R5523, E5502 and C5550 form the A+ drain bias circuit to Q5503-
2 and Q5503-3. C5542-43, C5545-46, C5548, C5551-53 and transmission lines form a low -pass 
combiner match that transfers approximately 51 W to the antenna switch. R5535 provides stability 
for Q5503. Q5503 operates Class AB. 
R5522 and U5503 comprise the final-stage, current-sense circuit that generates the VCURRENT 
voltage proportional to the final stage current. R5519 sets the circuit gain. U5502 generates the 
VTEMP voltage, which is proportional to the final-stage temperature. 
3.6.3.1.2  Output Network (ON)
The ON consists of the antenna switch, harmonic filter, and power detector (see Figure 3-30).
Figure 3-30.  Output Network Components (UHF Range 2)
RFPA_OUTANTENNA
SWITCHH-FILTERPOWER
DETECTOR
RF
CONNECTOR
From
RFPA51W
K9.1VVREVERSE
VFORWARDJ570144W
RX_IN 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-39
Antenna Switch
The antenna switch functions in two modes determined by the presence of K9.1V. The K9.1V switch 
bias is applied via L5701and C5702. When K9.1V is present, the switch is in TX mode. D5701, 
D5702 and D5703 are forward biased forming a low-loss path from the RFPA final stage to the 
harmonic filter and a 20 dB isolation path between the RFPA final stage and the RX front-end. 
Isolation is achieved via a quarter-wave transmission lines between D5701 - D5702 and between 
D5702 - D5703. C5709-10 resonates out the D5702-3 on inductance improving the isolation. When 
K9.1V is absent, the switch is in RX mode. D5701, D5702 and D5703 are reverse biased forming a 
low-loss path from the harmonic filter to the RX front-end and a 20 dB isolation path from the 
harmonic filter to the RFPA final stage. Isolation is achieved via the D5701 off resistance. L5702 
resonates out the D5701 off capacitance improving the isolation.
Harmonic Filter
The harmonic filter is a 7-element, equal-L Zolotarev quasi-lowpass filter consisting of C5712 and 
C5713, C5719 thru C5721 and L5706 thru L5708. L5712, C5711 and L5713, C5714 form two shunt 
zeros for extra attenuation at the second harmonic. C5708 acts as a DC block between the filter and 
the antenna switch. The filter provides approximately 60 dB of harmonic rejection. The harmonic 
filter together with the antenna switch provides approximately 0.7 dB insertion loss between the 
transmitter power amplifier and the antenna.
Power Detector
The power detector consists of a main microstrip transmission line that transfers power from the 
harmonic filter to the antenna and two parallel lines that are used to detect the forward and reverse 
power. The forward power detection line is terminated via R5707 and R5708. RF energy coupled 
onto this line is rectified and filtered via D5704 and C5715 to provide a DC voltage to the power 
control circuitry that is proportional to the forward transmitted power level. The detected forward 
voltage is approximately 1.5 Vdc when the radio is putting out 44 watts. Thermister R5704 
compensates for temperature changes in D5704 to maintain constant DC voltage versus detected 
forward power over temperature.
The reverse power detection line is terminated via R5705-06. RF energy coupled onto this line is 
rectified and filtered via D5705 and C5718 to provide a DC voltage to the power control circuitry that 
is proportional to the reverse power level reflected back from the antenna. Thermister R5712 
compensates for temperature changes in D5705 to maintain constant DC voltage versus detected 
reverse power over temperature.
3.6.3.1.3  Power Control
The power control section is comprised of a control loop to level forward power, and protection 
mechanisms to reduce power to a safe level for the given environmental conditions (see Figure 3-31 
on page 3-40). 
						

							May 25, 20056881096C74-B
3-40Theory of Operation: Transmitter
Figure 3-31.  Power Control Components (UHF Range 2)
Power Control Loop
VFORWARD from the ON is buffered via the non-inverting, variable-gain stage U0956-2 whose gain 
is set by EPOT U0952. The proper gain is determined during power-detection calibration tuning. 
Buffered VFORWARD (U0956-2, Pin 7) is added to PWR_SET via R0971 and R0972 and then 
compared to a reference determined by R0974 and R0975. PWR_SET is supplied by the digital-to-
analog converter (DAC) U0959, Pin 2. Comparator stage U0956-3 increases or decreases 
RFPA_CNTRL so that the voltage at U0956-3, Pin 9 in the same at the reference voltage at U0956-
3, Pin 10. When the PWR_SET voltage is decreased, U0956-3 increases RFPA_CNTRL to increase 
VFORWARD which is proportional to forward power thus increasing the power level. When the 
PWR_SET voltage is increased, U0956-3 decreases RFPA_CNTRL to decrease VFORWARD, thus 
decreasing the power level. The microprocessor initiates the loop through U0958-1 and Q0954. 
Loop timing is set via software together with R0977 and C0973.
EEPOT
U0952
Q0954RFPA_CNTRL
(TO RFPA) U0957-4
U0957-4 U0956-3
Q0955 TEMP_2
(U0959, PIN 10)VTEMP
(FROM RFPA)PA_EN
CURR_LIM_SET
(U0959, PIN1)
VCURRENT
(FROM RFPA) 9.3V
9.3V
9.3V9.3V 9.3V9.3V
9.3V
VFORWARD
(FROM ON)PWR_SET
(U0959, PIN 2)D0950
D0951
1.5V
D0952
U0957-1 U0956-2
U0957-2 TEMP_1
(U0959, PIN 9)
+- +-+-
+- +- +-
+
-
MAEPF-27889-O 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-41
Protection Mechanisms
Final-stage temperature is sensed in the RFPA resulting in VTEMP, which is proportional to 
temperature. VTEMP is compared against a reference voltage TEMP_1 (U0959, pin 9) via U0957-1. 
When VTEMP exceeds TEMP_1, the U0957-1, pin 1, voltage increases and forward biases one of 
the D0951 diodes, which cuts back power. Power continues to cut back with rising temperature until 
the voltage level at the junction of R0978 and R0983 is high enough to forward bias D0952, thus 
clamping the cut back so that the radio meets its duty cycle specification while providing protection 
against high-temperature conditions. The clamping level is set via TEMP_2 (U0959, pin 10) and 
U0957-2. U0957-3 is used to sense if a high A+ battery voltage condition exists and, if it does, the 
Q0955 gate is biased on, which increases the clamp voltage allowing for additional power cutback 
for a high A+, high temperature condition.
Final-stage current is also monitored via VCURRENT, which is proportional to current. VCURRENT 
is compared against a reference CURR_LIM_SET (U0959, pin 1) which is tuned after power 
characterization. If VCURRENT exceeds CURR_LIM_SET, then U0957-4, pin 14, voltage rises and 
forward biases one of the D0951 diodes, which limits power.
Finally, control voltage is limited by U0956-4 and D0950. RFPA_CNTRL can rise to the control 
voltage limit set by R0942-4. U0965 provides protection against supply voltage transients. When 
transients on the A+ voltage exceed 24 volts U0965 pin 1 is pulled high thus turning on Q0954 via 
TX_DISABLE, R0932, U0958 disabling the control voltage to the PA first stage and momentarily 
turning off the transmitter. In addition, Q0900 is turned on, forward biasing one of the D0950 diodes 
and thus reducing the control voltage. When the voltage transient drops back below 20 volts, U0965 
pin 1 goes low thus enabling the control loop and turning the transmitter on again.
3.6.4 700–800 MHz Band
3.6.4.1  35-Watt Transmitter
The following text discusses the 35-W transmitter.
3.6.4.1.1  RF Power Amplifier (RFPA)
The RFPA consists of three gain stages, which are shown in Figure 3-32.
Figure 3-32.  35-Watt RF Power Amplifier (RFPA) Gain Stages (700–800 MHz)
FIRST
STAGE
TX_INJ
From
FGU2mW
U6500
C65200mW
Q6520
15174WQ6540
9045M
Q6541
9045M42W
To Antenna
Switch
RFPA_CNTRLK9.1V
VGBIAS3A+
A+ A+
VGBIAS2 VGBIAS1
MAEPF-27887-O
FINAL
STAGE
RFPA_OUT DRIVER
STAGE 
						

							May 25, 20056881096C74-B
3-42Theory of Operation: Transmitter
First Stage
The RFPA first stage provides gain that is determined by the control voltage, RFPA_CNTRL. This 
control voltage is generated in the power control section and is a function of the final-stage output 
power, temperature, and current, as well as the control and A+ voltage levels. See “3.6.4.1.3. Power 
Control” on page 3-43 for a detailed explanation of the power control section.
The 2 mW TX_INJ signal is routed to the U6500 first-stage device (Pin 16, RFIN) via C6501 to an 
integrated, wide-band input match. U6500 is a two-stage LDMOS device with a bandpass interstage 
match consisting of L6502, C6506, and C6503 routed between VD1 (pin 14) and G2 (pin 11). L6501 
and L6500 provide the K9.1V drain bias voltage for the first and second stages to VD1 (pin 14) and 
RFOUT1/2 (pins 6 and 7), respectively. The RFPA_CNTRL gate bias is provided to both stages 
internally via VCNTRL (pin 1). Both U6500 stages are operated Class A, and the second-stage 
output power is approximately 200 mW.
Driver Stage
C6502, C6509, C6510, C6511, and a transmission line form a low-pass, interstage match that 
transfers power to the Q6520 LDMOS transistor. R6521-5 provide device stability, and R6520 and 
C6500 supply the VGBIAS1 gate bias. L6521-2, R6526-7, and C6521-5 form the A+ drain bias 
circuit. Q6520 is operated Class AB, and its output power is approximately 4 W.
Final Stage
C6541-2, C6544-5, C6547-8, and transmission lines form a bandpass, splitter match that transfers 
power to the LDMOS final-stage transistors Q6540 and Q6541. R6550-3, R6554-7, C6565-6, and 
R6559-60 provide stability for Q6540 and Q6541, respectively. R6540 and C6540 supply the 
VGBIAS1 gate bias to Q6540. R6543 and C6558 supply the VGBIAS2 gate bias to Q6541. L6542-3, 
C6559-60, and R6544 form the A+ drain bias circuit.
C6549-57 and transmission lines form a low-pass, combiner match that transfers approximately 
42 W to the antenna switch. Both Q6540 and Q6541 operate Class AB.
R6545-6, C6564, and U6541 comprise the final-stage, current-sense circuit that generates the 
VCURRENT voltage proportional to the final stage current. R6546 sets the circuit gain. U6540 
generates the VTEMP voltage, which is proportional to the final-stage temperature.
3.6.4.1.2  Output Network (ON)
The ON consists of the antenna switch, harmonic filter, and power detector (see Figure 3-33).
Figure 3-33.  Output Network Components (700–800 MHz)
RFPA_OUTANTENNA
SWITCHH-FILTERPOWER
DETECTOR
RF
CONNECTOR
From
RFPA42W
K9.1VVREVERSE
VFORWARDJ670038.5W
RX_IN
MAEPF-27888-O 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-43
Antenna Switch
The antenna switch functions in two modes, which are determined by the presence of K9.1V. The 
K9.1V switch bias is applied via L6700, L6702, and C6700. When K9.1V is present, the switch is in 
TX mode. D6701 and D6702 are forward biased forming a low-loss path from the RFPA final stage to 
the harmonic filter and a 20 dB isolation path between the RFPA final stage and the RX front-end. 
Isolation is achieved via a quarter-wave transmission line between D6701 and D6702. C6703 
resonates out the D6702 on inductance improving the isolation.
When K9.1V is absent, the switch is in RX mode. D6701 and D6702 are reverse biased forming a 
low-loss path from the harmonic filter to the RX front-end and a 20 dB isolation path from the 
harmonic filter to the RFPA final stage. Isolation is achieved via the D6701 off resistance. L6703 
resonates out the D6701 off capacitance improving the isolation.
Harmonic Filter
L6720-2, C6720-1, and two open-stub transmission lines form the seven-element, low-pass 
harmonic filter. The filter attenuates harmonics generated by the RFPA when the antenna switch is in 
TX mode and provides extra selectivity when the antenna switch is in RX mode.
Power Detector
The power detector consists of two asymmetric, coupled transmission lines and detection circuitry 
that detects forward and reverse power. C6730-1, D6730, L6730, R6730-3, and R6735-6 form the 
forward-power detector (VFORWARD), which is used for power leveling. C6732-3, D6731, L6731, 
R6737-9, and R6733-4 form the reverse-power detector (VREVERSE). C6734-5 provides additional 
harmonic attenuation. R6740 provides an electrostatic discharge path to protect the RFPA final stage 
device.
3.6.4.1.3  Power Control
The power control section is comprised of a control loop to level forward power, and protection 
mechanisms to reduce power to a safe level for the given environmental conditions (see Figure 3-34 
on page 3-44). 
						

							May 25, 20056881096C74-B
3-44Theory of Operation: Transmitter
Figure 3-34.  Power Control Components (700–800 MHz)
Power Control Loop
VFORWARD from the ON is buffered via the non-inverting, variable-gain stage U0956-2 whose gain 
is set by EPOT U0952. The proper gain is determined during power-detection calibration tuning. 
Buffered VFORWARD (U0956-2, Pin 7) is added to PWR_SET via R0971 and R0972 and then 
compared to a reference determined by R0974 and R0975. PWR_SET is supplied by the digital-to-
analog converter (DAC) U0959, Pin 2. Comparator stage U0956-3 increases or decreases 
RFPA_CNTRL so that the voltage at U0956-3, Pin 9 in the same at the reference voltage at U0956-
3, Pin 10. When the PWR_SET voltage is decreased, U0956-3 increases RFPA_CNTRL to increase 
VFORWARD which is proportional to forward power thus increasing the power level. When the 
PWR_SET voltage is increased, U0956-3 decreases RFPA_CNTRL to decrease VFORWARD, thus 
decreasing the power level. The microprocessor initiates the loop through U0958-1 and Q0954. 
Loop timing is set via software together with R0977 and C0973.
EEPOT
U0952
Q0954RFPA_CNTRL
(TO RFPA) U0957-4
U0957-4 U0956-3
Q0955 TEMP_2
(U0959, PIN 10)VTEMP
(FROM RFPA)PA_EN
CURR_LIM_SET
(U0959, PIN1)
VCURRENT
(FROM RFPA) 9.3V
9.3V
9.3V9.3V 9.3V9.3V
9.3V
VFORWARD
(FROM ON)PWR_SET
(U0959, PIN 2)D0950
D0951
1.5V
D0952
U0957-1 U0956-2
U0957-2 TEMP_1
(U0959, PIN 9)
+- +-+-
+- +- +-
+
-
MAEPF-27889-O