Motorola Astro Digital Mobile Radio Xtl5000 Detailled 6881096c74 B Manual

							6881096C74-BMay 25, 2005
Product Overview: Transmitter Section2-9
The back-end is primarily the ABACUS III digital IC. The ABACUS III IC uses a variable-bandwidth 
bandpass sigma-delta architecture. It is capable of down-converting analog as well as digital RF 
protocols into a baseband signal, which is then transmitted over the Synchronous Serial Interface 
(SSI) bus to the DSP and microprocessor.
2.4.3 700–800 MHz Band Radios
The 700–800 MHz receiver consists of a front-end section and a back-end section.
2.4.3.1  Front-End Section
The primary function of the receiver front-end is to optimize image rejection and selectivity while 
providing the first conversion. The front-end uses ceramic-filter technology and includes a wideband, 
monolithic amplifier. The first filter is a dual-switched filter that reduces the image frequency 
response and limits some of the out-of-band interference. The second filter following the monolithic 
low-noise amplifier (LNA) provides additional image rejection.
The receiver front-end signal is fed to the monolithic mixer IC where it is down converted to an IF of 
73.35 MHz. The mixer is designed to provide low conversion loss and high intermodulation 
performance. The mixer is driven by the receiver injection buffer, a two-stage discrete IC design used 
with the receiver VCO to efficiently drive the mixer over a wide temperature range with minimum 
power variation. The injection buffer provides 15 dBm to the mixer. The VCO performs low-side 
injection for the 800 MHz band and high-side Injection for the 700 MHz band. The design maintains 
temperature stability, low insertion loss, and high out-of-band rejection.
2.4.3.2  Back-End Section
The crystal filters provide IF selectivity and out-of-band signal protection to the back-end IC. Two 
2-pole crystal filters centered at 73.35 MHz that are isolated from one another by a stable, moderate- 
gain amplifier are used to meet the receiver specifications for gain, close-in intermodulation 
rejection, adjacent-channel selectivity, and second-image rejection.
The output of the IF circuit is fed directly to the ABACUS III digital back-end IC. The ABACUS III is an 
IC with a variable-bandwidth bandpass Sigma-Delta architecture. It is capable of down-converting 
analog, as well as digital, RF protocols into a baseband signal transmitted on the Synchronous Serial 
Interface (SSI) bus. The ABACUS III IC converts the 73.35 MHz signal from the IF section down to 
2.25 MHz using a second LO frequency of 71.1 MHz or 75.6 MHz. The second LO VCO is tuned to 
71.1 MHz (low side) or 75.6 MHz (high side injection). The choice of frequency depends on known 
spurious interference related to the programmed received frequency.
2.5 Transmitter Section
This section discusses the transmitter section components and basic operation for each band.
2.5.1 VHF Radios
The VHF (136–174 MHz) transmitter consists of an RF power amplifier (RFPA), output network 
(ON), and power control. See 2.5.3 700–800 MHz Radios below for an overview of the transmitter 
sections.
2.5.2 UHF Range 1/UHF Range 2 Radios
The UHF Range 1 (380–470 MHz)/UHF Range 2 (450–520 MHz) transmitter consists of an RF 
power amplifier (RFPA), output network (ON), and power control. See 2.5.3 700–800 MHz Radios 
below for an overview of the transmitter sections. 
						

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2-10Product Overview: Frequency Generation Unit
2.5.3 700–800 MHz Radios
The 700–800 MHz transmitter consists of an RF power amplifier (RFPA), output network (ON), and 
power control.
2.5.3.1  RFPA
The RFPA is a three-stage, discrete-LDMOS transistor amplifier consisting of the following stages: 
first, driver, and final.
The first stage acts as a variable-gain amplifier and feeds the driver stage, which, in turn, feeds the 
final stage. All of the stages are matched using transmission lines, capacitors, and inductors. Stage 
drain biases are supplied via A+ or K9.1V and DRV_9.3V (DRV_9.3V is present for UHF Range 1 
and UHF Range 2 only). Stage gate biases are supplied via a digital-to-analog converter (DAC) or 
the RFPA control voltage.
2.5.3.2  Output Network
The output network (ON) consists on the antenna switch, harmonic filter, and power detector. The 
antenna switch operates in two modes: RX and TX.
In TX mode, the RFPA final stage is connected to the antenna through the harmonic filter and power 
detector and is isolated from the RX path.
In RX mode, the antenna is connected to the RX front-end through the power detector and the 
harmonic filter and is isolated from the TX path. The harmonic filter attenuates harmonics generated 
by the RFPA when the antenna switch is in TX mode and provides extra selectivity in RX mode.
The power detector senses forward and reverse power and generates a detected voltage 
proportional to each.
2.5.3.3  Power Control
The forward-power and reverse-power detected voltage is fed back to the power control section 
where it is added to a DAC voltage determined via power tuning and compared to a reference 
voltage. A control loop corrects the control voltage adjusting the first stage gain to maintain the 
reference.
2.5.3.4  Circuit Protection
Final-stage current and temperature as well as radio A+ voltage and RFPA control voltage are 
sensed. If a fault condition is determined, power is cut back to a level that is safe for the particular 
conditions.
2.6 Frequency Generation Unit
This section discusses the frequency generation unit (FGU) components and basic operation for 
each band.
2.6.1 VHF MHz Radios
The VHF (136-174 MHz) frequency generation unit consists of the following:
• Low-voltage fractional-N synthesizer IC
• 16.8 MHz reference oscillator IC
• Two receiver (RX) voltage-controlled oscillators (VCOs)
• Two transmitter (TX) voltage-controlled oscillators (VCOs)
• VCO buffer/amplifier circuits 
						

							6881096C74-BMay 25, 2005
Product Overview: Frequency Generation Unit 2-11
• Associated circuitry
The reference oscillator IC provides a frequency standard to the Fractional-N synthesizer IC, the 
ABACUS III digital back-end IC, and the controller section. The synthesizer turns on one of the four 
VCOs (determined by mode and band of operation) and tunes it to the receiver (RX) local oscillator 
(LO) or transmitter (TX) carrier frequency.
All four voltage-controlled oscillators (VCOs) employ a discrete Colpitts configuration with a N-
channel J-FET transistor. The VCOs tank consists of a varactor diode, coupling capacitor, and a 
resonator. The varactor changes the oscillator frequency when the DC voltage of the steering line 
changes. The output of the VCOs is coupled to the second transistor for impedance buffering, and its 
output is coupled to respective TX/RX buffer amplifiers.
In TX mode, the transmitter VCO output is coupled to a three-stage buffer before being injected into 
the power amplifier. In RX mode, the receiver VCO output is buffered and amplified with a two-
stages. The output of the second-stage transistor is split into two paths. One path feeds back to the 
synthesizer prescaler; the other path is injected into the third-stage. The output of the third-stage 
provides the proper signal level for the LO port of the RX front-end mixer.
The superfilter supplies the voltage to the first two stages of the TX buffer and to the first two stages 
transistor of the RX buffer/amplifier. The voltage for the third stage of the TX buffer is supplied by a 
keyed 9.1 V source to conserve current drain while the radio is receiving. The third-stage of the RX 
buffer/amplifier is supplied by a 9.3 V regulator.
2.6.2 UHF Range 1/UHF Range 2 Radios
The UHF Range 1 (380–470 MHz)/UHF Range 2 (450–520 MHz) frequency generation unit consists 
of the following:
• Low-voltage fractional-N synthesizer IC
• 16.8 MHz reference oscillator IC
• Three receive voltage-controlled oscillators (VCO)
• Two transmit VCOs
• VCO buffer/amplifier circuits
• Associated circuitry
See 2.6.3 700–800 MHz Radios below for an overview of the FGU sections.
2.6.3 700–800 MHz Radios
The 700–800 MHz frequency generation unit consists of the following:
• Low-voltage fractional-N synthesizer IC
• 16.8 MHz reference oscillator IC
• Two voltage-controlled oscillator (VCO) modules (receive and transmit, containing two VCOs 
each)
• VCO buffer/amplifier circuits
• Associated circuitry
The reference oscillator IC provides a frequency standard to the fractional-N synthesizer IC, the 
ABACUS III digital back-end IC, and the controller section. The synthesizer turns on one of the four 
VCOs (determined by mode and band of operation) and tunes it to the receiver (RX) local oscillator 
(LO) or transmitter (TX) carrier frequency. 
						

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2-12Product Overview: Controller Section
The voltage-controlled oscillator (VCO) module employs a Colpitts configuration with two bipolar 
stages in a common-base, common-collector configuration. The LC tank circuits capacitive portion 
consists of a varactor diode, coupling capacitor, and a laser-trimmed capacitor for frequency 
adjustment. The inductive portion consists of microstrip transmission line resonators for TX VCO and 
coaxial resonators for RX VCO. Tuning is performed by the module manufacturer and is not field 
adjustable. The varactor changes the oscillator frequency when the DC voltage of the steering line 
changes. The output of the common base is coupled to the second transistor for impedance 
buffering, and its output is coupled to respective TX/RX buffer amplifiers.
In TX mode, the transmitter VCO output is coupled to a three-stage buffer before being injected into 
the power amplifier. In RX mode, the receiver VCO output is buffered and amplified with a two-stage 
transistor/microwave monolithic IC (MMIC) circuit. The output of the first-stage transistor is split into 
two paths. One path feeds back to the synthesizer prescaler; the other path is injected into the 
second-stage MMIC. The output of the MMIC provides the proper signal level for the LO port of the 
RX front-end mixer.
The superfilter supplies the voltage to the first two stages of the TX buffer and to the first-stage 
transistor of the RX buffer/amplifier. The voltage for the third stage of the TX buffer is supplied by a 
keyed 9.1 V source to conserve current drain while the radio is receiving. The second-stage MMIC of 
the RX buffer/amplifier is supplied by a 9.3 V regulator.
2.7 Controller Section
This section provides an explanation of radio operating modes and an overview of the controller 
section components and circuits.
2.7.1 Analog Mode of Operation
When the radio is receiving, the signal comes from the antenna/antenna-switch to the front-end 
receiver. The signal is then filtered, amplified, and mixed with the first local-oscillator signal 
generated by the voltage-controlled oscillator (VCO). The resulting intermediate frequency (IF) 
signal is fed to the IF circuitry, where it is again filtered and amplified. This amplified signal is passed 
to the digital back-end IC, where it is mixed with the second local oscillator to create the second IF at 
2.25 MHz. The analog IF is processed by an analog-to-digital (A/D) converter inside the digital back-
end IC where it is converted to a digital bit stream and divided down to a baseband signal, producing 
digital samples. These samples are converted to TTL logic signals and sent to the DSP. The DSP 
digitally filters and discriminates the signal, decodes the information in the signal, and identifies the 
appropriate destination for it. For a voice signal, the DSP will route the digital voice data to the coder/
decoder (CODEC) for conversion to an analog signal. The CODEC will then present the signal to the 
audio power amplifier, which drives the speaker. For signalling information, the DSP will decode the 
message and pass it to the microcomputer.
When the radio is transmitting, microphone audio is passed to an adjustable gain circuit, then to the 
CODEC where the signal is digitized. The CODEC passes digital data to the DSP where pre-
emphasis and low-pass (splatter) filtering are done. The DSP sends this signal to the modulation 
digital-to-analog (D/A) converter where it is reconverted into an analog signal and scaled for 
application to the voltage-controlled oscillator as a modulation signal. Transmitted signalling 
information is accepted by the DSP from the microcomputer, coded appropriately, and passed to the 
modulation D/A converter, which handles it the same as a voice signal. Modulation information is 
passed to the synthesizer along the modulation line. A modulated carrier is provided to the power 
amplifier (PA), which transmits the signal under dynamic power control. 
						

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Product Overview: Controller Section2-13
2.7.2 Digital (ASTRO) Mode of Operation
In the ASTRO mode (digital mode) of operation, the transmitted or received signal is limited to a 
discrete set of deviation levels, instead of continuously varying. The receiver handles an ASTRO-
mode signal identically to an analog-mode signal up to the point where the DSP decodes the 
received data. In the ASTRO receive mode, the DSP uses a specifically defined algorithm to recover 
information. In the ASTRO transmit mode, microphone audio is processed identically to an analog 
mode with the exception of the algorithm the DSP uses to encode the information. This algorithm will 
result in deviation levels that are limited to discrete levels.
2.7.3 Controller Section Circuitry
The controller section consists of the following:
• Voltage regulators
• Data connectivity circuitry (RS-232, USB, and SB9600)
• Daughtercard module, which contains the:
- Patriot microprocessor IC
- 64-Mbit (8MB) FLASH IC
- 8-Mbit (1MB) SRAM IC
• Modulation D/A conversion circuitry
• CODEC audio circuitry
• TX power-control circuitry
• Emergency circuitry
• V.I.P input/output paths
• Secure interconnect board interface
• Front connector interface for control heads and remote-mount interconnect boards (I.B)
• Rear connector for additional accessories
• DC power-in plug
The controller section controls receive/transmit frequencies, the display, and various radio functions 
using either direct logic control or serial communication to external devices. The connector J0701 
provides interface between the encryption module and the controller for encrypting voice messages.
Connector J0402 provides the accessory interface to the outside rear connector while connector 
J0401 provides the control-head interface.
The controller section executes a stored program located in the FLASH ROM. Data is transferred to 
and from memory via an RS-232 interface on the microprocessor. The memory location from which 
data is read, or to which data is written, is selected by the address lines. Besides the host and DSP 
code, the customer-specific programming features (codeplug) and tuning parameters also are stored 
in the FLASH ROM. The SRAM is used as scratchpad memory for the microprocessor.
The controller section is powered by SW_B+ coming from the control head, which is regulated down 
to a 5 V supply. This supply powers the entire controller section and its regulators. The SW_B+ 
supply is removed from the board when the radio is turned off by the control-head switch.
The microprocessor is powered by a 1.55-V regulator for the microprocessor core and a 2.85-V 
regulator for the I/O and control lines, while the memory is powered by a 1.85-V regulator. The 2.85-
V regulator also supplies almost all of the discrete controller circuitry. These three regulators are all 
supplied by a switched 5-V regulator, which also provides power for the SB9600 data bus and for 
interface to certain legacy data and control signals. 
						

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2-14Product Overview: Controller Section
The DSP section of microprocessor performs signaling, voice encoding/decoding, audio filtering, 
microphone gain and tuning, Private-Line/Digital Private Line (PL/DPL) encode, and alert-tone 
generation. It processes all baseband audio signals, providing pre-emphasis and signaling/filtering of 
the digital microphone audio data, as well as other transmitted signals. It also performs de-emphasis 
and decoding of received digital speaker audio and other received signals. The DSP clock frequency 
is derived from the 16.8 MHz reference oscillator clock input using a phase-locked loop (PLL) inside 
the Patriot IC. The digital audio bus on the Patriot IC uses an 8 kHz clock, which provides the 
sampling rate, and a 512 kHz clock, which provides the data rate.
The CODEC performs analog-to-digital and digital-to-analog conversions on audio signals. The DSP 
controls squelch, deviation, and compensation, and it executes receiver filtering and discrimination.
The interface to the RX back-end IC (ABACUS III IC) consists of a single logic-level data line, a 
1.2 MHz clock line (the discriminator data bit rate) and a 20 kHz frame-sync line (the discriminator 
data sample rate). These clocks are generated by the ABACUS III IC and provided to the Patriot IC.
The interface to the TX modulation/DAC consists of a single logic-level data line, a 2.4 MHz clock 
line (the modulation data bit rate), and a 48 kHz clock line (the modulation data sample rate). These 
clocks are generated by the Urchin IC and provided to the Patriot IC.
Other functions provided by the controller include SB9600 communication, IC programming, and TX 
power control. The SB9600 bus is used to communicate to legacy control heads and accessories. IC 
programming is performed via the SPI bus for ICs including the ABACUS III, LV Frac-N, A/D, D/A, 
and volume attenuator. The power-control circuitry receives power set and limit inputs from the D/A 
IC and feedback from the RF power amplifier (RFPA). Based on these inputs, the circuit produces a 
control voltage to maintain a fixed RF power level to the antenna.
The controller also provides detection of the On/Off and reset inputs. The reset circuits consist of the 
regulator power-on reset circuit, low SW_B+ voltage-detector circuit, an ignition detection circuit, an 
emergency detection circuit, and the external-bus system reset. The reset circuits allow the 
microcomputer to recover from an unstable situation; for example, no battery on the radio, battery 
voltage too high or too low, and remote devices on the external bus not communicating. 
Communication using RS-232 protocol is provided to the rear accessory connector (J2). 
						

							Chapter 3 Theory of Operation
3.1 Main Board
This section provides a detailed circuit description of the XTL 5000 radio main board for VHF/UHF 
Range 1/UHF Range 2/700–800 MHz models. The main board contains the following major 
sections:
• Radio Power (page 3-12)
• Receiver Front-End (page 3-13)
• Receiver Back-End (page 3-20)
• Transmitter (page 3-26)
• Frequency Generation Unit (page 3-45)
• Controller (page 3-62)
When reading the theory of operation, refer to your appropriate schematic and component location 
diagrams located in “Chapter 7. Schematics, Component Location Diagrams, and Parts Lists”. This 
detailed Theory of Operation will help isolate the problem. However, first use the ASTRO Digital 
XTL 5000 VHF/UHF Range 1/UHF Range 2/700–800 MHz Mobile Radio Basic Service Manual 
(6881096C73) to troubleshoot the problem to a particular board.
3.2 Main Board Major Sections
This section contains the main board layouts for each radio frequency band.
3.2.1 VHF (136–174 MHz) Band
The illustrations (Figure 3-1 on page 3-2 to Figure 3-4 on page 3-5) and their accompanying tables 
(Table 3-1 on page 3-2 to Table 3-4 on page 3-5) identify the location of the major sections of the 
main board. 
						

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3-2Theory of Operation: Main Board Major Sections
Figure 3-1.  XTL 5000 Main Board Sections (VHF Mid Power)—Side 1
Table 3-1.  XTL 5000 Main Board Sections (VHF Mid Power)—Side 1
1 Secure Connector (J0501) 8 Controller Section
2 Front Connector (J0401) 9 Audio Power Amplifier (PA)
3 RX Back-End (ABACUS III) 10 RX VCO
4 16.8 MHz Reference Oscillator 11 TX VCO
5 IF Filter 12 TX PA
6 RX Front-End 13 TX Power Control
7 Daughtercard
12
3 4
5
6 7 8
910
11
1312 
						

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Theory of Operation: Main Board Major Sections 3-3
Figure 3-2.  XTL 5000 Main Board Sections (VHF Mid Power)—Side 2
Table 3-2.  XTL 5000 Main Board Sections (VHF Mid Power)—Side 2
3 RX Back-End 16 Antenna Switch
5 IF Filter 17 Rear Connector (J0402)
6 Controller Section 18 RX Front-End Biasing
12 TX PA 19 RX VCO Injection Stage
13 TX Power Control 20 TX VCO Injection Stage
14 Power Detector 21 FGU (Synthesizer)
15 Harmonic Filter
5
3
21
19
18
20
6
141516
1217
13 
						

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3-4Theory of Operation: Main Board Major Sections
Figure 3-3.  XTL 5000 Main Board Sections (VHF High Power)—Side 1
Table 3-3.  XTL 5000 Main Board Sections (VHF High Power)—Side 1
1 Secure Connector (J0501) 8 Controller Section
2 Front Connector (J0401) 9 Audio Power Amplifier (PA)
3 RX Back-End (ABACUS III) 10 RX VCO
4 16.8 MHz Reference Oscillator 11 TX VCO
5 IF Filter 12 TX PA
6 RX Front-End 13 TX Power Control
7 Daughtercard
2
1
35
10
6 11
12 9
13 4
7 8