GE Cardiocap 5 Service Manual

Frames and Software 
A CPU control signal (ICHGLOW) reduces the maximum charge current. This can be used momentarily 
to cut the power consumption peaks of the monitor.  
Battery connector (X4) 
PIN  SIGNAL/VOLTAGE I/O DESCRIPTION 
X4/1 BAT in Battery voltage 
X4/2 BAT in  
X4/3 GND   
X4/4 GND   
5.4.8 Control electronics 
The main functions of the control and measuring electronics are listed below: 
• Buffering between CPU and DC/DC board signals. 
The buffers are HCT logic to be able to accept both...

Cardiocap/5 Technical Reference Manual 
CPU connector (X7) 
PIN  SIGNAL I/O DESCRIPTION 
X7/1 ON/STBY_1 in STBY switch end 1 
X7/2 GND  STBY switch end 2 
X7/3 STOP/ in Shut +3.3V and +5V switchers 
X7/4 POW_WD in Watchdog refresh 
X7/5 EN_VIN12V in Enable VIN_12V 
X7/6 EN_12V in Enable +12V 
X7/7 EN_15VB in Enable VIN_15VB and boost conv. 
X7/8 EN_15V in Enable +/-15V switcher 
X7/9 EN_15VD in Enable +15VD circuit breaker 
X7/10 CHG_INH in Disable charger input v. VCHG 
X7/11 BAT_TEST in Connect...

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5.4.9 AD converter 
The analog-to-digital converter is controlled by the CPU via a slow serial data bus. The signals are 
SSCLK (clock), SSDOUT (CPU data out), SSDIN (CPU data in), and ADC_CS/ (chip select). The A/D 
converter is an 11-channel, 12-bit circuit. It uses external reference voltage. On the DC/DC board, the 
reference voltage is RC-filtered from +5V_INT supply. The input voltage range is 0 to +5V. 
A/D channels 
CHANNEL SIGNAL/VOLTAGE DESCRIPTION 
ADCH0 VDD/BAT  
ADCH1...

Cardiocap/5 Technical Reference Manual 
5.5 CPU board 
The CPU board performs central data processing of the Cardiocap/5 monitor. The CPU board is based 
around an embedded AMD ELAN SC 410 (66MHz) processor. The memory chips listed below are 
located on the CPU board: 
• 16MByte DRAM 
• 8MByte Code Flash 
• 8MByte Store Flash 
• 2Mbyte Boot Flash 
• 32kByte NV-SRAM 
 
Figure 5-8. The CPU board 
The CPU board manages power by controlling and monitoring the voltage levels and power 
consumption of the...

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5-17 
DRAM
2 x 4Mx16
code & data
AMD ELAN   SC 410  ( 66MHz)
       - 486 core + 8kbyte cache
       - DRAM controller
       - 3 x Timer/Counter
       - 1 x UA RT(IrDA)
       - 2 x Interrupt Controller
       - DMA  Controller
       - ISA & VL-Bus
       - Digital I/OCrystal
32kHz
IrDAJTAG test
connector
256k x 16 display
memory
 1x
PCMCIA
connector LCD
Addr &
RAS &
CAS
Mem
card 2
Digital
I/O
Mem
card 1PCMCIA
controller
Data_lo
Data_hi
STR ATA FLASH 4M x 16
code       PLD
- upi...

Cardiocap/5 Technical Reference Manual 
5.5.1 Synchronous serial communication 
The CPU board contains two separate synchronous serial channels. Channel one handles 
communication with the Ethernet ID-block (if available). Channel two is the internal serial bus of the 
monitor. 
The synchronous serial channels are implemented with PLD to minimize the load of the main 
processor. Communication with the chips connected to the bus is handled by the PLD registers. 
Ethernet ID-block 
The Ethernet ID-block...

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Serial channels implemented with PLD (D19) 
Module Bus 
PLD and Main Software control the function of the Module Bus and the Universal Peripheral Interface 
(UPI). This way the interrupts generated by the serial communication will not load the main processor. 
The Module Bus Reset comes from PLD pin 105. 
The Module Bus is buffered to RS-485 level on the CPU board. The baud rate of the Module Bus is  
500 k baud. 
Serial channels of the Quart 
Recorder interface 
The Recorder serial...

Cardiocap/5 Technical Reference Manual 
5.5.4 Digital I/O signals 
The different I/O-signals have been split into groups according to their function:  
• Defibrillator synchronization output. 
• Alarm signals. 
• PWR-board control signals. 
Defibrillator synchronization output  
Each detected QRS complex generates a 10 ms long, 5V pulse to pin 3 of the rear panel 44-pin I/O 
connector. 
Alarm signals 
In addition to audible alarms, the CPU board drives the Alarm LEDs on the monitor front panel and a...

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5.5.5 Display controller 
The display controller chip is a VGA-compatible chip 65550. Two 256k x 16 display memories 
connected to the display controller enable use of a 32-bit databus for addressing display memory. The 
display controller is directly connected to the VESA Local bus (VL-Bus) of the processor. 
In addition to the control signals, the supply voltages (VEE_S & V_DISP) for the display are available 
on the display connector X7. The supply voltages for the display must...

Cardiocap/5 Technical Reference Manual 
5-22 
5.5.7  PC and ethernet interfaces 
PC card 
The PC card interface, a Cirrus PCMCIA controller CL-PD6722, drives two PC cards. It is connected to 
the ISA bus of the processor. 
The PC-Card interface accepts standard +3.3 V or +5  V cards. The controller selects the correct voltage 
automatically. A separate VCC and VPP switchin g matrix connects the voltage to the cards. 
Ethernet 
There are two different CPU boards available: one supporting the Network...