Acer Travelmate 7300 Service Guide

							2-24Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
SUSA# O
SUSPEND PLANE A CONTROL. Control signal asserted during power
management suspend states. SUSA# is primarily used to control the primary
power plane. This signal is asserted during POS, STR, and STD suspend states.
During Reset: Low After Reset: High During POS: Low
SUSB#/
GPO15O
SUSPEND PLANE B CONTROL. Control signal asserted during power
management suspend states. SUSB# is primarily used to control the secondary
power plane. This signal is asserted during STR and STD suspend states. If the
power plane control is not needed, this pin can be used as a general-purpose
output.
During Reset: Low After Reset: High During POS: High/GPO
SUSC#/
GPO16O
SUSPEND PLANE C CONTROL. Control signal asserted during power
management suspend states, primarily used to control the tertiary power plane.
It is asserted only during STD suspend state. If the power plane control is not
needed, this pin can be used as a general-purpose output.
During Reset: Low After Reset: High During POS: High/GPO
SUS_STAT1#/
GPO20O
SUSPEND STATUS 1. This signal is typically connected to the Host-to-PCI
bridge and is used to provide information on host clock status. SUS_STAST1# is
asserted when the system may stop the host clock, such as Stop Clock or during
POS, STR, and STD suspend states. If this function is not needed, this pin can
be used as a general-purpose output.
During Reset: Low After Reset: High During POS: Low/GPO
SUS_STAT2#/
GPO21O
SUSPEND STATUS 2. This signal will typically connect to other system
peripherals and is used to provide information on system suspend state. It is
asserted during POS, STR, and STD suspend states. If this function is not
needed, this pin can be used as a general-purpose output.
During Reset: Low After Reset: High During POS: Low/GPO
THRM#/
GPI8I
THERMAL DETECT. Active low signal generated by external hardware to start
the Hardware Clock Throttling mode. If enabled, the external hardware can force
the system to enter into Hardware Clock Throttle mode by asserting THRM#. This
causes PIIX4 to cycle STPCLK# at a preset programmable rate. If this function is
not needed, this pin can be used as a general-purpose input.
ZZ/
GPO19O
LOW-POWER MODE FOR L2 CACHE SRAM. This signal is used to power down
a cache’s data SRAMs when the clock logic places the CPU into the Stop Clock.
If this function is not needed, this pin can be used as a general-purpose output.
During Reset: Low After Reset: Low During POS: Low
GENERAL PURPOSE INPUT AND OUTPUT SIGNALS
Some of the General Purpose Input and Output signals are multiplexed with other PIIX4 signals. The usage
is determined by the system configuration.  The default pin usage is shown in Table 1 and Table 2. The
configuration can be selected via the General Configuration register and X-Bus Chip Select register.
GPI[21:0] I
GENERAL PURPOSE INPUTS. 
These input signals can be monitored via the
GPIREG register located in Function 3 (Power Management) System IO Space at
address PMBase+30h. See Table 1 for details. 
						

							Major Chips Description 2-25
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
GPO[30:0] O
GENERAL PURPOSE OUTPUTS. These output signals can be controlled via the
GPIREG register located in Function 3 (Power Management) System IO Space at
address PMBase+34h.
If a GPO pin is not multiplexed with another signal or defaults to GPO, then its
state after reset is the reset condition of the GPOREG register. If the GPO
defaults to another signal, then it defaults to that signal’s state after reset.  The
GPO pins that default to GPO remain stable after reset. The others may toggle
due to system boot or power control sequencing after reset prior to their being
programmed as GPOs.  The GPO8 signal is driven low upon removal of power
from the PIIX4 core power plane.  All other GPO signals are invalid (buffers
powered off).
GPI SIGNALS
SignalNameMultiplexedWithDefaultControl Registerand Bit (PCIFunction 1)
Notes
GPI0 IOCHK# GPI GENCFG
Bit 0Available as GPI only if in EIO bus mode.
GPI1# GPI Non-multiplexed GPI which is always available.
This signal when used by power management
logic is active low.
GPI[2:4] REQ[A:C]# GPI GENCFG
Bits 8–10Not available as GPI if used for PC/PCI. Can be
individually enabled, so for instance, GPI[4] is
available if REQ[C]# is not used.
GPI5 APICREQ# GPI XBCS
Bit 8Not available as GPI if using an external APIC.
GPI6 IRQ8# GPI GENCFG
Bit 14Not available as GPI if using external RTC or
external APIC.
GPI7 SERIRQ GPI GENCFG
Bit 16Not available as GPI if using Serial IRQ protocol.
GPI8 THRM# THRM# GENCFG
Bit 23Not available as GPI if using thermal monitoring.
GPI9 BATLOW# BATLOW# GENCFG
Bit 24Not available as GPI if using battery low feature.
GPI10 LID# LID GENCFG
Bit 25Not available as GPI if using LID feature.
GPI11 SMBALERT# SMBALERT# GENCFG
Bit 15Not available as GPI if using SMBALERT feature
GPI12 RI# RI# GENCFG
Bit 27Not available if using ring indicator feature
GPI[13:21] GPI Non-multiplexed GPIs which are always available.
GPO0 GPO Non-multiplexed GPO which is always available.
GPO[1:7] LA[17:23] GPO GENCFG
Bit 0Available as GPO only if EIO mode.
GPO8 GPO Non-multiplexed GPO which is always available.
The GPO[8] signal will be driven low upon
removal of power from the PIIX4 core power
plane. 
						

							2-26Service Guide
SignalNameMultiplexedWithDefaultControl Registerand Bit (PCIFunction 1)
Notes
GPO[9:11] GNT[A:C]# GPO GENCFG
Bits [8:10]Not available as GPO if using for PC/PCI. Can be
individually enabled, so GPO[11] is available if
REQ[C]# not used.
GPO12 APICACK# GPO XBCS
Bit 8Not available as GPO if using external APIC.
GPO13 APICCS# GPO XBCS
Bit 8Not available as GPO if using external APIC.
GPO14 IRQ0 GPO XBCS
Bit 8Not available as GPO if using external APIC.
GPO15 SUSB# SUSB# GENCFG
Bit 17Not available as GPO if using for power
management.
GPO16 SUSC# SUSC# GENCFG
Bit 17Not available as GPO if using for power
management.
GPO17 CPU_STP# CPU_STP# GENCFG
Bit 18Not available as GPO if using for clock control.
GPO18 PCI_STP# PCI_STP# GENCFG
Bit 19Not available as GPO if using for clock control.
GPO19 ZZ ZZ GENCFG
Bit 20Not available as GPO if using for power
management.
GPO20 SUS_STAT1# SUS_STAT1# GENCFG
Bit 21Not available as GPO if using for power
management.
GPO21 SUS_STAT2# SUS_STAT2# GENCFG
Bit 22Not available as GPO if using for power
management.
GPO22 XDIR# XDIR# GENCFG
Bit 28Not available as GPO if using X-bus transceiver.
GPO23 XOE# XOE# GENCFG
Bit 28Not available as GPO if using X-bus transceiver.
GPO24 RTCCS# RTCCS# GENCFG
Bit 29Not available as GPO if using external RTC that
doesn’t do self decode.
GPO25 RTCALE RTCALE GENCFG
Bit 30Not available as GPO if using external RTC that
doesn’t do self decode.
GPO26 KBCCS# KBCCS# GENCFG
Bit 31Not available as GPO if using external KBC that
doesn’t do self decode.
GPO[27:28] GPO Non-multiplexed GPOs which are always
available.
GPO29 IRQ9OUT# GPO XBCS
Bit 8Not available as GPO if using external APIC. This
signal is used for IRQ9 output in APIC mode,
where it is level triggered, active low.
GPO30 GPO Non-multiplexed GPO which is always available.
Table 2-2 82371AB Pin Descriptions (continued)
NameTypeDescription
OTHER SYSTEM AND TEST SIGNALS
CONFIG1 I
CONFIGURATION SELECT 1. 
This input signal is used to select the type of
microprocessor being used in the system. If CONFIG1=0, the system contains
a Pentium microprocessor. If CONFIG1=1, the system contains a Pentium II
microprocessor. It is used to control the polarity of INIT and CPURST signals. 
						

							Major Chips Description 2-27
Table 2-2 82371AB Pin Descriptions (continued)
NameTypeDescription
CONFIG2 I
CONFIGURATION SELECT 2. This input signal is used to select the positive or
subtractive decode of FFFF0000h–FFFFFFFFh memory address range (top
64 Kbytes).  If CONFIG[2]=0, the PIIX4 will positively decode this range. If
CONFIG[2]=1, the PIIX4 will decode this range with subtractive decode timings
only. The input value of this pin must be static and may not dynamically
change during system operations.
PWROK I
POWER OK. When asserted, PWROK is an indication to PIIX4 that power and
PCICLK have been stable for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is negated, PIIX4 asserts CPURST, PCIRST#
and RSTDRV. When PWROK driven active (high), PIIX4 negates CPURST,
PCIRST#, and RSTDRV.
SPKR O
SPEAKER. The SPKR signal is the output of counter timer 2 and is internally
“ANDed” with Port 061h bit 1 to provide the Speaker Data Enable. This signal
drives an external speaker driver device, which in turn drives the ISA system
speaker.
During Reset: Low After Reset: Low During POS: Last State
TEST# I
TEST MODE SELECT. The test signal is used to select various test modes of
PIIX4.  This signal must be pulled up to V
CC(SUS) for normal operation.
POWER AND GROUND PINS
VCC V
CORE VOLTAGE SUPPLY. These pins are the primary voltage supply for the
PIIX4 core and IO periphery and must be tied to 3.3V.
VCC (RTC) V
RTC WELL VOLTAGE SUPPLY. This pin is the supply voltage for the RTC
logic and must be tied to 3.3V.
VCC (SUS) V
SUSPEND WELL VOLTAGE SUPPLY. These pins are the primary voltage
supply for the PIIX4 suspend logic and IO signals and must be tied to 3.3V.
VCC (USB) V
USB VOLTAGE SUPPLY. This pin is the supply voltage for the USB
input/output buffers and must be tied to 3.3V.
VREF V
VOLTAGE REFERENCE. This pin is used to provide a 5V reference voltage
for 5V safe input buffers.  VREF must be tied to 5V in a system requiring 5V
tolerance. In a 5V tolerant system, this signal must power up before or
simultaneous to VCC. It must power down after or simultaneous to VCC.  In a
non-5V tolerant system (3.3V only), this signal can be tied directly to VCC.
There are then no sequencing requirements.
VSS V
CORE GROUND. These pins are the primary ground for PIIX4.
VSS (USB) V
USB GROUND. This pin is the ground for the USB input/output buffers. 
						

							2-28Service Guide
2.3 NM2160
The NM2160 is a high performance Flat Panel Video Accelerator that integrates in one single chip, 2
Mbytes of High Speed DRAM, 24-bit true-color RAMDAC, Graphics/Video Accelerator, Dual clock
synthesizer, TV Out support, ZV(Zoomed Video) port, Z-Buffer Data Stripping, PCI Bus Mastering and a
high speed glueless 32-bit PCI 2.1 compliance interface.
By integrating the display buffer DRAM and 128-bit graphics/video accelerator, the NM2160 achieves the
leading performance in the smallest footprint available. The NM2160 has sufficient bandwidth to perform
full-screen, 30fps video acceleration of MPEG, Indeo, Cinepak, and other video playback CODECs. The
bandwidth headroom also allows the NM2160 to deliver the highest quality video playback of any
notebook graphics solution, without compromising simultaneous graphics performance.
The unique integration of the NM2160 also allows the NM2160 to consume 70% less power than
equivalent video solutions, with fewer chips and less board space.
2.3.1 Features
· 128 Bit Graphics Acceleration
· High speed BitBLT Engine
· Color Expansion
· Accelerated Text Hardware
· Clipping
· X-Y Coordinates Addressing
· Memory Mapped I/O
· Bus Mastering
· Z-Buffer data stripping
· VGA I/O relocatable to MMIO Space
· Video Acceleration
· Integrated frame buffer for Video and Graphics
· 16M Color video in all modes
· Color space Conversion(YUV to RGB)
· Arbitrary video scaling up to 8X ratio
· Bilinear interpolation and Filtering
· Video Overlay capability from on/off screen memory
· Color Key Support
· Independent Brightness Control for Video Window
· Supports different color depths between video and graphics
· Supports RGB graphics and video in YUV format in one Integrated frame buffer
· Continuous down scaling independent of X&Y direction
· Memory Support 
						

							Major Chips Description 2-29
· High Speed 2Mbytes of integrated DRAM
· 128 bit Memory Interface
· Bus Support
· PCI 2.1 compliance Local Bus(Zero wait states)
· 3.3Volts or 5Volts operation
· EMI Reduction
· Spread Spectrum Clocking technology for reduced panel EMI
· Hardware Cursor and Icon
· Relocatable Hardware Cursor and Icon
· 64X64 Hardware Cursor
· 64X64 or 128X128 Hardware Icon
· Green PC Support
· VESA Display Power management(DPMS)
· DAC Power Down modes
· Suspend/Standby/Clock management
· VGA disable support
· PCI Mobile Computing “clockrun” support
· Resolution and Color Support
· VGA: TFT, DSTN, CRT@85Hz(640X480 256, 64k, 16M)
· SVGA: TFT, DSTN, CRT@85Hz(800X600 256, 64k, 16M)
· XGA: TFT, DSTN, CRT@75Hz(1024X768 256, 64k, Colors)
· Simultaneous CRT/Flat Panel operation
· Simultaneous TV/Flat Panel operation
· Display Enhancements
· TV Out Support
· ZV(Zoomed Video) Port
· 24 Bit Integrated RAMDAC with Gamma Correction
· 36 bit panel support
· Hardware expansion for low-resolution display mode compensation to panels
· Virtual Screen Panning Support
· Integrated Dual Clock Synthesizer
· VESA DDC1 and DDC2b 
						

							2-30Service Guide
2.3.2 Pin Diagram
Figure 2-3 NM2160 Pin Diagram 
						

							Major Chips Description 2-31
2.3.3 Pin Descriptions
Conventions used in the pin description types:
I Input into NM2160
O Output from NM2160
I/O Input and Output to/from NM2160
T/S Tri-state during un-driven state
S/T/S Before becoming tri-state the pin will be driven inactive
O/D Open-drain type output
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
PCI Interface
61
60
58
56
55
54
53
52
50
49
48
47
46
45
43
41
39
38
37
36
35
34
33
32
30
28
26
24
22
21
20
19AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0I/O
T/SMultiplexed Address and Data 31:0 
These multiplexed and bi-
directional pins are used to transfer address and data on the PCI
bus. The bus master will drive the 32-bit physical address during
address phase and data during data phase for write cycles.
NM2160 will drive the data bus during data phase for read cycles
63
51
40
31C/BE3#
C/BE2#
C/BE1#
C/BE0#I/O
Multiplexed Command and Byte Enable 
These multiplexed pins
provide the command during address phase and byte enable(s)
during data phase to the NM2160. NM2160 drives this pin in the
Bus Master mode 
						

							2-32Service Guide
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
72 FRAME# I/O
Frame This active-low signal is driven by the bus master to
indicate the beginning and duration of an access. NM2160 drives
this pin in the Bus Master mode
65 PAR I/O
Parity Even parity across AD31:0&C/BE3:0# is driven by the bus
master during address and write data phases and driven by
NM2160 during read data phases
67 TRDY# I/O
S/T/STarget ready This active low signal indicates NM2160’s ability to
complete the current data phase of the transaction. During a read
cycle TRDY# indicates that valid data is present on AD 31:00.
During a write, it indicates NM2160 is prepared to accept data.
Wait states will be inserted until both TRDY#&IRDY# are asserted
together. Input when NM2160 is in Bus Master
68 STOP# I/O
S/T/SStop This active low signal indicates that NM2160 is requesting
the master to terminate at the end of current transaction. Input
when NM2160 is in Bus Master
69 DEVSEL# I/O
S/T/SDevice Select This active low signal indicates that NM2160 has
decoded its address as the target of the current access. Input
when NM2160 is in Bus Master
81 IDSEL I
Initialization Device Select This input signal is used as a chip
select during configuration read and write transactions
71 BCLK I
Bus Clock This input provides the timing for all transactions on
PCI bus
66 BREQ# O
T/SBus Request This active-low output is used to indicate the arbiter
that NM2160 desires use of the bus
88 BGNT# I
Bus Grant This active-low input indicates NM2160 that access to
the bus has been granted
84 RESET# I
Reset This active-low input is used to initialize NM2160
70 INTA# O
O/DInterrupt request A This active low “level sensitive” output
indicates an interrupt request
145 CLKRUN# I/O
O/DClockrun The master device will control this signal to the NM2160,
according to the Mobile Computing PCI design guide.  If this signal
is sampled high by the NM2160 and the PCI clock related
functions are not completed then it will drive this signal Low to
request the Central Clock Resource for the continuation of the PCI
clock. This function can be Enabled/Disabled through register
GR12 bit 5
Clock Interface
93 XTAL1/
14MHZI
Oscillator Input This pin is used to feed in a reference clock of
14.31818Mhz from an external oscillator OR a Clock Source to the
internal PLL. NM2160 CR70[5] can be programmed to provide a
1Xfsc or 4xfsc NTSC sub-carrier frequency for an external analog
Encoder
92 XTAL2/
17MHZI
Oscillator Input This pin is used to feed in a reference clock of
17.734480Mhz from an external oscillator OR a Clock Source to
the internal PLL. NM2160 CR70[5] can be programmed to provide
a 1Xfsc or 4xfsc PAL/SECAM sub-carrier frequency for an external
Analog Encoder 
						

							Major Chips Description 2-33
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
83 XCKEN I
External Clock Enable This pin is used to select between
internally synthesized clocks or externally supplied clocks. A low
level on the pin selects internal mode and a high level selects
external mode. In the external clock mode, the internal clock
synthesizers will be disabled completely. Both PVCLK and PMCLK
pins should be driven with the desired clock rates in external
mode. This pin should be driven all the time during normal
operation
86 PMCLKI/
SRATUS4/
PNLCKII/O
T/SMemory Clock This pin is used for feeding external memory clock
or observing internal memory clock. When in internal clock
mode(XCKEN=0), the internal memory clock can be brought out
using this pin. When in external clock mode (XCKEN=1), PMCLKI
should be driven from an external memory clock source. General
purpose Status bit 4 can be read from register CR27 bit 1(GR17
bit 0 defines the function of this pin). GR17 bit 7 enables the
Modulated Clock Input function(PNLCKI) from the Spread
Spectrum Clock Generator
85 PVCLKI/
STATUS3/
PNLCKOI/O
T/SVideo Clock This pin is used for feeding external video clock or
observing internal video clock. When in internal clock mode
(XCKEN=0), the internal video clock can be brought out using this
pin. When in external clock mode(XCKEN=1). PVCLKI should be
driven from an external video clock source. General purpose
Status bit 3 can be read from register CR27 bit 2.  (GR17 bit 1
defines the function of this pin). GR17 bit 7 enables the Reference
clock output function(PNCLKO) to the Spread Spectrum Clock
Generator
Panel Interface
112 FLM O
First Line Marker This signal indicates start of a frame. For STN
panels this pin is connected to FLM pin. For TFT panels this pin is
connected to the VSYNC pin
113 LP O
Line Pulse This signal indicates start of a line. For STN panels
this pin is connected to the CP1 pin. For TFT panels this pin is
connected to the HSYNC pin
141 SCLK O
Shift Clock This signal is used to drive the panel shift clock. Some
panel manufactures call this CP2
115 SCLKI O
Shift Clocki This signal is used to drive the panel shift clock or as
a General Purpose Output Pin. This clock is used for panels which
use two clocks, one for the upper panel and the other for the lower
panel. This pin is also configured as a General Purpose Output Pin
as defined in register CR2F bits 1&0, to control the IMI chip for
reduced EMI
111 FPHDE/
MODO
Panel horizontal Display Enable/MOD This signal indicates the
horizontal display time to the panels.  For some panels it is used to
drive the shift clock enable pin. This pin can also be configured to
drive FPHDE for certain types of TFT panels which require
separate horizontal display time indicator.  Modulation This signal
is used to drive the panel MOD or AC input
142 FPVCC O
Flat Panel VCC This is used to control the logic power to the
panels
143 FPVEE O
Flat Panel VEE This is used to control the bias power to the
panels