Acer Travelmate 7300 Service Guide
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1-18Service Guide 1.6 System Configurations and Specifications 1.6.1 System Memory Map Table 1-8 System Memory Map Address RangeDefinitionFunction 000000 -09FFFF 640 KB memory Base memory 0A0000 -0BFFFF 128 KB video RAM Reserved for graphics display buffer 0C0000 -0CBFFF Video BIOS Video BIOS 0CC000 -0CDFFF 0CE000 -0CFFFFSystem CardBus Mini dock CardBus 0F0000 -0FFFFF 64 KB system BIOS System BIOS 010000 -07FFFF 080000 -027FFFExtended memory Onboard memory SIMM memory FE0000 -FFFFFF 256 KB system ROM Duplicate of code assignment at 0E0000-0FFFFF 1.6.2 Interrupt Channel Map Table 1-9 Interrupt Channel Map Interrupt NumberInterrupt Source (Device Name) IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 8 IRQ 9 IRQ 10 IRQ 11 IRQ 12 IRQ 13 IRQ 14 IRQ 15System Timer Keyboard Cascade IrDA / 2F8h Serial Port 1 / 3F8h Audio Floppy Disk Controller (FDC) Parallel Port Real Time Clock (RTC) USB/System CardBus Reserved for PCMCIA card Reserved for PCMCIA card/Mini dock CardBus PS/2 Mouse Co-processor Hard disk CD-ROM 1.6.3 I/O Address Map Table 1-10 I/O Address Map Address RangeDevice 000 -00F 020 -021 02E -02F 040 -043 048 -04B 060 -06EDMA controller-1 Interrupt controller-1 NS97338 peripheral controller Timer 1 Timer 2 Keyboard controller chip select
System Introduction1-19 Table 1-10 I/O Address Map Address RangeDevice 070 -071 080 -08F 0A0 -0A1 0C0 -0DF 1F0 -1F7 3F6 -3F7 170 -177 376 -377 220 -22F 240 -24F 260 -26F 280 -28F 278 -27F 2E8 -2EF 2F8 -2FF 300 -301 310 -311 320 -321 330 -321 378 -37F 388 -38B 3BC -3BE 3B4, 3B5, 3BA 3C0 -3C5 3C6 -3C9 3C0 -3CF 3D0 -3DF 3E8 -3EF 3F0 -3F7 3F8 -3FF CF8 -CFFReal-time clock and NMI mask DMA page register Interrupt controller-2 DMA controller-2 Hard disk select Hard disk select CD-ROM select CD-ROM select Audio Audio -default Audio Audio Parallel port 3 COM 4 COM 2 -IrDA MPU-401 port -default MPU-401 port MPU-401 port MPU-401 port Parallel port 2 FM synthesizer Parallel port 1 Video subsystem Video DAC Enhanced graphics display Color graphics adapter COM3 Floppy disk controller COM 1 -Serial 1 PCI configuration register 1.6.4 DMA Channel Map Table 1-11 DMA Channel Map ControllerChannelAddressFunction 1 1 1 1 2 2 2 20 1 2 3 4 5 6 70087 0083 0081 0082 Cascade 008B 0089 008AAudio(default) / IrDA(option) Audio(default) / ECP(option) / IrDA(option) Diskette Audio (option) / FIR IrDA(option) / ECP(option) Cascade Spare
1-20Service Guide 1.6.5 GPIO Port Definition Map Table 1-12 GPIO Port Definition Map I GPIO/SignalPin #I/ODescription GPIO Pin Assignment: PIIX4 SUSA# (PX3_SUSA#) W20 O 0: Power down clock generator GPO0 (PX3_DOCKRST#) G4 O 0 : Enable docking reset GPO1 (PX3_HDPON) Y15 O 1: Turn on HDD power GPO2 (PX3_ CD/FDPON) T14 O 1: Turn on CD/FDD power GPO3 (PX3_ HDRST#) W14 O 0: Reset HDD interface GPO4 (PX3_CDRST#) U13 O 0: Reset CD interface GPO5 (PX3_3MODE) V13 O 0: 3 mode drive GPO6 (PX3_SMBSEL0) Y13 O Select one of three SM buses GPO7 (PX3_SMBSEL1) T12 O SMBSEL1 SMBSEL0 0 0 DRAM bank 0 SMB 0 1 DRAM bank 1 SMB 1 0 MMO LM75 & clock gen. SMB 1 1 PCMCIA LM75 GPO8 (PX3_DOCKGNT#) T19 O 0: Granted docking GPO9/GNTA# (PX3_VDPD) N1 O 1: Power down VGA GPO10/GNTB# (PX3_VGADIS) P2 O 1: Disable VGA from PCI GPO11/GNTC# (PX3_AUDPON) P4 O 1: Power on analog audio power GPO12/APICACK# J17 O NC GPO13/APICCS# H18 O NC GPO14/IRQ0 (PX3_ROM#) H20 O 0: Enable ROMCS# GPO15/SUSB# V19 O NC GPO16/SUSC# U18 O NC GPO17/CPU_STP#(PX3_CPUSTP#) R1 O 0: Enable CPU clock stop GPO18/PCI_STP# (PX3_PCISTP#) R2 O 0: Enable PCI clock stop GPO19/ZZ (PXI_L2ZZ) K16 O 1: Power down L2 cache GPO20/SUS_STAT1#(PX3_SUSTAT#) T17 O 0: Enable MTXC power down GPO21/SUS_STAT2# (PM3_A_ACT/PD#)T18 O 0: Power down PD6832 Cardbus controller GPO22/XDIR# (PX3_FDDBEN) M3 O 1: FDD buffer enable GPO23/XOE# (PX3_SPPD) M4 O 1: Power down serial interface GPO27 (PX3_SPKOFF) G5 O 1: Turn off speaker GPO28 (PX3_FLASHVPP) F2 O 1: Enable Flash Vpp control GPO29 (PX3_FPAGE1) F3 O Force BIOS to high page 1F segment and 3 E segments GPO30 (PX3_FPAGE2) F4 O FPAGE2 FPAGE1 0 0 F, E0 0 1 F, E1 1 0 F, E2 1 1 reserved EXTSMI#(PX3_KRSMIREQ#) V20 O 0: Enable by KBD SMI or RTC wake
System Introduction1-21 Table 1-12 GPIO Port Definition Map I GPIO/SignalPin #I/ODescription GPI1 (DK3_DOCKIRQ#) P19 O 0: Detect Docking IRQ GPI2/REQA# (PX3_OEM0) M1 O OEM detection GPI3/REQB# (SM5_BAYSW) N2 O Detect FDD/CD bay 1: installed, 0: not installed GPI4/REQC# (CF5_FDD/CD#) P3 O Detect FDD or CD installed 1: FDD, 0: CD GPI5/APICREQ# K18 O NC GPI6/IRQ8# (RT3_IRQ8#) Y20 O 0: RTC wake GPI7/SERIRQ (PM3_IRQSER) J19 O Serial IRQ GPI8/THRM# (SM5_OVTMP#) H19 O 0: Enable over temperature of CPU or system GPI9/BATLOW# (PX3_OEM1) U19 I OEM detection GPI10/LID P16 I NC GPI11/SMBALER# N17 I NC GPI12/RI# (PX3_RI#) P18 I 0: Enable by Ring indicator input GPI13 (PT3_MID0) L2 I Detect MMO module revision GPI14 (PT3_MID1) J3 I Detect MMO module revision GPI15 (PT3_MID2) L5 I Detect MMO module revision GPI16 (PT3_MID3) K3 I Detect MMO module revision GPI17 (SM5_FLOATREQ#) K4 I Detect float request from SMC GPI18 (PX3_FLASHRCY#) H1 I 0: Enable flash BIOS recovery GPI19 (PX3_VGACT) H4 I 1: Detect VGA activity GPI20 (PM3_A_ACT/PD#) H5 I Detect PCMCIA socket A activity for OZ6832 GPI21 (PM3_B_ACT) G3 I Detect PCMCIA socket B activity Table 1-13 GPIO Port Definition Map II GPIOI/ODescription GPIO Pin Assignment: 80C51SL LED 0 (KB5_MIREQ#) O ANI3 (KB5_PANID3) LED 1 (KB5_NUMLED#) O PAD LED control LED 2 (KB5_CAPLED#) O CAP LED control LED 3 (KB5_KEYLICK) O Keyclick output P1.0 O NC P1.1 O NC P1.2 O NC P1.3 O NC P1.4 O NC P1.5 O NC P1.6 O NC
1-22Service Guide Table 1-13 GPIO Port Definition Map II GPIOI/ODescription P1.7 (IS5_IRQ12) O IRQ12 P2.0 (KB5_MEMB0A0) I Address 0 of memory bank 0 P2.1 (KB5_MEMB0A1) I Address 1 of memory bank 0 P2.2 (KB5_MODE) I Detect KBD mode (1:US/EC 0:Japan) P2.3 I NC P2.4 (KB5_MEMB1A0) I Address 0 of memory bank 1 P2.5 (KB5_PSWD) I Enable Password P2.6 (KB5_MEMB1A1) I Address 1 of memory bank 1 P2.7 (PX3_OEM0) I Address 1 of memory bank 1 P3.0 (SM5_TXD) I Receiving data from SMC to KBC P3.1 (SM5_RXD) O Transmitting data from KBC to SMC P3.2 (KB5_KBDCLK) O External KB clock P3.3 (KB5_PTRCLK) O External PS/2 clock P3.4 (KB5_KBDDAT) O External KB data P3.5 (KB5_PTRDAT) O External PS/2 data P3.6 (KB5_TOUCHWR*) O Write enable touch pad data P3.7 (KB5_TOUCHRD*) O Read enable touch pad data ANI0 (KB5_PANID0) I Panel ID ANI1 (KB5_PANID1) I Panel ID ANI2 (KB5_PANID2) I Panel ID ANI3 (KB5_PANID3) I Panel ID: 3 2 1 0 0 0 0 0 12.1” TFT GPIO Pin Assignment: 83C552 P0.0(SM5_CHARGEON#) O Charge control enable P0.1 O NC P0.2 (SM5_BMCPWREN#) O BMC VCC power enable P0.3 (SM5_P3/5VRON#) O 3V and 5V power on P0.4 (SM5_SUSPEND) O Suspend control enable P0.5 (SM5_PWRLED#) O Power LED P0.5 (SM5_PWRLED#) O Battery LED P0.7 (SM5_SMIREQ#) O SMC SMI request P1.0 (SI5_PNF) I Detect Printer or external FDD 0: FDD 1: Printer P1.1 (SM5_1WIRE) IO Dallas protocol P1.2 (SM5_UNDOCK_REQ#) I Undocked request P1.3 (PX3_CPUSTP#) I Detect CPU clock stop P1.4 (SM5_ATN#) IO I2C inturrupt P1.5 (SM5_RST#) IO I2C reset P1.6 (SM5_CLK#) IO I2C clock P1.7 (SM5_DAT#) IO I2C data P2.0 I NC
System Introduction1-23 Table 1-13 GPIO Port Definition Map II GPIOI/ODescription P2.1 O NC P2.2 (SM5_BAYSW) I Detect FDD/CD bay installed or not P2.3 O NC P2.4 O NC P2.5 O NC P2.6 O NC P2.7 O NC P3.0 (SM5_RXD) I Receiving data from KBC to SMC P3.1 (SM5_TXD) O Transmitting data from SMC to KBC P3.2 (SM5_DOCKSW) I Dock switch sense P3.3 (CF5_DOCKED) I Detect completely docked or not P3.4 (SM5_LIDSW) I Lid switch sense P3.5 (SM5_OVTMP#) O CPU or system over temperature P3.6 O NC P3.7 (SM5_ON_RES_SW) O ON/RESUME switch for Japan version P4.0 (SM5_FANON) O Fan control P4.1 NC P4.2 (SM5_FLOATREQ#) O Docking float request P4.3 (SM5_UNDOCK_GNT#) O Undock grant P4.4 (SM5_ICONT) I Charge current control P4.5 (SM5_FLAOTGNT#) I Docking float grant P4.6 (SM5_PWRRDYB) O Power ready, delay about 4ms after power good P4.7 (SM5_SYSRDY) O NC P5.0 (CHARGSP) I Charging set point P5.1 (SM5_VBAT_MAIN) I Main battery detection P5.2 (SM5_ACPWRGD) I AC source power good P5.3 (SM5_NBPWRGD) I 3V, 5V, processor module power good P5.4 (SM5_ATFINT) I CPU thermal interrupt (panic) P5.5 (SM5_THERM_SYS) I System thermal input (analog) P5.6 (SM5_ACIN_AUX) I Aux AC adapter in P5.7 (SM5_ACIN_MAIN) I Main AC adapter in PWM1# (SM5_CONT) O LCD contrast PWM0# (SM5_BRIT) O LCD brightness 1.6.6 PCI Devices Assignment Table 1-14 PCI Devices Assignment
1-24Service Guide DeviceDevice IDAssignment MTXC North Bridge 0 AD11 PIIX4 ISA Bridge 1 AD18 (Function 0) PIIX4 IDE controller 1 AD18 (Function 1) PIIX4 USB controller 1 AD18 (Function 2) PIIX4 PM/SMBUS controller 1 AD18 (Function 3) PCI VGA(NM2160) 2 AD13 PCI Cardbus controller A AD21 PCI Ethernet (Am79C970A) (ACER Dock III) C AD23 PCI CardBus (TI 1131) (ACER Dock V) C AD23 1.6.7 Power Management Power Management in this design is aimed toward the conservation of power on the device and system level when the devices or system is not in use. This implies that if any device is detected as not active for a sustained period of time, the device will be brought to some lower power state as soon as practicable. W ith the exception of thermal management, if a device has a demand upon it, full performance and bandwidth will be given to that device for as long as the user demands it. Power management should not cause the user to sacrifice performance or functionality in order to get longer battery life. The longer battery life should be obtained through managing resources not in use. Pathological cases of measuring CPU speed or trying to periodically check for reaction time of specific peripherals can detect the presence of power management. However, in general, since the device I/O is trapped and the device managed in SMI, the power management of devices should be invisible to the user and the application. Thermal management is the only overriding concern to the power management architecture. By definition, thermal management only comes into play when the resources of the computer are used in such a way as to accumulate heat and operate many devices at maximum bandwidth to create a thermal problem inside the unit. This thermal problem indicates a danger of damaging components due to excessively high operating temperatures. Hence, in order to maintain a safe operating environment, there may be occasions where we have to sacrifice performance in order to achieve operational safety. Heuristic power management is designed to operate and adapt to the user while the user is using it. It is the plug and play equivalent for power management. There are no entries in BIOS Setup which are required to be set by the user in order to optimize the computers battery life or operation. The only BIOS Setup entries are for condition information for suspend/resume operations. Normal operations and power management are done automatically. (see chapter 3 for details). Since the power management is implemented by linking with APM interface closely, the APM function in Win95 or Win3.1 must be enabled and set to advanced level for optimum power management and the driver that installed in system must be Acer authorized and approved.
System Introduction1-25
1.6.7.1 PMU Timers
There are several devices related timers available on the V1-LS chip. Each timer may have zero or
more devices assigned to the timer for the purpose of retriggering the timer.
Table 1-15 PMU Timers List
ItemDescriptions
Video timer
Timer value 30sec, 1min, 1.5min, 2min, 2.5min, 3min, 3.5min, 4min, 4.5min, 5min, 6min, 7min,
8min, 9min, 10min, 15min, 20min, 30min(if AC plugged-in)
System activities
and timer retriggersSystem activities
- The video display (CRT and LCD) is in power saving mode.
Timer retriggers
- KBC, PS/2 mouse will retrigger the timer..
Detective hardware
change
Parallel/serial timer
Timer value Parallel port/COM1/COM2/FIR: 30sec
System activities
and timer retriggersSystem activities
- Parallel/serial port pins are in standby mode, serial port clock is stopped and
parallel port and UART1 decode in the 87338 chip is disabled.
Timer retriggers
- Parallel port/COM1/COM2/FIR activities
Detective hardware
changeCOM1: The pin-25 of U4 MAX3243 (PX3-SPPD#) is from H to L.
Hard disk timer
Timer value First phase heuristic time-out table for entering HDD standby mode: 10sec, 20sec,
30sec, 40sec, 50sec, 60sec, 70sec, 80sec, 90sec, 2min, 3min, 4min, 5min, 30min(if
AC plugged-in)
Second phase fixed timer for entering HDD suspend mode: 10sec
System activities
and timer retriggersSystem activities
- First phase time-out (heuristic) results in hard disk spin down and IDE interface
disable. The second time-out (10sec) results in hard disk power off and IDE
controller clock is stopped and its internal HDD buffer disabled.
Timer retriggers
- The I/O access to 1F0-7, 3F6 will retrigger the timer.
Detective hardware
change1. The U20 pin Y15(PX3_HDPON) is from H to L, HDD is powered off.
FDD/CD-ROM timer
Timer value The system with internal floppy: 30sec
The system with internal CD-ROM
1: 1min, 2min, 3min, 4min, 5min, 6min, 7min, 8min,
9min, 10min, 15min, 30min(AC)
1 This parameter is for both internal CD-ROM and external floppy.
1-26Service Guide Table 1-15 PMU Timers List ItemDescriptions System activities and timer retriggersSystem activities - Power off either or both FDD and CD-ROM. Tri-state FDD and CD-ROM interfaces and stop IDE controller clock. Timer retriggers - The I/O access to 3F2, 3F4, 3F5(FDD), 3F7, 376(CD ROM) will retrigger the timer. Detective hardware change1. The PX3_FDDBEN signal on pin-M3 of U21(PIIX4) is from L to H. CD-ROM buffer is disabled. 2. The pin-T14(PX3_CD/FDPON) of U21(PIIX4) is from H to L, the FDD/CD-ROM is powered off. 1.6.7.2 Component activities in power saving mode · Hard disk The hard disk is fully power managed. This means that when the hard disk is not in use, the hard disk is powered off. The following pins are dedicated toward the management of power on the hard disk. 1. HDD power enable pinY15(PX3_HDPON). This pin turns the power on/off for the hard disk only. 2. HDD reset [pinW14(PX3_HDRST#) of PIIX4]. This pin provides the reset to the drive when the drive is newly powered up. The reset pin is asserted when the drive is first powered up, then the reset is removed after the drive is powered up and before the interface is enabled. · CD-ROM The CD-ROM and the hard disk are both IDE devices. They share the same controller. The following pins are dedicated toward the management of power on the CD-ROM. 1. CD-ROM buffer enable [pin-M3 of U21 PX3-FDDBEN of PIIX4]. The CD buffer enable separates the CD-ROM from the IDE controller. This buffer must be disabled before the CD-ROM is turned off. The buffer is re-enabled after the CD-ROM is turned on and brought out of reset. 2. CD-ROM power control [pin-T14 of U21(PX3_CD/FDPON) of PIIX4]. The power control pin is used to turn the CD-ROM unit off or on. This pin is shared as a power on/off pin for the floppy disk as well. If either the internal or external floppy or the CD-ROM is active, then this control pin must be asserted on.
System Introduction1-27 3. CD-ROM Reset [pin-U13 of U21(PX3_CDRST#) of PIIX4]. The reset pin is used to assert the hard reset needed for the CD-ROM during power up. The reset pin is asserted before CD-ROM power up and is deasserted after CD-ROM power up and before the buffer is enabled. · Floppy The floppy has two components involved in the process. The floppy drive and the controller imbedded in the 87338 super I/O chip. The FDC enable/disabled function is controlled by 87338 chip. In power saving mode, there are following condition happened to floppy drive: 1. External pin tri-state. Enabled whenever the floppy is turned off. This control signal is same to CD-ROM buffer enable pin[pin-M3 of U21(PX3_FDDBEN) of PIIX4], please see CD- ROM portion for details. 2. PLL disabled. Disabled whenever the floppy and both serial channels are inactive or disabled. 3. FDC power disable. Disables the active decode of the floppy unit. This control signal is same to CD-ROM power control[pin-T14 of U21(PX3_CD/FDPON) of PIIX4], please see CD-ROM portion for details. · Video The video controller has two interfaces for controlling power consumption. The sleep mode is controlled by software and is performed by BIOS calls. The suspend operation is controlled by a PX3_VDPD signal (pin-N1 of PIIX4). The video timer is not controlled or retriggered by video activity. Instead, the timer is retriggered by PS/2 mouse and keyboard activity. · Serial port The serial port is a UART1 and is contained within the 87368 super I/O chip. The UART1 operates off of a 14 MHz clock. The serial port also has a transceiver, a MAX211. Therefore, there are several steps to the power conservation of the serial port as below: 1. Disable the UART1 decode in the 87338 chip. 2. Tri-state the UART1 output pins. 3. Assert the Power Down pin[pin M4(PX3_SPPD#) of PIIX4] on the MAX3243 chip. The MAX3243 pin25-PX3-SPPD# of MAX3243 chip will still pass through the Ring Indicate signal even while in the power down mode(if the Resume On Modem Ring in BIOS Setup is set to enabled). . 4. Disable the 14MHz clock (If the floppy and the SIR are also disabled). If the 14MHz is disabled through the 87336 power down mode, then all serial and floppy functions will fail.