Acer Travelmate 7300 Service Guide

							2-4Service Guide
Enhanced Power Management
PIIX4’s power management functions include enhanced clock control, local and global monitoring
support for 14 individual devices, and various low-power (suspend) states, such as Power-On
Suspend, Suspend-to-DRAM, and Suspend-to-Disk. A hardware-based thermal management circuit
permits software-independent entrance to low-power states. PIIX4 has dedicated pins to monitor
various external events (e.g., interfaces to a notebook lid, suspend/resume button, battery low
indicators, etc.). PIIX4 contains full support for the Advanced Configuration and Power Interface
(ACPI) Specification.
System Management Bus (SMBus)
PIIX4 contains an SMBus Host interface that allows the CPU to communicate with SMBus slaves
and an SMBus Slave interface that allows external masters to activate power management events.
Configurability
PIIX4 provides a wide range of system configuration options. This includes full 16-bit I/O decode on
internal modules, dynamic disable on all the internal modules, various peripheral decode options,
and many options on system configuration.
2.2.1 Features
· Supported Kits for Pentium® II Microprocessors
· 82440BX ISA/DP Kit
· Multifunction PCI to ISA Bridge
· Supports PCI at 30 MHz and 33 MHz
· Supports PCI Rev 2.1 Specification
· Supports Full ISA or Extended I/O (EIO) Bus
· Supports Full Positive Decode or Subtractive Decode of PCI
· Supports ISA and EIO at 1/4 of PCI Frequency
· Supports both Mobile and Desktop Deep Green Environments
· 3.3V Operation with 5V Tolerant Buffers
· Ultra-low Power for Mobile Environments Support
· Power-On Suspend, Suspend to RAM, Suspend to Disk, and Soft-OFF System States
· All Registers Readable and Restorable for Proper Resume from 0.V Suspend
· Power Management Logic
· Global and Local Device Management
· Suspend and Resume Logic
· Supports Thermal Alarm
· Support for External Microcontroller 
						

							Major Chips Description 2-5
· Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0
Specification and OS Directed Power Management
· Integrated IDE Controller
· Independent Timing of up to 4 Drives
· PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec
· Supports “Ultra DMA/33” Synchronous DMA Mode Transfers up to 33 Mbytes/sec
· Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers
· Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation
· Enhanced DMA Controller
· Two 82C37 DMA Controllers
· Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA Protocols
(Simultaneously)
· Fast Type-F DMA for Reduced PCI Bus Usage
· Interrupt Controller Based on Two 82C59
· 15 Interrupt Support
· Independently Programmable for Edge/Level Sensitivity
· Supports Optional I/O APIC
· Serial Interrupt Input
· Timers Based on 82C54
· System Timer, Refresh Request, Speaker Tone Output
· USB
· Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec
· Supports Legacy Keyboard and Mouse Software with USB-based Keyboard and Mouse
· Supports UHCI Design Guide
· SMBus
· Host Interface Allows CPU to Communicate Via SMBus
· Slave Interface Allows External SMBus Master to Control Resume Events
· Real-Time Clock
· 256-byte Battery-Back CMOS SRAM
· Includes Date Alarm
· Two 8-byte Lockout Ranges
· Microsoft Win95* Compliant
· 324 mBGA Package 
						

							2-6Service Guide
The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-to-
ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced
Power Management function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions
found in ISA-based PC systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an
82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA
channel supports Type F transfers. PIIX4 also contains full support for both PC/PCI and Distributed
DMA protocols implementing PCI-based DMA. The Interrupt Controller has Edge or Level sensitive
programmable inputs and fully supports the use of an external I/O Advanced Programmable
Interrupt Controller (APIC) and Serial Interrupts. Chip select decoding is provided for BIOS, Real
Time Clock, Keyboard Controller, second external microcontroller, as well as two Programmable
Chip Selects. PIIX4 provides full Plug and Play compatibility. PIIX4 can be configured as a
Subtractive Decode bridge or as a Positive Decode bridge. This allows the use of a subtractive
decode PCI-to-PCI bridge such as the Intel 380FB PCIset which implements a PCI/ISA docking
station environment.
PIIX4 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard
disks and CD ROMs. Up to four IDE devices can be supported in Bus Master mode. PIIX4 contains
support for “Ultra DMA/33” synchronous DMA compatible devices.
PIIX4 contains a Universal Serial Bus (USB) Host Controller that is Universal Host Controller
Interface (UHCI) compatible. The Host Controller’s root hub has two programmable USB ports.
PIIX4 supports Enhanced Power Management, including full Clock Control, Device Management for
up to 14 devices, and Suspend and Resume logic with Power On Suspend, Suspend to RAM or
Suspend to Disk. It fully supports Operating System Directed Power Management via the Advanced
Configuration and Power Interface (ACPI) specification. PIIX4 integrates both a System
Management Bus (SMBus) Host and Slave interface for serial communication with other devices.
2.2.2  Architecture Block Diagram
The following is the architectural block diagram of the PIIX4 with respect to its implementation in this
notebook computer.
Figure 2-1 PIIX4 Architecture Block Diagram 
						

							Major Chips Description 2-7
2.2.3 Block Diagram
Figure 2-2 PIIX4 Simplified Block Diagram 
						

							2-8Service Guide
2.2.4 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional
groups according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage level. W hen “#” is not present after the signal name, the signal is
asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when
working with a mixture of “active low” and “active high” signal. The term assert, or assertion
indicates that a signal is active, independent of whether that level is represented by a high or low
voltage. The term negate, or negation indicates that a signal is inactive.
Certain signals have different functions, depending on the configuration programmed in the PCI
configuration space. The signal whose function is being described is in 
bold font. Some of the
signals are multiplexed with General Purpose Inputs and Outputs. The default configuration and
control bits for each are described in Table 1 and Table 2.
Each output signal description includes the value of the signal 
During Reset, 
After Reset, and
During POS.
During Reset refers to when the PCIRST# signal is asserted. 
After Reset is immediately after
negation of PCIRST# and the signal may change value anytime thereafter. The term 
High-Z means
tri-stated. The term 
Undefined means the signal could be high, low, tri-stated, or in some in-
between level. Some of the power management signals are reset with the RSMRST# input signal.
The functionality of these signals during RSMRST# assertion is described in the 
Suspend/Resume
and Power Plane Control 
section.
The I/O buffer types are shown below:
BUFFER TYPE DESCRIPTION
I input only signal
O totem pole output
I/O bi-direction, tri-state input/output pin
s/t/s sustained tri-state
OD open drain
I/OD input/open drain output is a standard input buffer with an open drain output
V This is not a standard signal. It is a power supply pin.
3.3V/2.5V Indicates the buffer is 3.3V or 2.5V only, depending on the voltage (3.3V or 2.5V)
connected to VCCX pins.
3.3V/5V Indicates that the output is 3.3V and input is 3.3V receiver with 5V tolerance.
5V Indicates 3.3V receiver with 5V tolerance.
All 3V output signals can drive 5V TTL inputs. Most of the 3V input signals are 5V tolerant. The 3V
input signals which are powered via the RTC or Suspend power planes should not exceed their
power supply voltage (see Power Planes chapter for additional information). The open drain (OD)
CPU interface signals should be pulled up to the CPU interface signal voltage. 
						

							Major Chips Description 2-9
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
PCI BUS INTERFACE
AD[31:0] I/O
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits).
During subsequent clocks, AD[31:0] contain data.  A PIIX4 Bus transaction
consists of an address phase followed by one or more data phases. Little-endian
byte ordering is used. AD[7:0] define the least significant byte (LSB) and
AD[31:24] the most significant byte (MSB).  When PIIX4 is a Target, AD[31:0] are
inputs during the address phase of a transaction.  During the following data
phase(s), PIIX4 may be asked to supply data on AD[31:0] for a PCI read, or
accept data for a PCI write.  As an Initiator, PIIX4 drives a valid address on
AD[31:2] and 0 on AD[1:0] during the address phase, and drives write or latches
read data on AD[31:0] during the data phase.
During Reset: High-Z After Reset: High-Z During POS: High-Z
C/BE#[3:0] I/O
BUS COMMAND AND BYTE ENABLES. The command and byte enable signals
are multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used
as Byte Enables. The Byte Enables determine which byte lanes carry meaningful
data.  C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4 drives C/BE[3:0]#
as an Initiator and monitors C/BE[3:0]# as a Target.
During Reset: High-Z After Reset: High-Z During POS: High-Z
CLKRUN# I/O
CLOCK RUN#. This signal is used to communicate to PCI peripherals that the
PCI clock will be stopped. Peripherals can assert CLKRUN# to request that the
PCI clock be restarted or to keep it from stopping. This function follows the
protocol described in the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low After Reset: Low During POS: High
DEVSEL# I/O
DEVICE SELECT. PIIX4 asserts DEVSEL# to claim a PCI transaction through
positive decoding or subtractive decoding (if enabled). As an output, PIIX4
asserts DEVSEL# when it samples IDSEL active in configuration cycles to PIIX4
configuration registers.  PIIX4 also asserts DEVSEL# when an internal PIIX4
address is decoded or when PIIX4 subtractively or positively decodes a cycle for
the ISA/EIO bus or IDE device. As an input, DEVSEL# indicates the response to
a PIIX4 initiated transaction and is also sampled when deciding whether to
subtractively decode the cycle. DEVSEL# is tri-stated from the leading edge of
PCIRST#. DEVSEL# remains tri-stated until driven by PIIX4 as a target.
During Reset: High-Z After Reset: High-Z During POS: High-Z
FRAME# I/O
CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the
beginning and duration of an access. While FRAME# is asserted data transfers
continue. When FRAME# is negated the transaction is in the final data phase.
FRAME# is an input to PIIX4 when it is the Target. FRAME# is an output when
PIIX4 is the initiator. FRAME# remains tri-stated until driven by PIIX4 as an
Initiator.
During Reset: High-Z After Reset: High-Z During POS: High-Z
IDSEL I
INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during PCI
configuration read and write cycles. PIIX4 samples IDSEL during the address
phase of a transaction. If IDSEL is sampled active, and the bus command is a
configuration read or write, PIIX4 responds by asserting DEVSEL# on the next
cycle. 
						

							2-10Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
IRDY# I/O
INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete
the current data phase of the transaction. It is used in conjunction with TRDY#. A
data phase is completed on any clock both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates PIIX4 has valid data present on
AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY# is an
input to PIIX4 when PIIX4 is the Target and an output when PIIX4 is an Initiator.
IRDY# remains tri-stated until driven by PIIX4 as a master.
During Reset: High-Z After Reset: High-Z During POS: High-Z
PAR O
CALCULATED PARITY SIGNAL. PAR is “even” parity and is calculated on 36
bits; AD[31:0] plus C/BE[3:0]#. “Even” parity means that the number of “1”s within
the 36 bits plus PAR are counted and the sum is always even. PAR is always
calculated on 36 bits regardless of the valid byte enables. PAR is generated for
address and data phases and is only guaranteed to be valid one PCI clock after
the corresponding address or data phase. PAR is driven and tri-stated identically
to the AD[31:0] lines except that PAR is delayed by exactly one PCI clock. PAR is
an output during the address phase (delayed one clock) for all PIIX4 initiated
transactions. It is also an output during the data phase (delayed one clock) when
PIIX4 is the Initiator of a PCI write transaction, and when it is the Target of a read
transaction.
During Reset: High-Z After Reset: High-Z During POS: High-Z
PCIRST# O
PCI RESET. PIIX4 asserts PCIRST# to reset devices that reside on the PCI bus.
PIIX4 asserts PCIRST# during power-up and when a hard reset sequence is
initiated through the RC register. PCIRST# is driven inactive a minimum of 1 ms
after PWROK is driven active. PCIRST# is driven for a minimum of 1 ms when
initiated through the RC register.  PCIRST# is driven asynchronously relative to
PCICLK.
During Reset: Low After Reset: High During POS: High
PHOLD# O
PCI HOLD. An active low assertion indicates that PIIX4 desires use of the PCI
Bus.  Once the PCI arbiter has asserted PHLDA# to PIIX4, it may not negate it
until PHOLD# is negated by PIIX4. PIIX4 implements the passive release
mechanism by toggling PHOLD# inactive for one PCICLK.
During Reset: High-Z After Reset: High During POS: High
PHLDA# I
PCI HOLD ACKNOWLEDGE. An active low assertion indicates that PIIX4 has
been granted use of the PCI Bus. Once PHLDA# is asserted, it cannot be
negated unless PHOLD# is negated first.
SERR# I/O
SYSTEM ERROR. SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, PIIX4 can be programmed
to generate a non-maskable interrupt (NMI) to the CPU.
During Reset: High-Z After Reset: High-Z During POS: High-Z
STOP# I/O
STOP. STOP# indicates that PIIX4, as a Target, is requesting an initiator to stop
the current transaction. As an Initiator, STOP# causes PIIX4 to stop the current
transaction.  STOP# is an output when PIIX4 is a Target and an input when PIIX4
is an Initiator.  STOP# is tri-stated from the leading edge of PCIRST#. STOP#
remains tri-stated until driven by PIIX4 as a slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z 
						

							Major Chips Description 2-11
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
TRDY# I/O
TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase
is completed when both TRDY# and IRDY# are sampled asserted. During a read,
TRDY# indicates that PIIX4, as a Target, has place valid data on AD[31:0].
During a write, it indicates PIIX4, as a Target is prepared to latch data. TRDY# is
an input to PIIX4 when PIIX4 is the Initiator and an output when PIIX4 is a Target.
TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated
until driven by PIIX4 as a slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
Note: All of the signals in the host interface are described in the Pentium Processor data sheet. The
preceding table highlights PIIX4 specific uses of these signals.
ISA BUS INTERFACE
AEN O
ADDRESS ENABLE. AEN is asserted during DMA cycles to prevent I/O slaves
from misinterpreting DMA cycles as valid I/O cycles. When negated, AEN
indicates that an I/O slave may respond to address and I/O commands. When
asserted, AEN informs I/O resources on the ISA bus that a DMA transfer is
occurring. This signal is also driven high during PIIX4 initiated refresh cycles.
During Reset: High-Z After Reset: Low During POS: Low
BALE O
BUS ADDRESS LATCH ENABLE. BALE is asserted by PIIX4 to indicate that the
address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17]
address lines are latched on the trailing edge of BALE. BALE remains asserted
throughout DMA and ISA master cycles.
During Reset: High-Z After Reset: Low During POS: Low
IOCHK#/
GPI0I
I/O CHANNEL CHECK. IOCHK# can be driven by any resource on the ISA bus.
When asserted, it indicates that a parity or an uncorrectable error has occurred
for a device or memory on the ISA bus. A NMI will be generated to the CPU if the
NMI generation is enabled. If the EIO bus is used, this signal becomes a general
purpose input.
IOCHRDY I/O
I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to indicate
that wait states are required to complete the cycle. This signal is normally high.
IOCHRDY is an input when PIIX4 owns the ISA Bus and the CPU or a PCI agent
is accessing an ISA slave, or during DMA transfers. IOCHRDY is output when an
external ISA Bus Master owns the ISA Bus and is accessing DRAM or a PIIX4
register. As a PIIX4 output, IOCHRDY is driven inactive (low) from the falling
edge of the ISA commands.  After data is available for an ISA master read or
PIIX4 latches the data for a write cycle, IOCHRDY is asserted for 70 ns. After 70
ns, PIIX4 floats IOCHRDY. The 70 ns includes both the drive time and the time it
takes PIIX4 to float IOCHRDY. PIIX4 does not drive this signal when an ISA Bus
master is accessing an ISA Bus slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
IOCS16# I
16-BIT I/O CHIP SELECT. This signal is driven by I/O devices on the ISA Bus to
indicate support for 16-bit I/O bus cycles.
IOR# I/O
I/O READ. IOR# is the command to an ISA I/O slave device that the slave may
drive data on to the ISA data bus (SD[15:0]). The I/O slave device must hold the
data valid until after IOR# is negated. IOR# is an output when PIIX4 owns the ISA
Bus. IOR# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High 
						

							2-12Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
IOW# I/O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns
the ISA Bus. IOW# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
LA[23:17]/
GPO[7:1]I/O
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on
the ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns the ISA
Bus. The LA[23:17] lines become inputs whenever an ISA master owns the ISA
Bus.  If the EIO bus is used, these signals become a general purpose output.
During Reset: High-Z After Reset: Undefined During POS: Last LA/GPO
MEMCS16# I/O
MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17] without any
qualification of the command signal lines. ISA slaves that are 16-bit memory
devices drive this signal low. PIIX4 ignores MEMCS16# during I/O access cycles
and refresh cycles. MEMCS16# is an input when PIIX4 owns the ISA Bus. PIIX4
drives this signal low during ISA master to PCI memory cycles.
During Reset: High-Z After Reset: High-Z During POS: High-Z
MEMR# I/O
MEMORY READ. MEMR# is the command to a memory slave that it may drive
data onto the ISA data bus. MEMR# is an output when PIIX4 is a master on the
ISA Bus.  MEMR# is an input when an ISA master, other than PIIX4, owns the
ISA Bus. This signal is also driven by PIIX4 during refresh cycles. For DMA
cycles, PIIX4, as a master, asserts MEMR#.
During Reset: High-Z After Reset: High During POS: High
MEMW# I/O
MEMORY WRITE. MEMW# is the command to a memory slave that it may latch
data from the ISA data bus. MEMW# is an output when PIIX4 owns the ISA Bus.
MEMW# is an input when an ISA master, other than PIIX4, owns the ISA Bus.
For DMA cycles, PIIX4, as a master, asserts MEMW#.
During Reset: High-Z After Reset: High During POS: High
REFRESH# I/O
REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when a refresh
cycle is in progress. It should be used to enable the SA[7:0] address to the row
address inputs of all banks of dynamic memory on the ISA Bus. Thus, when
MEMR# is asserted, the entire expansion bus dynamic memory is refreshed.
Memory slaves must not drive any data onto the bus during refresh. As an output,
this signal is driven directly onto the ISA Bus. This signal is an output only when
PIIX4 DMA refresh controller is a master on the bus responding to an internally
generated request for refresh.  As an input, REFRESH# is driven by 16-bit ISA
Bus masters to initiate refresh cycles.
During Reset: High-Z After Reset: High During POS: High
RSTDRV O
RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the
ISA/EIO Bus. PIIX4 asserts this signal during a hard reset and during power-up.
RSTDRV is asserted during power-up and negated after PWROK is driven active.
RSTDRV is also driven active for a minimum of 1 ms if a hard reset has been
programmed in the RC register.
During Reset: High After Reset: Low During POS: Low 
						

							Major Chips Description 2-13
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
SA[19:0] I/O
SYSTEM ADDRESS[19:0]. These bi-directional address lines define the
selection with the granularity of 1 byte within the 1-Megabyte section of memory
defined by the LA[23:17] address lines. The address lines SA[19:17] that are
coincident with LA[19:17] are defined to have the same values as LA[19:17] for
all memory cycles.  For I/O accesses, only SA[15:0] are used, and SA[19:16] are
undefined. SA[19:0] are outputs when PIIX4 owns the ISA Bus. SA[19:0] are
inputs when an external ISA Master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: Last SA
SBHE# I/O
SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a byte is
being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated
during refresh cycles. SBHE# is an output when PIIX4 owns the ISA Bus. SBHE#
is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: High
SD[15:0] I/O
SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on the
ISA Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond to
the low order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z After Reset: Undefined During POS: High-Z
SMEMR# O
STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA
memory slave to drive data onto the data lines. If the access is below the 1-Mbyte
range (00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA
master cycles, PIIX4 asserts SMEMR#. SMEMR# is a delayed version of
MEMR#.
During Reset: High-Z After Reset: High During POS: High
SMEMW# O
STANDARD MEMORY WRITE. PIIX4 asserts SMEMW# to request an ISA
memory slave to accept data from the data lines. If the access is below the 1-
Mbyte range (00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or
ISA master cycles, PIIX4 asserts SMEMW#. SMEMW# is a delayed version of
MEMW#.
During Reset: High-Z After Reset: High During POS: High
ZEROWS# I
ZERO WAIT STATES. An ISA slave asserts ZEROWS# after its address and
command signals have been decoded to indicate that the current cycle can be
shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An 8-bit
memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect
during 16-bit I/O cycles.  If IOCHRDY is negated and ZEROWS# is asserted
during the same clock, then ZEROWS# is ignored and wait states are added as a
function of IOCHRDY.
X-BUS INTERFACE
A20GATE I
ADDRESS 20 GATE. This input from the keyboard controller is logically
combined with bit 1 (FAST_A20) of the Port 92 Register, which is then output via
the A20M# signal.
BIOSCS# O
BIOS CHIP SELECT. This chip select is driven active during read or write
accesses to enabled BIOS memory ranges. BIOSCS# is driven combinatorially
from the ISA addresses SA[16:0] and LA[23:17], except during DMA cycles.
During DMA cycles, BIOSCS# is not generated.
During Reset: High After Reset: High During POS: High