Acer Travelmate 7300 Service Guide

							2-44Service Guide
2.5.2 Block Diagram
Figure 2-6 87C552 Block Diagram 
						

							Major Chips Description 2-45
2.5.3 Pin Diagram
9 P4.2/CMSR2
8 P4.1/CMSR1
7 P4.0/CMSR0
6 EW#
5 PWM1#
4 PWM0#
3 STADC
2 VDD
1 P5.0/ADC0
68 P5.1/ADC1
67 P5.2/ADC2
66 P5.3/ADC3
65 P5.4/ADC4
64 P5.5/ADC5
63 P5.6/ADC6
62 P5.7/ADC7
61 AVDD
60 AVSS
59 AVref+
58 AVref–
57 P0.0/AD0
56 P0.1/AD1
55 P0.2/AD2
54 P0.3/AD3
53 P0.4/AD4
52 P0.5/AD5
51 P0.6/AD6
50 P0.7/AD7
49 EA#/VPP
48 ALE/PROG#
47 PSEN#
46 P2.7/A15
45 P2.6/A14
44 P2.5/A13
43 P2.4/A12
42 P2.3/A11
41 P2.2/A10
40 P2.1/A09
39 P2.0/A08
38 NC
37 VSS
36 VSS
35 XTAL1
34 XTAL2
33 NC
32 NC
31 P3.7/RD
30 P3.6/WR
29 P3.5/T1
28 P3.4/T0
27 P3.3/INT1
P4.3/CMSR3 10
P4.4/CMSR4 11
P4.5/CMSR5 12
P4.6/CMT0 13
P4.7/CMT1 14
RST 15
P1.0/CT0I 16
P1.1/CT1I 17
P1.2/CT2I 18
P1.3/CT3I 19
P1.4/T2 20
P1.5/RT2 21
P1.6/SCL 22
P1.7/SDA 23
P3.0/RxD 24
P3.1/TxD 25
P3.2/INT0 26
Figure 2-7 87C552 Pin Diagram 
						

							2-46Service Guide
2.5.4 Pin Descriptions
Table 2-5 87C552 Pin Descriptions
MnemonicPin No.TypeName And Function
VDD2I
Digital Power Supply: 
+5V power supply pin during normal operation,
idle and power-down mode.
STADC 3 I
Start ADC Operation: 
Input starting analog to digital conversion (ADC
operation can also be started by software).
PWM0# 4 O
Pulse Width Modulation: 
Output 0.
PWM1# 5 O
Pulse Width Modulation: 
Output 1
EW# 6 I
Enable Watchdog Timer: 
Enable for T3 watchdog timer and disable
power-down mode.
P0.0-P0.7 57-50 I/O
Port 0: 
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1s written to them float and can be used as high-impedance
inputs. Port 0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory. In this
application it uses strong internal pull-ups when emitting 1s. Port 0 is
also used to input the code byte during programming and to output the
code byte during verification.
P1.0-P1.7 16-23 I/O
Port 1: 
8-bit I/O port. Alternate functions include:
16-21 I/O
(P1.0-P1.5): 
Quasi-bidirectional port pins.
22-23 I/O
(P1.6, P1.7): 
Open drain port pins.
16-19 I
CT0I-CT3I (P1.0-P1.3): 
Capture timer input signals for timer T2.
20 I
T2 (P1.4): 
T2 event input.
21 I
RT2 (P1.5): 
T2 timer reset signal. Rising edge triggered.
22 I/O
SCL (P1.6): 
Serial port clock line I 2 C-bus.
23 I/O
SDA (P1.7): 
Serial port data line I 2 C-bus. Port 1 is also used to input
the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
P2.0-P2.7 39-46 I/O
Port 2: 
8-bit quasi-bidirectional I/O port. Alternate function: High-order
address byte for external memory (A08-A15). Port 2 is also used to
input the upper order address during EPROM programming and
verification. A8 is on P2.0, A9 on P2.1, through A12 on P2.4.
P3.0-P3.7 24-31 I/O
Port 3: 
8-bit quasi-bidirectional I/O port. Alternate functions include:
24
RxD(P3.0): 
Serial input port.
25
TxD (P3.1): 
Serial output port.
26
INT0 (P3.2): 
External interrupt.
27
INT1 (P3.3): 
External interrupt.
28
T0 (P3.4): 
Timer 0 external input.
29
T1 (P3.5): 
Timer 1 external input.
30
WR (P3.6): 
External data memory write strobe.
31
RD (P3.7): 
External data memory read strobe. 
						

							Major Chips Description 2-47
Table 2-5 87C552 Pin Descriptions
MnemonicPin No.TypeName And Function
P4.0-P4.7 7-14 I/O
Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
7-12 O
CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs
on a match with timer T2. 13, 14
13, 14 O
CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a
match with timer T2.
P5.0-P5.7 68-62, I
Port 5: 8-bit input port.
1
ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to
ADC.
RST 15 I/O
Reset: Input to reset the 87C552. It also provides a reset pulse as
output when timer T3 overflows.
XTAL1 35 I
Crystal Input 1: Input to the inverting amplifier that forms the oscillator,
and input to the internal clock generator. Receives the external clock
signal when an external oscillator is used.
XTAL2 34 O
Crystal Input 2: Output of the inverting amplifier that forms the
oscillator. Left open-circuit when an external clock is used.
VSS36, 37 I
Digital ground.
PSEN# 47 O
Program Store Enable: Active-low read strobe to external program
memory.
ALE/PROG# 48 O
Address Latch Enable: Latches the low byte of the address during
accesses to external memory. It is activated every six oscillator
periods. During an external data memory access, one ALE pulse is
skipped. ALE can drive up to eight LS TTL inputs and handles CMOS
inputs without an external pull-up. This pin is also the program pulse
input (PROG#) during EPROM programming.
EA#/V PP49 I
External Access: When EA# is held at TTL level high, the CPU
executes out of the internal program ROM provided the program
counter is less than 8192. When EA# is held at TTL low level, the CPU
executes out of external program memory. EA# is not allowed to float.
This pin also receives the 12.75V programming supply voltage (V
PP )
during EPROM programming.
AVREF–58 I
Analog to Digital Conversion Reference Resistor: Low-end.
AVREF+59 I
Analog to Digital Conversion Reference Resistor: High-end.
AVSS60 I
Analog Ground
AVDD61 I
Analog Power Supply 
						

							2-48Service Guide
2.6  NS97338VJG Super I/O Controller
The PC97338VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA
based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs, and an
IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the peripherals and a
set of configuration registers are also implemented in this highly integrated member of the Super l/O
family. Advanced power management features, mixed voltage operation and integrated Serial-
lnfrared(both IrDA and Sharp) support makes the PC97338 an ideal choice for low-power and/or
portable personal computer applications.
The PC97338 FDC uses a high performance digital data separator eliminating the need for any
external filter components. It is fully compatible with the PC8477 and incorporates a superset of
DP8473, NEC PD765 and N82077 floppy disk controller functions. All popular 5.25” and 3.5” floppy
drives, including the 2.88 MB 3.5” floppy drive, are supported. In addition, automatic media sense
and 2 Mbps tape drive support are provided by the FDC.
The two UARTs are fully NS16450 and NS16550 compatible. Both ports support MIDI baud rates
and one port also supports IrDA 1.0 SIR(with data rate of 115.2Kbps), IrDA 1.1 MIR and FIR(with
data rate of 1.152Mbps and 4.0Mbps respectively) ,  and Sharp SIR(with data rate of 38.4Kbps
respectively) compliant signaling protocol.
The parallel port is fully IEEE 1284 level 2 compatible. The SPP(Standard Parallel Port) is fully
compatible wit ISA and EISA parallel ports. In addition to the SPP, EPP(Enhanced Parallel Port) and
ECP(Extended Capabilities Port) modes are supported by the parallel port.
A set of configuration registers are provided to control the Plug and Play and other various functions
of the PC97338. These registers are accessed using two 8-bit wide index and data registers. The
ISA I/O address of the register pair can be relocated using a power-up strapping option and the
software configuration after power-up.
W hen idle, advanced power management features allows the PC97338 to enter extremely low
power modes under software control. The PC97338 operates at a 3.3/5V power supply.
2.6.1 Features
· 100% compatible with ISA, and EISA architectures
· The Floppy Disk Controller:
· Software compatible with the DP8473, the 765A and the N82077
· 16-byte FlFO(disabled by default)
· Burst and Non-Burst modes
· Perpendicular Recording drive support
· New high-performance internal digital data separator(no external filter components required)
· Low-power CMOS with enhanced power-down mode
· Automatic media-sense support, with full IBM TDR(Tape Drive Register) implementation
· Supports fast 2 Mbps and standard 1 Mbps/500 kbps/250 kbps tape drives 
						

							Major Chips Description 2-49
· The Bidirectional Parallel Port:
· Enhanced Parallel Port(EPP) compatible
· Extended Capabilities Port(ECP) compatible, including level 2 support
· Bidirectional under either software or hardware control
· Compatible with ISA, and EISA, architectures
· Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk
Drive(FDD)
· Includes protection circuit to prevent damage to the parallel port when a connected printer is
powered up or is operated at a higher voltage
· The UARTs:
· Software compatible with the PC16550A and PC16450
· MIDI baud rate support
· Infrared support on UART2 (IrDA 1.0 SIR, IrDA 1.1 MIR and FIR, and Sharp SIR)
· The Address Decoder
· 6 bit or 10 bit decoding
· External Chip Select capability when 10 bit decoding
· Full relocation capability(No limitation)
· Enhanced Power Management
· Special configuration registers for power-down
· Enhanced programmable power-down FDC command
· Auto power-down and wake-up modes
· 2 special pins for power management
· Typical current consumption during power-down is less than 10 uA
· Reduced pin leakage current
· Voltage support
· 3.3/5V operation
· The General Purpose Pins:
· 1 pin, for 2 separate programmable chip select decoders, can be programmed for game port
control
· Plug and Play Compatible:
· 16 bit addressing(full programmable)
· 10 selectable IRQs
· 4 selectable DMA Channels
· 3 SIRQ Inputs allows external devices to mapping IRQs
· 100-Pin TQFP package - PC97338VJG 
						

							2-50Service Guide
2.6.2 Block Diagram
Configuration
Re
gisters
UART
(16550 or 16450)UART
+ IrDA/HP & Sharp IR
(16550 or 16450)
General
Purpose
Re
gisters
Power
Down Lo
gic
IEEEE1284
Parallel Port
Hifh Current Driver
Floppy Disk
Controller with
Di
gital Data
Separator
(Enhabced 8477)
I/O Ports Control
InterruptData HandshakeFloppy
Drive
Interface
OSCInterrupt
and
DMAFloppy
Drive
Interface InterruptIR
Interface Serial
Interface Interrupt Serial
Interface Confi
g.
Inputs
Figure 2-8 NS97338VJG Block Diagram 
						

							Major Chips Description 2-51
2.6.3 Pin Diagram
Figure 2-9 NS97338VJG Pin Diagram 
						

							2-52Service Guide
2.6.4 Pin Description
Table 2-6 NS97338VJG Pin Descriptions
PinNo.I/ODescription
A15-A0 67, 64,
62-60,
29, 19-
28I
Address.
  These address lines from the microprocessor determine
which internal register is accessed.  A0-A15 are dont cares during
DMA transfer.
/ACK 83 I
Parallel Port Acknowledge.
  This input is pulsed low by the printer to
indicate that it has received the data from the parallel port.  This pin
has a nominal 25 KW pull-up resistor attached to it.
ADRATE0,
ADRATE196,
46O
FDD Additional Data Rate 0,1.
  These outputs are similar to DRATE0,
1.  They are provided in addition to DRATE0, 1.  They reflect the
currently selected FDC data rate, (bits 0 and 1 in the Configuration
Control Register (CCR) or the Data Rate Select Register (DSR),
whichever was written to last).  ADRATE0 is configured when bit 0 of
ASC is 1.  ADRATE1 is configured when bit 4 of ASC is 1.  (See IRQ5
and DENSEL for further information).
/AFD 76 I/O
Parallel Port Automatic Feed XT.
  W hen this signal is low, the printer
automatically line feed after printing each line.  This pin is in a tristate
condition 10 ns after a 0 is loaded into the corresponding Control
Register bit.  The system should pull this pin high using a 4.7 KW
resistor.
AEN 18 I
Address Enable.
  W hen this input is high, it disables function selection
via A15-A0.  Access during DMA transfer is not affected by this pin.
/ASTRB 79 O
EPP Address Strobe.
  This signal is used in EPP mode as address
strobe.  It is an active low signal.
BADDR0,
BADDR172,
71I
Base Address.
  These bits determine one of the four base addresses
from which the Index and Data Registers are offset.   An internal pull-
down resistor of 30 KW is on this pin.  Use a 10 KW resistor to pull this
pin to VCC.
BOUT1,
BOUT271,
63O
UARTs Baud Output.
  This multi-function pin supports the associated
serial channel Baud Rate generator output signal if the test mode is
selected in the Power and Test Configuration Register and the DLAB
bit (LCR7) is set.  After the Master Reset, this pin offers the SOUT
function.
BUSY 82 I
Parallel Port Busy.
  This pin is set high by the printer when it cannot
accept another character.  It has a nominal 25 KW pull-down resistor
attached to it.
CFG0 63 I
SIO Configuration Strap.
  These CMOS inputs select 1 of 4 default
configurations in which the PC97338 powers up.  An internal pull-down
resistor of 30 KW is on this. Use a 10 KW resistor to pull these pins to
VCC.   CFG0 is multiplexed with SOUT2, BOUT2 and IRTX.
/CS0,
/CS151, 3 O
Programmable Chip Select.  
/CS0, 1 are programmable chip select
and/or latch enable and/or output enable signals that can be used as
game port, I/O expand, etc.  The decoded address and the assertion
conditions are configured via the 97338VJG’s configuration registers. 
						

							Major Chips Description 2-53
Table 2-6 NS97338VJG Pin Descriptions
PinNo.I/ODescription
/CTS1,
/CTS272, 64 I
UARTs Clear to Send.  W hen low, this indicates that the modem or
data set is ready to exchange data.  The /CTS signal is a modem
status input.  The CPU tests the condition of this /CTS signal by
reading bit 4 (CTS) of the Modem Status Register (MSR) for the
appropriate serial channel.  Bit 4 is the complement of the CTS signal.
Bit 0 (DCTS) has no effect on the transmitter.
/CTS2 is multiplexed with A13.  W hen it is not selected, it is masked to
“0”.
NOTE: 
Whenever the MSR DCTS bit is set, an interrupt is generated if
Modem Status interrupts are enabled.
D7-D0 10-17 I/O
Data.  These are bidirectional data lines to the microprocessor.  D0 is
the LSB and D7 is the MSB.  These signals have a 24 mA (sink)
buffered outputs.
/DACK0
/DACK1
/DACK2
/DACK353,
52,
3
49I
DMA Acknowledge 0, 1, 2, 3.  These active low inputs acknowledge
the DMA request and enable the /RD and /W R inputs during a DMA
transfer. It can be used by one of the following: FDC or Parallel Port.  If
none of them uses this input pin, it is ignored.  If the device which uses
on of this pins is disabled or configured with no DMA, this pin is also
ignored.
DACK3 is multiplexed with DRATE1, MSEN1, /CS0 and SIRQI2.
/DCD1, /DCD2 75, 67 I
UARTs Data Carrier Detect.  W hen low, this indicates that the modem
or data set has detected the data carrier.  The /DCD signal is a modem
status input.  The CPU tests the condition of this /DCD signal by
reading bit 7 (DCD) of the Modem Status Register (MSR) for the
appropriate serial channel.  Bit 7 is the complement of the DCD signal.
Bit 3 (DDCD) of the MSR indicates whether DCD input has changed
state since the previous reading of the MSR.
NOTE: 
Whenever the MSR DDCD bit is set, an interrupt is generated if
Modem Status interrupts are enabled.
DENSEL
(Normal Mode)46 O
FDC Density Select.  DENSEL indicates that a high FDC density data
rate (500 Kbs, 1 Mbs or 2 Mbs) or a low density data rate (250 or 300
Kbs) is selected.  DENSEL is active high for high density (5.25-inch
drives) when IDENT is high, and active low for high density (3.5-inch
drives) when IDENT is low.  DENSEL is also programmable via the
Mode command.
DENSEL
(PPM Mode)76 O
FDC Density Select.  This pin offers an additional Density Select
signal in PPM Mode when PNF=0.
/DIR
(Normal Mode)39 O
FDC Direction.  This output determines the direction of the floppy disk
drive (FDD) head movement (active = step-in; inactive = step-out)
during a seek operation.  During reads or writes, DIR is inactive.
/DIR
(PPM Mode)78 O
FDC Direction.  This pin offers an additional Direction signal in PPM
Mode when PNF = 0.
/DR0,
/DR1
(Normal Mode)42, 43 O
FDC Drive Select 0, 1.  These are the decoded drive select outputs
that are controlled by Digital Output Register bits D0, D1.  The Drive
Select outputs are gated with DOR bits 4-7.  These are active low
outputs.  They are encoded with information to control four FDDs when
bit 4 of the Function Enable Register (FER) is set.  DR0 exchanges
logical drive values with DR1 when bit 4 of Function Control Register is
set.