Acer Travelmate 7300 Service Guide

							1-38Service Guide
1.6.22  Hard Disk Drive
Table 1-33 Hard Disk Drive Specifications
ItemSpecification
Vendor & Model Name IBM DTCA-23240 IBM DTCA-24090
Drive Format
Capacity (GB) 4.09 3.24
Bytes per sector 512 512
Logical heads 16 16
Logical sectors 63 63
Logical cylinders 6304 7944
Physical read/write heads 4
Disks 2
Rotational speed (RPM) 4000 4000
Performance Specifications
Buffer size (KB) 512 512
Interface ATA-2 ATA-2
Data transfer rate (disk-buffer, Mbytes/s) 6.47 ~ 10.45 6.47 ~ 10.45
Data transfer rate (host-buffer, Mbytes/s) 33.3 (Ultra DMA Mode-2) 33.3 (Ultra DMA Mode-2)
DC Power Requirements
Voltage tolerance (V)
5 ± 5%
1.6.23 Keyboard
Table 1-34 Keyboard Specifications
ItemSpecification
Vendor & Model Name SMK KAS1902-
0211R (English)SMK KAS1902-
0232R (Germany)SMK KAS1902-0251R
(Japanese)
Total number of keypads 84 keys 85 keys 88 keys
Windows95 keys Yes, (Logo key /
Application key)Yes, (Logo key /
Application key)Yes, (Logo key /
Application key)
External PS/2 keyboard hot plug Yes
Internal & external keyboard
work simultaneouslyYes
Keyboard automatic tilt feature Yes
The keyboard has the option of automatically tilting to a six-degree
angle whenever you open the lid.  This feature is set by an keyboard
automatic tilt latch on the rear side of the system unit. 
						

							System Introduction1-39
1.6.24 Battery
Table 1-35 Battery Specifications
ItemSpecification
Vendor & Model Name Sony BTP-S31
Battery Gauge Yes
Battery type Li-Ion
Cell capacity 2700mAH
Cell voltage 3.6V
Number of battery cell 6-Cell
Package configuration 3 serial, 2 parallel
Package voltage 10.8V
Package capacity 58.3WH
Second battery No
1.6.25 DC-DC Converter
DC-DC converter generates multiple DC voltage level for whole system unit use, and offer charge
current to battery.
Table 1-36 DC-DC Converter Specifications
ItemSpecification
Vendor & Model Name Ambit T62.036.C.00
Input voltage (Vdc) 7 -19
Short circuit protection The DC/DC converter shall be capable of withstanding a continuous short-circuit
to any output without damage or over stress to the component, traces and cover
material under the DC input 7~19 V from AC adapter or 18V from battery. It
shall operate in shut down mode for the shorting of any de output pins.
Output ratingBMCVCC
(5V)
P5VR
(3.3V)
P3VR
(3.3V)
P12VR
(+12V)
CHRGOUT
(0 ~ 3.5A)
Load range (w/load, A) 0 ~ 0.5 0 ~ 2.5 0 ~ 3 0 ~ 0.5 0 ~ 4
Load range (w/load, V) - - - - 0 ~ 13.5
Voltage ripple + noise
(max., mV)100 100 100 100 400 
						

							1-40Service Guide
1.6.26 DC-AC Inverter
DC-AC inverter is used to generate very high AC voltage, then supply to LCD CCFT backlight use.
The DC-AC inverter area should be void to touch while the system unit is turned on.
Table 1-37 DC-AC Inverter Specifications
ItemSpecification
Vendor & Model Name Ambit T62-055.C.00 Ambit T62-088.C.00
Used LCD typeIBM ITSV50D (12.1” TFT) LG LP133X1 (13.3” TFT)
Input voltage (V) 7 ~ 19 7 ~ 19
Output voltage (Vrms, with load) 650 (typ.) 650 (typ.)
Output current (mArms, with load) 2 ~ 5 2.5 ~ 5
1.6.27 AC Adapter
Table 1-38 AC Adapter Specifications
ItemSpecification
Vendor & Model Name ADP-45GB-C1
Input Requirements
Nominal voltages (V) 90 - 264 Vac, single phase
Nominal frequency (Hz) 47 -63
Inrush current (A) (cold start) 50 (@115Vac), 100 (@230Vac)
Efficiency 84% (min., 115Vac) full load
Output Ratings
Output voltage (V) +18
Noise + Ripple (mV) 300 mVp-p
Load (A) 0 (min.), 2.5 (max.)
Dynamic Output Characteristics
Turn-on delay time 2 sec (max., @ 115 Vac)
Hold up time 5 ms (min., @ 115 Vac input) full load
Short circuit protection Output can be shorted without damage (auto recovery)
Dielectric Withstand Voltage
Primary to secondary 3000 Vac (10mA for 1 second or 4242Vdc 10mA for 1 second)
Leakage current .25mA (max. @254Vac 60Hz)
Regulatory Requirements
1.   CISPR 55022 and CISPR55014, class B (@230Vac and 115Vac) requirements. [Scandinavia]
2.   FCC 47 CFR Part15, class B (115Vac) with 6db of margin. [USA] 
						

							System Introduction1-41
1.7  System Block Diagrams
1.7.1  System Functional Block Diagram
“7100” System Block Diagram
MAIN BOARD.  Intel Tillamook/Deschutes MMO   
.  PCI IDE
.  Intel 430TX Core Logic chipset    
.  NS87338 Super I/O controller
.  512KB L2 cache memory   
.  256KB PMU/System/Video BIOS
.  32~128MB EDO/SDRAM memory   
.  6832 CardBus chip
.  NeoMagic NMG4 VGA chip   
.  IBM IrDA/FIR
.  2MB video memory   
.  DMI 2.0 with Intel LDCM
Ext. Keyboard
 or  PS/2 Mouse
 6-pin
       25-pin15-pin
 9-pinParallel
PortCRT
PortSerial
Port
DC-DC
Converter
DC-AC
Inverter
 12.1” SVGA TFT,
 13.3” XGA TFT
  2.5” 12.7mm HDD
  3.0GB+
45w
AC AdapterPri-Battery
84/85-key
auto-tilt-up
Keyboard
10.8V 5500mAh Li-Ion
3P3S (10w/cell) 3.6V/cell
100V ~ 240V
Auto-Switching
 Touchpad
Charger
68-pin
Two CardBus
Slots
   240-pin
   Docking
   Line-in jack
Line-out jack
soDIMM x 2
32~128MB
Swappable FDD,
CD-ROM, removable
3” HDD module
Figure 1-13 System Functional Block Diagram 
						

							1-42Service Guide
1.7.2  System Bus Block Diagram
970T SYSTEM BLOCK DIAGRAM
440BX
SYSTEM
 CONTROLLER
HOST BUS
L2 CACHE
32KX32 MD[0..63]
MA[0..13] SDRAM
2, 4, 8MX64
2 BANKS
DIMCLK(60/66MHz)PCI BUS
14.318MHzINTEL
 CPU
CLOCK
 GEN.
 IMICS651HCLK(60/66MHz)
PCICLK(30/33MHz)
USB(48MHz)
IDE
CDPIIX4
PCI TO EIO BRG
   IDE,USB, RTCUSB VIDEO CTRL
     NM2160 CARDBUS
 CTRL
 PD6832 
ZVDOCKING
10 Mbps
Ethernet
CRT LCD EIO BUS
16 MHz
SMC
 83C55224 MHz
14.318MHz
KBC
80C51SLFlash
BIOSAUDIO
NMA1SUPER I/O
   NS97338
RTC 32.768KHz
 SIO PIO FDD FIR KeyBoard, Mouse
Touch Pad
MMO MODULE
Figure 1-14 System Bus Block Diagram 
						

							System Introduction1-43
1.8 Environmental Requirements
Table 1-39 Environmental Requirements
ItemSpecification
Temperature
Operating (ºC) +5 ~ +35
Non-operating(ºC)(unpacked) -10 ~ +60
Non-operating(ºC)(storage package) -20 ~ +60
Humidity
Operating (non-condensing) 20% ~ 80%
Non-operating (non-condensing)
(unpacked)20% ~ 80%
Non-operating (non-condensing) (storage
package)20% ~ 90%
Operating Vibration (sine mode)
Operating 5 -25.6Hz, 0.38mm;  25.6 -250Hz, 0.5G
Sweep rate > 1 minute / octave
Number of test cycles 2 / axis (X,Y,Z)
Non-operating Vibration (unpacked/sine mode)
Non-operating 5 -27.1Hz, 0.6G;  27.1 -50Hz, 0.016”;  50 -500Hz, 2.0G
Sweep rate > 0.5 minutes / octave
Number of text cycles 4 / axis (X,Y,Z)
Non-operating Vibration (packed/sine mode)
Non-operating 5 -62.6Hz, 0.51mm;  62.6 -500Hz, 4G
Sweep rate > 0.5 minutes / octave
Number of text cycles 4 / axis (X,Y,Z)
Shock
Non-operating (unpacked) 40G peak, 11±2ms, half-sine
Non-operating (packed) 50G peak, 11±2ms, half-sine
Altitude
Operating 10,000 feet
Non-operating 40,000 feet
ESD
Air discharge 8kV (no error)
12.5kV (no restart error)
15kV (no damage)
Contact discharge 4kV (no error)
6kV (no restart error)
8kV (no damage) 
						

							1-44Service Guide
1.9 Mechanical Specifications
Table 1-40 Mechanical Specifications
ItemSpecification
Weight (includes battery and FDD)
   12.1 TFT SVGA LCD and 12.5mm HDD
   Adapter3.3 kgs (7.2 lbs)
230 g (0.52 lb)
Dimensions
   round contour
   main footprint297~313mm x 233~240mm x 50~53mm
11.7” x 9.1” x 2” 
						

							&KDSWHU &KDSWHU
Major Chips Description
Major Chips Description 2-1
This chapter discusses the major components.
2.1  Major Component List
Table 2-1 Major Chips List
ComponentVendorDescription
PIIX4(82371AB) Intel South Bridge
NM2160 NeoMagic Flat Panel Video Accelerator
NMA1 NeoMagic Audio chip
87C552 Philips Single-chip 8-bit controller for SMC
(System Management Controller)
NS97338 NS (National Semiconductor) Super I/O controller
CL-PD6832 Cirrus Logic PCI-to-CardBus Host Adapter
T62.036.C.00 Ambit DC-DC Converter
T62.088.C.00
T62.055.C.00Ambit DC-AC Inverter 
						

							2-2Service Guide
2.2  Intel PIIX4
PIIX4 is a multi-function PCI device that integrates many system-level functions.
PCI to ISA/EIO Bridge
PIIX4 is compatible with the PCI Rev 2.1 specification, as well as the IEEE 996 specification for the
ISA (AT) bus. On PCI, PIIX4 operates as a master for various internal modules, such as the USB
controller, DMA controller, IDE bus master controller, distributed DMA masters, and on behalf of ISA
masters. PIIX4 operates as a slave for its internal registers or for cycles that are passed to the ISA
or EIO buses. All internal registers are positively decoded.
PIIX4 can be configured for a full ISA bus or a subset of the ISA bus called the Extended IO (EIO)
bus. The use of the EIO bus allows unused signals to be configured as general purpose inputs and
outputs. PIIX4 can directly drive up to five ISA slots without external data or address buffering. It
also provides byte-swap logic, I/O recovery support, wait-state generation, and SYSCLK generation.
X-Bus chip selects are provided for Keyboard Controller, BIOS, Real Time Clock, a second
microcontroller, as well as two programmable chip selects.
PIIX4 can be configured as either a subtractive decode PCI to ISA bridge or as a positive decode
bridge. This gives a system designer the option of placing another subtractive decode bridge in the
system (e.g., an Intel 380FB Dock Set).
IDE Interface (Bus Master capability and synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and
CD ROMs.
Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to
14 Mbytes/sec and Bus Master IDE transfers up to 33 Mbytes/sec. It does not consume any ISA
DMA resources.  The IDE interface integrates 16x32-bit buffers for optimal transfers.
PIIX4’s IDE system contains two independent IDE signal channels. They can be electrically isolated
independently, allowing for the implementation of a “glueless” Swap Bay. They can be configured to
the standard primary and secondary channels (four devices) or primary drive 0 and primary drive 1
channels (two devices).  This allows flexibility in system design and device power management.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently
programmable channels. Channels [0:3] are hardwired to 8-bit, count-by-byte transfers, and
channels [5:7] are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels
can be programmed to support fast Type-F transfers. The DMA controller also generates the ISA
refresh cycles.
The DMA controller supports two separate methods for handling legacy DMA via the PCI bus. The
PC/PCI protocol allows PCI-based peripherals to initiate DMA cycles by encoding requests and
grants via three PC/PCI REQ#/GNT# pairs. The second method, Distributed DMA, allows reads and
writes to 82C37 registers to be distributed to other PCI devices. The two methods can be enabled
concurrently. The serial interrupt scheme typically associated with Distributed DMA is also
supported. 
						

							Major Chips Description 2-3
The timer/counter block contains three counters that are equivalent in function to those found in one
82C54 programmable interval timer. These three counters are combined to provide the system timer
function, refresh request, and speaker tone. The 14.31818-MHz oscillator input provides the clock
source for these three counters.
PIIX4 provides an ISA-Compatible interrupt controller that incorporates the functionality of two
82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two
internal interrupts are possible. In addition, PIIX4 supports a serial interrupt scheme. PIIX4 provides
full support for the use of an external IO APIC.
All of the registers in these modules can be read and restored. This is required to save and restore
system state after power has been removed and restored to the circuit.
Enhanced Universal Serial Bus (USB) Controller
The PIIX4 USB controller provides enhanced support for the Universal Host Controller Interface
(UHCI). This includes support that allows legacy software to use a USB-based keyboard and
mouse.
RTC
PIIX4 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed
RAM. The real-time clock performs two key functions: keeping track of the time of day and storing
system data, even when the system is powered down. The RTC operates on a 32.768-kHz crystal
and a separate 3V lithium battery that provides up to 7 years of protection.
The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two
8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of
passwords or other system security information.
The RTC also supports a date alarm, that allows for scheduling a wake up event up to 30 days in
advance, rather than just 24 hours in advance.
GPIO and Chip Selects
Various general purpose inputs and outputs are provided for custom system design. The number of
inputs and outputs varies depending on PIIX4 configuration. Two programmable chip selects are
provided which allows the designer to place devices on the X-Bus without the need for external
decode logic.
Pentium® and Pentium® II Processor Interface
The PIIX4 CPU interface allows connection to all Pentium and Pentium II processors. The Sleep
mode for the Pentium II processors is also supported.