Acer Travelmate 7300 Service Guide

							2-34Service Guide
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
108 FPBACK O
Flat Panel Backlight This is used to control the backlight power to
the panels or as a General Purpose Output Pin as defined by
register CR2F bits 3&2
7
6
5
4
3
2
176
174
172
171
170
169
18
17
16
15
14
13
117
118
119
120
121
122
123
124
126
127
128
129
130
131
135
137
139
140PDATA35
PDATA34
PDATA33
PDATA32
PDATA31
PDATA30
PDATA29
PDATA28
PDATA27
PDATA26
PDATA25
PDATA24
PDATA23
PDATA22
PDATA21
PDATA20
PDATA19
PDATA18
PDATA17/
LCD_ID0
PDATA16/
LCD_ID1
PDATA15/
LCD_ID2
PDATA14/
LCD_ID3
PDATA13
PDATA12
PDATA11
PDATA10
PDATA9
PDATA8
PDATA7
PDATA6
PDATA5
PDATA4
PDATA3
PDATA2
PDATA1
PDATA0O
I/O
I/O
I/O
I/OPanel data These pins are used to provide the data interface to
different kinds of panels. The following table shows the functions
of these pins based on the selected panel type
LCD_ID[3..0] pins are general purpose read only bits which can be
used for panel identification.  During RESET# these LCD_ID pins
are inputs. The state of these bits are reflected in register CR2Eh
bits 3:0. The state of these bit can also be sampled anytime on-
the-fly through register GR17 bit-3. Internally these pins are pulled-
up, recommended external pull down resistor value is 22k ohm
CRT Interface
90 VSYNC O
T/SCRT Vertical Sync This output is the vertical synchronization
pulse for the CRT monitor
89 HSYNC O
T/SCRT Horizontal sync This output is the horizontal synchronization
pulse for the CRT monitor
98 R O
(Analog)RED This DAC analog output drives the CRT interface
97 G O
(Analog)GREEN  This DAC analog output drives the CRT interface 
						

							Major Chips Description 2-35
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
96 B O
(Analog)BLUE This DAC analog output drives the CRT interface
101 REXT I
(Analog)DAC Current reference This pin is used as a current reference by
the internal DAC. Please refer to the NM2160 system schematics
for the external circuit
TV interface
79 CSYNC O
T/SComposite Sync This output is the composite synchronization
signal for RGB-to-NTSC or PAL/SECAM External Analog Encoders
74 NTSC_PAL O
T/SNTSC/PAL/SECAM Encoding Selection This pin is used to select
the mode NTSC or PAL/SECAM in which the external analog
encoder need to be driven
147 FSC O
Sub-Carrier Frequency Selection This pin provides an
appropriate Sub-carrier frequency 1xfsc or 4xfsc to an external
NTSC or PAL/SECAM analog encoder
98 R O
(Analog)RED This DAC analog video red component output is to drive the
external RGB-to-NTSC or PAL/SECAM analog encoders
97 G O
(Analog)GREEN This DAC analog video green component output is to
drive the external RGB-to-NTSC or PAL/SECAM analog encoders
96 B O
(Analog)BLUE This DAC analog video blue component is to drive the
external RGB-to-NTSC or PAL/SECAM analog encoders external
Power Management
76 Standby/
Status1I/O
Standby/Status1 The direction of the pin is controlled by GR18 bit
3. In output mode, this pin indicates the state of standby mode.
The state of this pin is reflected in register CR25 bit 5 and can be
used as a status pin
77 Suspend I/O
Suspend This pin can be configured as control Suspend input or
status Suspend output. The active high input mode is used for
controlling hardware Suspend. When asserted NM2160 is forced
into suspend mode where all the inputs are disabled and chip goes
into the low power mode NM2160 will come out of suspend only by
de-asserting this pin
77 Suspend I/O During output mode, this pin will indicate the software suspend
status
75 Activity I/O
Activity This pin when in input mode and asserted indicates the
system activity. A high on this pin can be used to reset internal
timers. This pin when in output mode is a General Purpose Output
pin as defined by CR2F bits 5&4, which can be used to control the
IMI chip for reduced EMI
82 RTC32K/
Status2I/O
Real Time Clock 32Khz/Status2 This pin is used to feed 32 kHz
from an external source. It is used to generate the refresh timing
for the internal display memory during Standby and software
Suspend modes. 14  MHz can be used to generate the memory
refresh timing in above modes. / General purpose Status bit 3, can
be read from register CR27 bit 0
ZV Interface 
						

							2-36Service Guide
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
167
166
165
164
163
162
161
160UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0I
Chrominance Data 7:0 These are the 8-bits of chrominance data
that are input to the ZV port of NM2160
159
158
155
152
151
150
149
148Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0I
Luminance Data 7:0 These are the 8-bits of luminance data that
are input to the ZV port of NM2160
144 HREF I
Horizontal Synchronization Pulse: This input signal provides the
horizontal synchronization pulse to the ZV port
168 PCLK I
Video Clock This signal is used to clock the valid video data and
the HREF signal into the ZV Port. The maximum rate is 16 MHz.
During display time, rising edge of PCLK is used to clock the 16-bit
pixel data into the ZV Port
146 VS I
Vertical SYNC This signal supplies the Vertical synchronization
pulse to the ZV Port of NM2160
Miscellaneous Pins
87 MTEST# I
Memory test This active low signal is used for internal memory
testing. This should be tied high for normal system operation
145 CLKRUN# I/O
O/DClockrun The master device will control this signal to the NM2160,
according to the Mobile computing PCI design guide.  If this signal
is sampled high by the NM2160 and the PCI clock related
functions are not completed then it will drive this signal Low to
request the Central Clock Resource for the continuation of the PCI
clock. This function can be Enabled/Disabled through reg. GR12
bit 5
110 VGADIS I
VGA Disable This pin when active disables all the accesses to the
NM2160 controller, but maintains all the screen refreshes.  GR12
bit-4 enables/disables this feature.
NOTE: When driven by an external source, the swing on this pin
should not be above LVDD
11 DDC2BD I/O
O/DDDC Data pin
12 DDC2BC I/O
O/DDDC Clock pin
Power pins
10, 29, 44,
59, 80, 114,
125, 138,
153VSSP Host bus interface ground, ZV interface ground and Panel
Interface ground
23, 64, 109,
88GND Logic ground 
						

							Major Chips Description 2-37
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
136, 154,
173DVSS DRAM ground
105 AVSSM Analog ground for MCLK synthesizer
104 AVSSV Analog ground for VCLK synthesizer
99 AVSSR1 Analog ground for DAC
100 AVSSR2 Analog ground for DAC current reference
91 AVSSX1 Analog ground for crystal oscillator
25, 42, 57,
78HVDD
Host bus interface VDD.(+5v or +3v) Includes the PCI, VL, CRT,
Power management, External clock pins(PMCLKI and PVCLKI)
and Miscellaneous pins
27,62,107 VDD Logic VDD(+3V only)
134, 156,
175DVDD DRAM VDD(+3V only)
116, 132, 1,
8LVDD Panel VDD(+5v or +3v)
157 MMVDD ZV Port VDD(+5V /+3V)
106 AVDDM Analog VDD for MCLK synthesizer(+3V only)
103 AVDDV Analog VDD for VCLK synthesizer(+3V only)
95 AVDDR1 Analog VDD for DAC(+3V only)
102 AVDDR2 Analog VDD for DAC current reference(+3V only)
94 AVDDX1
Analog VDD for crystal oscillator.  If external 14 MHz source is
used AVDDX1 can be +5V or +3V based on the XTAL1 clock
source levels
133 VBB A capacitor across ground to this pin is required. Please refer to
NM2160 system schematics for more details 
						

							2-38Service Guide
2.4 NMA1
NMA1 is a single audio chip that integrates OPL3 FM and its DAC, 16bit Sigma-delta CODEC, MPU401
MIDI interface, and a 3D enhanced controller including all the analog components which is suitable for
multi-media application. This LSI is fully compliant with Plug and Play ISA 1.0a, and supports all the
necessary features, i.e. 16bit address decode, more IRQs and DMAs in compliance with PC’96. This LSI
also supports the expandability, i.e. Zoomed Video and Modem interface in a Plug and Play manner, and
power management(power down, power save, partial power down, and suspend/resume) that is
indispensable with power-conscious application.
2.4.1 Features
· Built-in OPL3 FM Synthesizer
· Supports Sound Blaster Game compatibility
· Supports Windows Sound System compatibility
· Supports Plug&Play ISA 1.0a compatibility
· Full Duplex operation
· Built-in MPU401 Compatible MIDI I/O port
· Built-in the 3D enhanced controller including all the analog components, Supports 16-bit
addresss decode, Port for external Wavetable synthesizer
· Hardware and software master volume control
· Supports monaural input
· 24 mA TTL bus drive capability
· Supports Power Management(power down, power save, partial power down, and
suspend/resume)
· +5V/+3.3V power supply for digital, 5V power supply for analog
· 100 pin SQFP package 
						

							Major Chips Description 2-39
2.4.2 Block Diagram
Figure 2-4 NMA1 Block Diagram 
						

							2-40Service Guide
2.4.3 Pin Diagram
Figure 2-5 NMA1 Pin Diagram 
						

							Major Chips Description 2-41
2.4.4 Pin Descriptions
Conventions used in the pin description types:
I+: Input Pin with Pull up Resistor
T: TTL-tri-state output pin
Schmitt: TTL-Schmitt input pin
O+: Output Pin with Pull up Resistor
Table 2-4 NMA1 Pin Descriptions
Pin nameNumberI/ODescription
ISA bus interface: 36 pins
D7-0 8 I/O Data Bus
A15-0 12 I Address Bus
AEN 1 I Address Bus Enable
/IOW 1 I Write Enable
/IOR 1 I Read Enable
RESET 1 I Reset
IRQ3,5,7,9,10,11 6 T Interrupt request
DRQ0,1,3 3 T DMA Request
/DACK0,1,3 3 I DMA Acknowledge
Analog Input&Output: 24 pins
OUTL 1 O Left mixed analog output
OUTR 1 O Right mixed analog output
VREFI 1 I Voltage reference input
VREFO 1 O Voltage reference output
AUX1L 1 I Left AUX1 input
AUX1R 1 I Right AUX1 input
AUX2L 1 I Left AUX2 input
AUX2R 1 I Right AUX2 input
LINEL 1 I Left LINE input
LINER 1 I Right LINE input
MIC 1 I MIC input
MIN 1 I Monaural input
TRECL 1 Left Treble capacitor
TRECR 1 Right Treble capacitor
SBFLTL 1 Left SBDAC filter
SBFLTR 1 Right SBDAC filter
SYNSHL 1 Left SYNDAC sample/ hold capacitor
SYNSHR 1 Right SYNDAC sample/ hold capacitor
ADFLTL 1 Left input filter 
						

							2-42Service Guide
Table 2-4 NMA1 Pin Descriptions
Pin nameNumberI/ODescription
ADFLTR 1 Right input filter
VOCOL 1 O Left voice output
VOCOR 1 O Right voice output
VOCIL 1 I Left voice input
VOCIR 1 I Right voice input
Miscellaneous pins: 14 pins
SYEN 1 I External synthesizer enable input
SYCS 1 O External synthesizer chip select output
SYCLK 1 I External synthesizer clock input or ZV  clock input
SYLR 1 I External synthesizer L/R clock input or ZV L/R clock input
SYIN 1 I External synthesizer data input or ZV data input
SYCLKO 1 O External synthesizer master clock output
RSVD 8 Reserved for future use
Others: 27 pins
RXD 1 I+ MIDI Data Receive
TXD 1 O MIDI Data Transfer
/VOLUP 1 I+ Hardware Volume(Up)
/VOLDW 1 I+ Hardware Volume(Down)
X33I 1 I 33.8688MHZ
X33O 1 O 33.8688MHZ
X24I 1 I 24.576MHZ
X24O 1 O 24.576MHZ
AVDD 2 Analog Power Supply(put on +5.0V)
DVDD 3 Digital Power Supply(put on +5.0V or +3.3V)
AVSS 2 Analog GND
DVSS 7 Digital GND 
						

							Major Chips Description 2-43
2.5  Philips 87C552 System Management Controller
The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and
is a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the
80C51.
The 87C552 contains a 8kx8 a volatile 256x8 read/write data memory, five 8-bit I/O ports, one 8-bit
input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit
timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt
structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART
and I
2C-bus), a “watchdog” timer and on-chip oscillator and timing circuits. For systems that require
extra capability, the 87C552 can be expanded using standard TTL compatible memories and logic.
In addition, the 87C552 has two software selectable modes of power reduction—idle mode and
power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and
interrupt system to continue functioning. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be inoperative.
The device also functions as an arithmetic processor having facilities for both binary and BCD
arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-
byte, 45 two-byte, and 17 three-byte. W ith a 16MHz (24MHz) crystal, 58% of the instructions are
executed in 0.75ms (0.5ms) and 40% in 1.5ms (1ms). Multiply and divide instructions require 3ms
(2ms).
2.5.1 Features
· 80C51 central processing unit
· 8kx8 EPROM expandable externally to 64k bytes
· An additional 16-bit timer/counter coupled to four capture registers and three compare registers
· Two standard 16-bit timer/counters
· 256x8 RAM, expandable externally to 64k bytes
· Capable of producing eight synchronized, timed outputs
· A 10-bit ADC with eight multiplexed analog inputs
· Two 8-bit resolution, pulse width modulation outputs
· Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs
· I2C-bus serial I/O port with byte oriented master and slave functions
· Full-duplex UART compatible with the standard 80C51
· On-chip watchdog timer
· Speed ranges: 16MHz
· Extended temperature ranges
· OTP package available