Acer Travelmate 7300 Service Guide
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$SSHQGL[( $SSHQGL[( BIOS POST Checkpoints BIOS POST Checkpoints E-1 This appendix lists the POST checkpoints of the notebook BIOS. Table E-1 POST Checkpoint List CheckpointDescription 04h · Determines if the current booting procedure is from cold boot (press reset button or turn the system on), from warm boot (press Ctrl +Alt +Del). Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to determine whether this POST is caused by a cold or warm boot. If it is a cold boot, a complete POST is performed. If it is a warm boot, the chip initialization and memory test is eliminated from the POST routine. 08h · Disables Non-Maskable Interrupt (NMI), Alarm Interrupt Enable (AIE), Periodical Interrupt Enable (PIE), and Update-ended Interrupt Enable (UIE). Note: These interrupts are disabled in order to avoid any mis-action happened during the POST routine. 09h · Initializes Intel ChipSet, V3-LS and DRAM type determination(SDRAM or EDO type) 0Ah · Intel drip GPIO pin initialization and base address assignment 10h · DMA(8237) testing & initialization 14h · System timer (8254) testing & initialization 18h · Memory refresh test; refresh occurrence verification (IRQ0) 1Ch · Verifies CMOS shutdown byte, battery and check sum Note: Several parts of the POST routine require the system to be in protected mode. When returning to real mode from protected mode, the processor is reset, therefore POST is re-entered. In order to prevent re-initialization of the system, POST reads the shutdown code stored in location 0Fh in CMOS RAM. Then it jumps around the initialization procedure to the appropriate entry point. · The CMOS shutdown byte verification assures that CMOS 0Fh area is fine to execute POST properly. · Initializes CMOS default setting · Initializes RTC time base Note: The RTC has an embedded oscillator that generates 32.768 KHz frequency. To initial RTC time base, turn on this oscillator and set a divisor to 32768 so that RTC can count time correctly. 1Eh · DRAM sizing 2Ch · Tests 128K base memory Note: The 128K base memory area is tested for POST execution. The remaining memory area is tested later. 20h · Tests keyboard controller (8041/8042) · Determines keyboard type (AT, XT, PS/2) then write default command byte upon KB type 23h · Detects whether keyboard X is depressed from system powered-on till POST or not. If yes, set BIOS Setup parameter too default settings; or keep the original settings.
E-2Service Guide Table E-1 POST Checkpoint List CheckpointDescription 24h · Tests programmable interrupt controller (8259) · Initializes system interrupt 30h · Enables system shadow RAM 34h · Memory sizing 5Ah · Changes SMBASE, copy SMI Handler. · 56h · Issues 1st software SMI to communicate with PMU. · Initializes the SMI environment. 3Fh · Enable/Disable USB function 3Ch · Initializes interrupt vectors 3Eh · Set fixed CMOS setting 4Ch · CPU clock checking · Sets the DRAM timing in correspondent to the system speed 35h · Scans PCI Devices to Initialize the PCI buffer that used by BIOS. 4Eh · Isolations for PnP ISA Card 4Fh · Configurations for PnP ISA Card · Initializes the PCI device according to ESCD data (if ESCD data is valid). · Initialize the PCI Devices by BIOS · Initialize the PCI VGA card 50h · Initializes video display Note: If system has any display card, here it should be initialized via its I/O ROM or corresponding initialization program. Exh · VGA BIOS POST. 54h · Enables video shadow RAM 58h · Displays Acer (or OEM) logo (if necessary) · Displays Acer copyright message (if necessary) · Displays BIOS serial number 5Ch · Memory testing 5Eh · Assign PCMCIA resource, enable serial IRQ 60h · External Cache sizing · Enables/disables L1/L2 cache according to the BIOS SETUP 64h · Tests keyboard interface Note: The keyboard LEDs should flash once. 68h · Enables UIE, then checks RTC update cycle Note: The RTC executes an update cycle per second. When the UIE is set, an interrupt (IRQ8) occurs after every update cycle and indicates that over 999ms are available to read valid time and date information. 70h · Parallel port testing
BIOS POST Checkpoints E-3 Table E-1 POST Checkpoint List CheckpointDescription 74h · Serial port testing 78h · Math coprocessor testing 7Ch · Reset pointing device 80h · Set security status 84h · KB device initialization · Set KB led upon setup requests · Enable KB device 86h · Issue 2nd software SMI to communicate with PMU · Enable the use of BIOS Setup, system information. and fuel gauge 6Ch · Tests and initializes FDD Note: The FDD LED should flash once and its head should be positioned. 6Dh · password checking 88h · HDD, CD testing & parameter table setup · Initializes HDD, CD enhanced features 90h · Displays POST status if necessary · Changes POST mode to default text mode 94h · Initializes I/O ROM Note: I/O ROM is an optional extension of the BIOS located on an installed add-on card as a part of the I/O subsystem. POST detects I/O ROMs and gives them opportunity to initialize themselves and their hardware environment. · Shadows I/O ROM if setup requests · Builds up free expansion ROM table 96h · Initializes PCI Card ROM · Writes ESCD data into NVRAM 97h · Writes ESCD data into NVRAM A0h · Initializes timer counter for DOS use A4h · Initializes security feature ACh · Enables NMI · Enables parity checking · Sets video mode AEh · Issues 3rd software SMI to communicate with PMU · Starts all power management timers · Checks whether system is resumed from 0V suspend or not. B0h · Clear memory buffer used for POST · Select boot device BDh · Shutdown 5 BEh · Shutdown A BFh · Shutdown B