Motorola Gm328 Gm338 Gm398 Detailed 6804112j18 E Manual
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i Table of Contents Section 1 Model Chart and Technical Specifications 1.0 GM338 Model Chart............................................................................................. 1-1 2.0 Technical Specifications ...................................................................................... 1-1 Section 2 Theory of Operation 1.0 Introduction .......................................................................................................... 2-1 2.0 UHF (450-520 MHz) Receiver ............................................................................. 2-1 2.1 Receiver Front-End ........................................................................................ 2-1 2.2 Front-End Band-Pass Filters & Pre-Amplifier ................................................. 2-2 2.3 First Mixer and High Intermediate Frequency (IF) .......................................... 2-2 2.4 Low Intermediate Frequency (IF) and Receiver Back End ............................. 2-3 3.0 UHF (450-520 MHz) Transmitter Power Amplifier (PA) 40W............................... 2-3 3.1 First Power Controlled Stage.......................................................................... 2-4 3.2 Power Controlled Driver Stage ....................................................................... 2-4 3.3 Final Stage ..................................................................................................... 2-4 3.4 Directional Coupler ......................................................................................... 2-4 3.5 Antenna Switch............................................................................................... 2-5 3.6 Harmonic Filter ............................................................................................... 2-5 3.7 Power Control ................................................................................................. 2-5 4.0 UHF (450-520 MHz) Frequency Synthesis .......................................................... 2-6 4.1 Reference Oscillator ....................................................................................... 2-6 4.2 Fractional-N Synthesizer ................................................................................ 2-6 4.3 Voltage Controlled Oscillator (VCO) ............................................................... 2-8 4.4 Synthesizer Operation .................................................................................... 2-9 Section 3 Troubleshooting Charts 1.0 Troubleshooting Flow Chart for Receiver ............................................................ 3-1 2.0 Troubleshooting Flow Chart for 40W Transmitter ................................................ 3-3 3.0 Troubleshooting Flow Chart for Synthesizer ........................................................ 3-4 4.0 Troubleshooting Flow Chart for VCO ................................................................... 3-5
ii Section 4 UHF PCB/Schematics/Parts Lists 1.0 Allocation of Schematics and Circuit Boards ....................................................... 4-1 1.1 Controller Circuits ........................................................................................... 4-1 2.0 UHF Band 2 25-40W PCB / Schematics / Parts List ........................................... 4-3 UHF Band 2 (450-520 MHz) 40W 8486250Z02 Top Side ...................................... 4-3 UHF Band 2 (450-520 MHz) 40W 8486250Z02 Bottom Side................................ 4-4 UHF Band 2 (450-520 MHz) Power Amplifier 40W ................................................ 4-5 UHF Band 2 (450-520 MHz) FRACN ..................................................................... 4-6 UHF Band 2 (450-520 MHz) Voltage Controlled Oscillator .................................... 4-7 UHF Band 2 (450-520 MHz) Receiver Front End ................................................... 4-8 UHF Band 2 (450-520 MHz) IF............................................................................... 4-9 UHF Band 2 PCB 8486250Z02 Parts List 25-40W.............................................. 4-10
1-1 Section 1 MODEL CHART AND TECHNICAL SPECIFICATIONS 1.0 GM338 Model Chart 2.0 Technical Specifications Data is specified for +25°C unless otherwise stated. GM Series, UHF Band 2, 450-520 MHz Model Description AZM25SKF9AA5GM338 450-520 MHz 25-40W (LDMOS) Item Description XGCN6114_GM338 Control Head Direct Mount X IMUE6019_ Tanapa WM 450-520 MHz 25-40W XRAE4155_BNC 470-512 MHz, 1/4 Wave Roof Mount X RAE4156_ BNC 470-494 MHz, 3.5 Gain Roof Mount XRAE4157_BNC 494-512 MHz, 5dB Gain Roof Mount X 6804112J06 GM338 User Guide x = Indicates one of each is required. General Specifications Channel Capacity GM338 128 Power Supply 13.2Vdc (10.8 - 15.6Vdc) Dimensions: H x W x D (mm) Depth excluding knobsGM338 59mm x 179mm x 198mm (25 - 40W) (add 9mm for Volume Knob) Weight GM338 1400 g Sealing:Withstands rain testing per MIL STD 810 C/D/E and IP54 Shock and Vibration: Protection provided via impact resistant housing exceeding MIL STD 810-C/D/E Dust, Salt & Fog:Protection provided via environment resistant housing exceeding MIL STD 810 C/D/E
1-2Technical Specifications *Availability subject to the laws and regulations of individual countries.Transmitter UHF *Frequencies - Full BandsplitUHF 450-520 MHz Channel Spacing12.5/20/25 kHz Frequency Stability (-30°C to +60°C, +25° Ref.)±2.0 ppm Power 25-40W Modulation Limiting ±2.5 @ 12.5 kHz ±4.0 @ 20 kHz ±5.0 @ 25 kHz FM Hum & Noise-40 dB @ 12.5kHz -45 dB @ 20/25kHz Conducted/Radiated Emission (ETS)-36 dBm 1 GHz Adjacent Channel Power-60 dB @ 12.5 kHz -70 dB @ 25 kHz Audio Response (300 - 3000 Hz)+1 to -3 dB Audio Distortion @1000Hz, 60% Rated Maximum Deviation 65 dB Adjacent Channel Selectivity (ETS) 65 dB @ 12.5 kHz 70 dB @ 20 kHz 75 dB @ 25 kHz Spurious Rejection (ETS)70 dB @ 12.5 kHz 75 dB @ 20/25 kHz Rated Audio 3W Internal 7.5W External 13W External Audio Distortion @ Rated Audio
2-1 Section 2 THEORY OF OPERATION 1.0 Introduction This Chapter provides a detailed theory of operation for the UHF circuits in the radio. For details of the theory of operation and troubleshooting for the associated Controller circuits refer to the Controller Section of this manual. 2.0 UHF (450-520 MHz) Receiver 2.1 Receiver Front-End The UHF receiver, shown in Figure 2-1, is able to cover the UHF range from 450 to 520 MHz. It consists of four major blocks: front-end bandpass filters and pre-amplifier, first mixer, high-IF, low-IF and receiver back-end . Two varactor-tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode mixer converts the signal to the first IF of 44.85 MHz. Low-side first injection is used. Figure 2-1 UHF Receiver Block Diagram Demodulator 1. Crystal Filter Mixer Va r a c t o r Tuned Filter RF Amp Va r a c t o r Tuned Filter Pin Diode Antenna Switch RF Jack Control Voltage from PCICFirst LO from FGU Recovered Audio RSSI Second LO 2. Crystal Filter 455kHz Filter (25kHz)455kHz Filter (25kHz) 455kHz Filter (12.5kHz)455kHz Filter (12.5kHz)SwitchSwitchSwitchSwitch Limiter 1. IF Amp 2. IF Amp Filter Bank Selection from Synthesizer IC Harmonic Filter BWSELECT
2-2UHF (450-520 MHz) Receiver The two 2-pole 44.85 MHz crystal filters in the high-IF section and two pairs of 455 kHz ceramic filters in the low-IF section provide the required adjacent channel selectivity .The correct pair of ceramic filters for 12.5 or 25KHz channel spacing is selected via control line BWSELECT. The second IF at 455 kHz is mixed, amplified, and demodulated in the IF IC. The processing of the demodulated audio signal is performed by an audio processing IC located in the controller section. 2.2 Front-End Band-Pass Filters & Pre-Amplifier The received signal from the radio’s antenna connector is first routed through the harmonic filter and antenna switch, which are part of the RF power amplifier circuits, before being applied to the receiver pre-selector filter (C5001, C5002, D5001, and related components). The 2-pole pre-selector filter, tuned by the varactor diodes D5001 and D5002, pre-select the incoming signal (RXIN) from the antenna switch to reduce spurious effects to the stages that follow. The tuning voltage (FECTRL_1), ranging from 2 volts to 8 volts, is controlled by pin 20 of PCIC (U5501) in the transmitter section. A dual hot carrier diode (D5003) limits any inband signal to 0 dBm to prevent damage to the pre- amplifier. The RF pre-amplifier is an SMD device (Q5003) with collector base feedback to stabilize gain, impedance, and intermodulation. The collector current of approximately 11-16 mA is drawn from the 9.3 volt supply via L5003 and R5002. A 3dB pad (R5006,R5007, R5011, and R5008 - R5010) stabilizes the output impedance and intermodulation performance. A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal. Varactor diodes D5004 and D5005 are controlled by the same signal, FECTRL_1, which controls the pre-selector filter. A following 1 dB pad (R5013 - R5015) stabilizes the output impedance and intermodulation performance. 2.3 First Mixer and High Intermediate Frequency (IF) The signal from the front-end is converted to the first IF (44.85 MHz) using cross-over, quad diode mixer D5051. Its ports are matched for incoming RF signal conversion to the 44.85 MHz IF using low side injection via matching transformers T5051 and T5052. The injection signal (RXINJ) coming from the RX VCO buffer (Q5332) is filtered by the lowpass filter consisting of L5053, L5054, and C5053 - C5055 followed by matching transformer T5052 which has a level of approximately 15dBm. The mixer IF output signal from transformer T5501, pin 2 is fed to the first two-pole crystal filter (FL3101). The filter output in turn is matched to IF amplifier Q3101 which is actively biased using collector-base feedback resistors R3101and R3106 to provide a current drain of approximately 5 mA drawn from the 5 volt supply. The output impedance of this device is matched to the second two-pole crystal filter FL3102. The signal is further amplified by a preamplifier Q3102 before going to pin 1 of IFIC (U3101). A dual, hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at RF input levels above -27 dBm.
UHF (450-520 MHz) Transmitter Power Amplifier (PA) 40W 2-3 2.4 Low Intermediate Frequency (IF) and Receiver Back End The 44.85 MHz first IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the IF IC the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator to produce a low IF signal of 455 kHz. The second LO frequency is determined by crystal Y3101. The second IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters (FL3112 and FL3114) for 20/25 kHz channel spacing, or FL3111 and FL3113/F3115 for 12.5 kHz channel spacing. These pairs are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter input pin of the IF IC (pin 14). The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% deviation) from U3103, pin 8 (DISCAUDIO) which is fed to ASFIC_CMP U0221, pin 2 (part of the controller circuits). A received signal strength indicator (RSSI) signal is available at U3101, pin 5, which has a dynamic range of 70 dB. The RSSI signal is interpreted by the µP (U0101, pin 63) and is available at accessory connector J0501-15. 3.0 UHF (450-520 MHz) Transmitter Power Amplifier (PA) 40W The radio’s 40W PA is a three stage amplifier used to amplify the output from the VCOBIC to the radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U5401) is adjustable, controlled by pin 4 of PCIC (U5501). It is followed by an LDMOS stage (Q5421) and LDMOS final stage (Q5441). Figure 2-2 UHF Transmitter Block Diagram Devices U5401, Q5421 and Q5441 are surface mounted. A pressure pad between board and the radio’s cover provides good thermal contact between the devices and the chassis.PCIC Pin Diode Antenna Switch RF JackAntenna Harmonic Filter PowerSensePA - F i n a lSta gePADriver From VCOControlledStag e VcontrolBias 1Bias 2 To Microprocessor Temperature Sense SPI BUS ASFIC_CMP PA PWR SET To Microprocessor & Bias 3
2-4 UHF (450-520 MHz) Transmitter Power Amplifier (PA) 40W 3.1 First Power Controlled Stage The first stage (U5401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U5401 is controlled by a DC voltage applied to pin 1 from Q5473. The control voltage simultaneously varies the bias of two FET stages within U5401. This biasing point determines the overall gain of U5401 and therefore its output drive level to Q5421, which in turn controls the output power of the PA. Switch S5440 is a pressure pad with a conductive strip which connects two conductive areas on the board when the radios cover is properly screwed to the chassis. When the cover is removed, S5440 opens and cuts the supply voltage to Q5473 thus disabling control voltage to U5401. This prevents transmitter key up while the devices do not have proper thermal contact to the chassis. 3.2 Power Controlled Driver Stage The next stage is an LDMOS device (Q5421) providing a gain of 12dB. This device requires a positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit mode by U5501-24 and fed to the gate of Q5421 via the resistive network R5480, R5408, R5415 and R5416. 3.3 Final Stage The final stage is an LDMOS MRF1570 device Q5441. It provides a gain of 11dB. It integrates two MRF1535 die inside. These two die are being run in parallel. The output of each of the device (die) inside are combined to constitute the total output power. This device also requires a positive gate bias and a quiescent current flow for proper operation. The voltage of the line MOSBIAS_2 and MOSBIAS_3 are set in transmit mode by the ASFIC and fed to the gate of Q5441 via two resistive network R5631, R5634, R5485, R5486 and R5632, R5635, R5481, R5489. These bias voltages are tuned in the factory. If the transistor is replaced, the bias voltage must be tuned using the Global Tuner. Care must be taken not to damage the device by exceeding the maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage input, PASUPVLTG, via L5421, L5437 and L5436, L5438. A matching network consisting of C5440-45, C5466-67, C5476-77, C5487, C5491, C5455-56, C5449-50, C5465, C5468 and striplines transforms the impedance to 50 ohms and feeds the directional coupler. 3.4 Directional Coupler The directional coupler is a microstrip printed circuit, which couples a small amount of the forward power delivered by Q5441. The coupled signal is rectified by D5451. The DC voltage is proportional to the RF output power and feeds the RFIN port of the PCIC (U5501 pin 1). The PCIC controls the gain of stage U5401 as necessary to hold this voltage constant, thus ensuring the forward power out of the radio to be held to a constant value.
UHF (450-520 MHz) Transmitter Power Amplifier (PA) 40W 2-5 3.5 Antenna Switch The antenna switch consists of two PIN diodes, D5471 and D5472. In the receive mode, both diodes are off. Signals applied at the antenna jack J5401 are routed, via the harmonic filter, through network L5472, C5474 and C5475, to the receiver input. In the transmit mode, K9V1 turns on Q5471 which enables current sink Q5472, set to 96 mA by R5512 and VR5471. This completes a DC path from PASUPVLTG, through L5437, D5471, L5472, D5472, L5473, R5496 and the current sink to ground. Both diodes are forward biased into conduction. The transmitter RF from the directional coupler is routed via D5471 to the harmonic filter and antenna jack. D5472 also conducts, shunting RF power and preventing it from reaching the receiver port (RXIN). L5472 is selected to appear as a broadband lambda/4 wave transmission line, making the short circuit presented by D5472 appear as an open circuit at the junction of D5472 and the receiver path. 3.6 Harmonic Filter Components L5491-L5493 and L5472, C5448, C5494, C5496 and C5498 form a Butterworth low- pass filter to attenuate harmonic energy of the transmitter to specifications level. R5491 is used to drain electrostatic charge that might otherwise build up on the antenna. The harmonic filter also prevents high level RF signals above the receiver passband from reaching the receiver circuits, improving spurious response rejection. 3.7 Power Control The transmitter uses the power control IC (PCIC, U5501) to control the power output of the radio. A portion of the forward RF power from the transmitter is sampled by the bi-directional coupler and rectified to provide a dc voltage to the RFIN port of the PCIC (pin 1) that is proportional to the sampled RF power. The ASFIC (U0221) has internal digital to analog converters (DACs) which provide a reference voltage of the control loop to the PCIC via R5483. The reference voltage level is programmable through the SPI line of the PCIC. This reference voltage is proportional to the desired power setting of the transmitter, and is factory programmed at several points across the frequency range of the transmitter to offset frequency response variations of the transmitter’s power detector circuit. The PCIC provides a DC output voltage at pin 4 (INT) which sets the drain current of the first (U5401). This adjusts the transmitter power output to the intended value. Variations in forward transmitter power cause the DC voltage at pin 1 to change, and the PCIC adjusts the control voltage above or below its nominal value to raise or lower output power. Capacitors C5502-4, in conjunction with resistors and integrators within the PCIC, control the transmitter power rise (key-up) and power decay (de-key) characteristic to minimize splatter into adjacent channels. U5502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity of the transmitter driver and final devices, and provides a DC voltage to the PCIC (TEMP, pin 30) proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the transmitter output power will be reduced so as to decrease the transmitter temperature.
2-6UHF (450-520 MHz) Frequency Synthesis 4.0 UHF (450-520 MHz) Frequency Synthesis The synthesizer subsystem shown in Figure 2-3, consists of the reference oscillator (Y5261 or Y5262), the Low Voltage Fractional-N synthesizer (LVFRAC-N, U5201), and the Voltage Controlled Oscillator (VCO). 4.1 Reference Oscillator The reference oscillator (Y5262) contains a temperature compensated crystal oscillator with a frequency of 16.8 MHz. An Analog-to-Digital (A/D) converter internal to U5201 (LVFRAC-N) and controlled by the µP via serial interface (SRL) sets the voltage at the warp output of U5201, pin 25 to set the frequency of the oscillator. The output of the oscillator (Y5262, pin 3) is applied to pin 23 (XTAL1) of U5201 via an RC series combination. In applications where less frequency stability is required, the oscillator inside U5201 is used along with external crystal Y5261, varactor diode D5261, C5261, C5262, and R5262. In this case, Y5262, R5263, C5235 and C5251 are not used. When Y5262 is used, Y5261, D5261, C5261, C5262 and R5262 are not used, and C5263 is increased to 0.1 uF. 4.2 Fractional-N Synthesizer The LVFRAC-N synthesizer IC (U5201) consists of a pre-scaler, programmable loop divider, control divider logic, phase detector, charge pump, A/D converter for low frequency digital modulation, balanced attenuator used to balance the high frequency analog modulation and low frequency digital modulation, 13V positive voltage multiplier, serial interface for control, and a super filter for the regulated 5 volts. A voltage of 5V applied to the super filter input (U5201, pin 30) supplies an output voltage of 4.5 Vdc (VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R5322), and synthesizer charge pump resistor network (R5251, R5252). The synthesizer supply voltage is provided by 5V regulator, U5211. To generate a high voltage to supply the phase detector (charge pump) output stage at pin VCP (U5701-32), a voltage of 13 Vdc is generated by the positive voltage multiplier circuit (D5201, C5202, and C5203). This voltage multiplier is basically a diode capacitor network driven by two signals (1.05MHz) 180 degrees out of phase (U5201, pins 14 and 15).