Motorola Gm328 Gm338 Gm398 Detailed 6804112j18 E Manual

							1-1
Section 1
MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM338 Model Chart
2.0 Technical Specifications
Data is specified for +25°C unless otherwise stated.
GM Series, UHF Band 2, 450-520 MHz
Model Description
AZM25SKF9AA5GM338 450-520 MHz 25-40W
Item Description
XGCN6114_GM338 Control Head Direct Mount
X IMUE6019_ Tanapa WM 450-520 MHz 25-40W
XRAE4155_BNC 470-512 MHz, 1/4 Wave Roof Mount
X RAE4156_ BNC 470-494 MHz, 3.5 Gain Roof Mount
XRAE4157_BNC 494-512 MHz, 5dB Gain Roof Mount
X 6804112J06 GM338 User Guide
x = Indicates one of each is required.
General Specifications
Channel Capacity
GM338
128
Power Supply 13.2Vdc (10.8 - 15.6Vdc)
Dimensions: H x W x D (mm)  Depth excluding knobsGM338
59mm x 179mm x 198mm (25 - 40W)
(add 9mm for Volume Knob)
Weight GM338 1400 g
Sealing:Withstands rain testing per 
MIL STD 810 C/D/E and IP54
Shock and Vibration: Protection provided via impact
resistant housing exceeding MIL STD 
810-C/D/E
Dust, Salt & Fog:Protection provided via environment 
resistant housing exceeding MIL STD 
810 C/D/E  
						

							1-2Technical Specifications
*Availability subject to the laws and regulations of individual countries.Transmitter UHF
*Frequencies - Full BandsplitUHF 450-520 MHz
Channel Spacing12.5/20/25 kHz
Frequency Stability
(-30°C to +60°C, +25° Ref.)±2.0 ppm
Power 25-40W
Modulation Limiting
±2.5 @ 12.5 kHz 
±4.0 @ 20 kHz
±5.0 @ 25 kHz
FM Hum & Noise-40 dB @ 12.5kHz
-45 dB @ 20/25kHz
Conducted/Radiated Emission (ETS)-36 dBm 1 GHz
Adjacent Channel Power-60 dB @ 12.5 kHz
-70 dB @ 25 kHz
Audio Response (300 - 3000 Hz)+1 to -3 dB
Audio Distortion
@1000Hz, 60%
Rated Maximum Deviation
65 dB
Adjacent Channel Selectivity (ETS)
65 dB @ 12.5 kHz 
70 dB @ 20 kHz
75 dB @ 25 kHz
Spurious Rejection (ETS)70 dB @ 12.5 kHz
75 dB @ 20/25 kHz
Rated Audio
3W Internal
7.5W External
13W External
Audio Distortion @ Rated Audio
						

							2-1
Section 2
THEORY OF OPERATION
1.0 Introduction
This Chapter provides a detailed theory of operation for the UHF circuits in the radio. For details of 
the theory of operation and troubleshooting for the associated Controller circuits refer to the 
Controller Section of this manual.
2.0 UHF (450-520 MHz) Receiver
2.1 Receiver Front-End
The UHF receiver, shown in Figure 2-1, is able to cover the UHF range from 450 to 520 MHz. It 
consists of four major blocks: front-end bandpass filters and pre-amplifier, first mixer, high-IF, low-IF 
and receiver back-end . Two varactor-tuned bandpass filters perform antenna signal pre-selection. 
A cross over quad diode mixer converts the signal to the first IF of 44.85 MHz. Low-side first 
injection is used.
Figure 2-1 UHF Receiver Block Diagram
Demodulator
1. Crystal 
Filter Mixer Va r a c t o r  
Tuned Filter RF Amp Va r a c t o r  
Tuned Filter Pin Diode 
Antenna 
Switch
RF Jack
Control Voltage
from PCICFirst LO
from FGU
Recovered Audio
RSSI
Second LO
2. Crystal 
Filter
455kHz Filter
(25kHz)455kHz Filter
(25kHz)
455kHz Filter
(12.5kHz)455kHz Filter
(12.5kHz)SwitchSwitchSwitchSwitch
Limiter
1. IF Amp
2. IF Amp
Filter Bank Selection
from Synthesizer IC
   Harmonic 
   Filter
BWSELECT 
						

							2-2UHF (450-520 MHz) Receiver
The two 2-pole 44.85 MHz crystal filters in the high-IF section and two pairs of 455 kHz ceramic 
filters in the low-IF section provide the required adjacent channel selectivity .The correct pair of 
ceramic filters for 12.5 or 25KHz channel spacing is selected via control line BWSELECT. The 
second IF at 455 kHz is mixed, amplified, and demodulated in the IF IC. The processing of the 
demodulated audio signal is performed by an audio processing IC located in the controller section.
2.2 Front-End Band-Pass Filters & Pre-Amplifier 
The received signal from the radio’s antenna connector is first routed through the harmonic filter and 
antenna switch, which are part of the RF power amplifier circuits, before being applied to the receiver 
pre-selector filter (C5001, C5002, D5001, and related components). The 2-pole pre-selector filter, 
tuned by the varactor diodes D5001 and D5002, pre-select the incoming signal (RXIN) from the 
antenna switch to reduce spurious effects to the stages that follow. The tuning voltage (FECTRL_1), 
ranging from 2 volts to 8 volts, is controlled by pin 20 of PCIC (U5501) in the transmitter section. A 
dual hot carrier diode (D5003) limits any inband signal to 0 dBm to prevent damage to the pre-
amplifier.
The RF pre-amplifier is an SMD device (Q5003) with collector base feedback to stabilize gain, 
impedance, and intermodulation. The collector current of approximately 11-16 mA is drawn from the 
9.3 volt supply via L5003 and R5002. A 3dB pad (R5006,R5007, R5011, and R5008 - R5010) 
stabilizes the output impedance and intermodulation performance. 
A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal. 
Varactor diodes D5004 and D5005 are controlled by the same signal, FECTRL_1, which controls 
the pre-selector filter. A following 1 dB pad (R5013 - R5015) stabilizes the output impedance and 
intermodulation performance.
2.3 First Mixer and High Intermediate Frequency (IF)
The signal from the front-end is converted to the first IF (44.85 MHz) using cross-over, quad diode 
mixer D5051. Its ports are matched for incoming RF signal conversion to the 44.85 MHz IF using low 
side injection via matching transformers T5051 and T5052. The injection signal (RXINJ) coming from 
the RX VCO buffer (Q5332) is filtered by the lowpass filter consisting of L5053, L5054, and C5053 - 
C5055 followed by matching transformer T5052 which has a level of approximately 15dBm.
The mixer IF output signal from transformer T5501, pin 2 is fed to the first two-pole crystal filter 
(FL3101). The filter output in turn is matched to IF amplifier Q3101 which is actively biased using 
collector-base feedback resistors R3101and R3106 to provide a current drain of approximately 5 mA 
drawn from the 5 volt supply. The output impedance of this device is matched to the second two-pole 
crystal filter FL3102. The signal is further amplified by a preamplifier Q3102 before going to pin 1 of 
IFIC (U3101).
A dual, hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at 
RF input levels above -27 dBm. 
						

							Transmitter Power Amplifier (PA) 40W2-3
2.4 Low Intermediate Frequency (IF) and Receiver Back End
The 44.85 MHz first IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the 
IF IC the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator to produce a 
low IF signal of 455 kHz. The second LO frequency is determined by crystal Y3101. The second IF 
signal is amplified and filtered by an external pair of 455 kHz ceramic filters (FL3112 and FL3114) for 
20/25 kHz channel spacing, or FL3111 and FL3113/F3115 for 12.5 kHz channel spacing. These 
pairs are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the 
limiter input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide 
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% 
deviation) from U3103, pin 8 (DISCAUDIO) which is fed to ASFIC_CMP U0221, pin 2 (part of the 
controller circuits). 
A received signal strength indicator (RSSI) signal is available at U3101, pin 5, which has a dynamic 
range of 70 dB. The RSSI signal is interpreted by the µP (U0101, pin 63) and is available at 
accessory connector J0501-15.
3.0 Transmitter Power Amplifier (PA) 40W
The radio’s 40W power amplifier (PA), shown in Figure 2-2, is a four-stage amplifier used to amplify 
the output from the VCOBIC to the radio transmit level. The first stage is an LDMOS predriver 
(U5401) controlled by pin 4 of PCIC (U5501) via Q5473 (CNTLVLTG). This stage is followed by 
another LDMOS stage (Q5421), LDMOS stage Q5431, and a bipolar final stage (Q5441). Device 
Q5401 is surface mounted and Q5421, Q5431, and Q5441 are directly attached to the heat sink.
Figure 2-2 UHF Transmitter Block Diagram PCIC
Pin Diode 
Antenna 
Switch
RF JackAntenna
Harmonic 
Filter
PowerSensePA - F i n a lSta gePADriver From VCOControlledStag e
VcontrolBias 1Bias 2
To Microprocessor
Temperature
Sense SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor 
						

							2-4Transmitter Power Amplifier (PA) 40W
3.1 Power Controlled Stage
The first stage (U5401) amplifies the RF signal from the VCO (TXINJ) and controls the output power 
of the PA. The output power of the transistor U5401 is controlled by a voltage control line feed from 
the PCIC (U5501, pin 4). The control voltage simultaneously varies the bias of two FET stages within 
U5401. This biasing point determines the overall gain of U5401 and therefore its output drive level to 
Q5421, which in turn controls the output power of the PA. 
In receive mode, the voltage control line is at ground level and turns off Q5473, which in turn 
switches off the biasing voltage to U5401.
3.2 Pre-Driver Stage
The next stage is a 13dB gain LDMOS device (Q5421) which requires a positive gate bias and a 
quiescent current flow for proper operation. The voltage of the line PCIC_MOSBIAS_1 is set in 
transmit mode by PCIC, pin 24 and fed to the gate of Q5421 via the resistive network R5407, 
R5408, R5416, and R5415. The bias voltage is factory tuned.
3.3 Driver Stage
This stage is an enhancement-mode N-Channel MOSFET device (Q5431) providing a gain of 10dB. 
This device also requires a positive gate bias and a quiescent current flow for proper operation. The 
voltage of the line Bias_2_UHF_PA_1 is set in transmit mode by the ASFIC and fed to the gate of 
Q5431 via resistive network R5630, R5631, and R5632. This bias voltage is also factory tuned.
If the transistor is replaced, the bias voltage must be tuned using the Customer Programming 
Software (CPS). Care must be taken not to damage the device by exceeding the maximum allowed 
bias voltage. The device’s drain current is drawn directly from the radio’s dc supply voltage input, A+ 
via L5421.
3.4 Final Stage
The final stage uses bipolar device Q5441 whose collector current is also drawn from the radio’s dc 
supply voltage input. To maintain class C operation, the base is dc-grounded by series inductor 
L5441 and bead L5440. A matching network consisting of C5541-C5544 and two striplines 
transform the impedance to 50 ohms and also feed the directional coupler.
3.5 Bi-Directional Coupler
The bi-directional coupler is a microstrip printed circuit, which couples a small amount of the forward 
and reverse power of the RF power from Q5441. The coupled signal is rectified to an output power 
proportional dc voltage by diodes D5451 and D5452 before being sent to the RFIN input of the 
PCIC. The PCIC controls the gain of stage U5401 as necessary to hold this voltage constant. This 
ensures the forward power out of the radio is held to a constant value. 
						

							Transmitter Power Amplifier (PA) 40W2-5
3.6 Antenna Switch
The antenna switch utilizes the existing dc feed (A+) to the last stage device (Q5441). Basic 
operation is to have both PIN diodes (D5471 and D5472) turned on during key-up by forward 
biasing them.   This is achieved by pulling down the voltage at the cathode end of D5472 to around 
11.8V (0.7V drop across each diode). The current through the diodes needs to be set around 80mA 
to fully open the transmit path through resistor R5496. Q5472 is a current source controlled by 
Q5471 and is eventually connected to pin ANO of PCIC. VR5471 ensures the voltage at resistor 
R4511 never exceeds 5.6V.
3.7 Harmonic Filter
Inductors L5491, L5492, and L4493 along with capacitors C5448, C5493, C5494, C5496, and 
C5498 form a low-pass filter to attenuate harmonic energy from the transmitter. Resistor R5491 
drains any electrostatic charges that might otherwise build up on the antenna. The harmonic filter 
also prevents high level RF signals above the receiver passband from reaching the receiver circuits 
to improve spurious response rejection.
3.8 Power Control
The transmitter uses the power control IC (PCIC, U5501) to control the power output of the radio. A 
portion of the forward RF power from the transmitter is sampled by the bi-directional coupler and 
rectified to provide a dc voltage to the RFIN port of the PCIC (pin 1) that is proportional to the 
sampled RF power. 
The PCIC has internal digital-to-analog converters (DACs) which provide a reference voltage to the 
control loop. The reference voltage level is programmable through the SPI line of the PCIC and is 
proportional to the desired power setting of the transmitter. Factory programming at several points 
across the frequency range of the transmitter is used to offset frequency response variations of the 
transmitter’s power detector circuits.
The PCIC provides a dc output voltage at pin 4 (INT) and applied as CNTLVLTG to the power-adjust 
input pin of the first transmitter stage U5401. This adjusts the transmitter power output to the 
intended value. Variations in forward or reflected transmitter power cause the dc voltage at pin 1 to 
change, and the PCIC adjusts the control voltage above or below its nominal value to raise or lower 
output power.
Capacitor C5502-4, in conjunction with resistors and integrators within the PCIC, control the 
transmitter power rise (key-up) and power decay (de-key) characteristic to minimize splatter into 
adjacent channels.
U5502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity 
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29) 
proportional to temperature. If the dc voltage produced exceeds the set threshold in the PCIC, the 
transmitter output power is reduced to decrease the transmitter temperature. 
						

							2-6Frequency Synthesis
4.0 Frequency Synthesis
The synthesizer, shown in Figure 2-3, consists of a reference oscillator (Y5261 or Y5262), low 
voltage LVFRAC-N synthesizer (U5201), and a voltage controlled oscillator (VCO).
4.1 Reference Oscillator
The reference oscillator (Y5262) contains a temperature compensated crystal oscillator with a 
frequency of 16.8 MHz. An analog-to-digital (A/D) converter internal to U5201 (LVFRAC-N) and 
controlled by the µP via serial interface (SRL) sets the voltage at the warp output of U5201, pin 25 to 
set the frequency of the oscillator. The output of the oscillator (Y5262, pin 3) is applied to pin 23 
(XTAL1) of U5201 via an RC series combination.
In applications where less frequency stability is required, the oscillator inside U5201 is used along 
with external crystal Y5261, varactor diode D5261, C5261, C5262, and R5262. In this case, Y5262, 
R5263, C5235 and C5251 are not used. When Y5262 is used, Y5261, D5261, C5261, C5262 and 
R5262 are not used, and C5263 is increased to 0.1 uF.
4.2 Fractional-N Synthesizer
The LVFRAC-N synthesizer IC (U5201) consists of a pre-scaler, programmable loop divider, control 
divider logic, phase detector, charge pump, A/D converter for low frequency digital modulation, 
balanced attenuator used to balance the high frequency analog modulation and low frequency digital 
modulation, 13V positive voltage multiplier, serial interface for control, and a super filter for the 
regulated 5 volts.
A voltage of 5V applied to the super filter input (U5201, pin 30) supplies an output voltage of 4.5 Vdc 
(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R5322), and synthesizer 
charge pump resistor network (R5251, R5252). The synthesizer supply voltage is provided by 5V 
regulator, U5211.
To generate a high voltage to supply the phase detector (charge pump) output stage at pin VCP 
(U5701-32), a voltage of 13 Vdc is generated by the positive voltage multiplier circuit (D5201, 
C5202, and C5203). This voltage multiplier is basically a diode capacitor network driven by two 
signals (1.05MHz) 180 degrees out of phase (U5201, pins 14 and 15). 
						

							Frequency Synthesis2-7
Figure 2-3 UHF Synthesizer Block Diagram
Output LOCK (U5201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U5201 provides the 16.8 MHz reference frequency at 
pin 19.
The serial interface (SRL) is connected to the µP via data line DATA (U5201-7), clock line CLK 
(U5201-8), and chip enable line CSX (U5201-9).
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U4211 PIN 1)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
        1540FILTERED 5VSTEERING LOCK (U0101 PIN 56)
PRESCALER INFREF (U0221 PIN 34)
39 BIAS2
41
 48 5, 20, 34, 36
+5V (U4211 PIN 1)
AUX1 VDD, DC5VMODOUT
U5201 
LOW VOLTAGEFRACTIONAL-N
SYNTHESIZER
AUX21 (NU)
BWSELECTVCO Bias
TRB
To IF
SectionTX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
2-POLE
LOOP
FILTER 
						

							2-8Frequency Synthesis
4.3 Voltage Controlled Oscillator (VCO)
The voltage controlled oscillator (VCO), shown in Figure 2-4, consists of a VCO buffer IC (VCOBIC, 
U5301), TX and RX tank circuits, external RX buffer stages, and modulation circuits.
The VCOBIC together with Fractional-N synthesizer (U5201) generates the required frequencies in 
both transmit and receive modes. The TRB line (U5301, pin 19) determines which tank circuits and 
internal buffers are to be enabled. A high level on TRB enables TX tank and TX output (pin 10), and 
a low enables RX tank and RX output (pin 8). A sample of the signal from the enabled output is 
routed from U5301, pin 12 (PRESC_OUT), via a low pass filter of U5201, pin 32 (PREIN).
A steering line voltage (VCTRL) between 3.0V and 10.0V at varactor diode CR5311 tunes the full 
TX frequency range (TXINJ) from 450 MHz to 520 MHz, and at varactor diodes CR5301, CR5302, 
and CR5303 tunes the full RX frequency range (RXINJ) from 405 MHz to 475 MHz. The tank circuits 
uses the Hartley configuration for wider bandwidth. For the RX tank circuit, external transistor 
Q5301 is used in conjunction with the internal transistor for better side-band noise.
Figure 2-4 UHF VCO Block Diagram
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U5201 Pin28)
VCC Buffers
TX RF Injection U5201 Pin 32 AUX3 (U5201 Pin2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U5301
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U5201 Pin28)Rx-SW
Tx-SW
Vcc-Logic
(U5201 Pin28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION
Q4301
Q4332