Motorola Gm328 Gm338 Gm398 Detailed 6804112j18 E Manual
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1-1 Section 1 MODEL CHART AND TECHNICAL SPECIFICATIONS 1.0 GM328/GM338/GM398 Model Chart GM Series, UHF Band 1, 403-470 MHz Model Description AZM25RHC9AA1GM328 403-470 MHz 1-25W AZM25RHF9AA5 GM338 403-470 MHz 1-25W AZM25RHN9AA8GM398 403-470 MHz 1-25W Item Description X GCN6112_ GM328 Control Head Direct Mount XGCN6114_GM338 Control Head Direct Mount X GCN6115_ GM398 Control Head Direct Mount XXIMUE6021_Tanapa WM 403-470 MHz 1-25W X IMUE6039_ Tanapa WM 403-470 MHz 1-25W XXXRAE4151_BNC 403-430 MHz, 1/4 Wave Roof Mount XXXRAE4158_ BNC 406-420 MHz, 3.5dB Gain Roof Mount XXXRAE4152_BNC 450-470 MHz, 1/4 Wave Roof Mount XXXRAE4153_ BNC 450-470 MHz, 3.5dB Gain Roof Mount XXXRAE4154_BNC 450-470 MHz, 5dB Gain Roof Mount X 6804113J74 GM328 User Guide X6804112J06GM338 User Guide X 6804112J07 GM398 User Guide x = Indicates one of each is required.
1-2Technical Specifications 2.0 Technical Specifications Data is specified for +25°C unless otherwise stated. General Specifications Channel Capacity GM328 GM338 GM398 4 128 160 Power Supply 13.2Vdc (10.8 - 15.6Vdc) Dimensions: H x W x D (mm) Depth excluding knobsGM328 56mm x 176mm x 177mm (add 8mm for Volume Knob) Dimensions: H x W x D (mm) Depth excluding knobsGM338 59mm x 179mm x 186mm (1 - 25W) 59mm x 179mm x 198mm (25 - 45W) (add 9mm for Volume Knob) Dimensions: H x W x D (mm) Depth excluding knobsGM398 72mm x 185mm x 188mm (add 8mm for Volume Knob) Weight: GM328/GM338 1400 g Weight: GM398 1500 g Sealing: Withstands rain testing per MIL STD 810 C/D/E and IP54 Shock and Vibration: Protection provided via impact resistant housing exceeding MIL STD 810-C/D/E Dust, Salt & Fog: Protection provided via environment resistant housing exceeding MIL STD 810 C/D/E
Technical Specifications1-3 Transmitter UHF *Frequencies - Full BandsplitUHF 403-470 MHz Channel Spacing12.5/20/25 kHz Frequency Stability (-30°C to +60°C, +25° Ref.)±2.0 ppm Power 1-25W Modulation Limiting ±2.5 @ 12.5 kHz ±4.0 @ 20 kHz ±5.0 @ 25 kHz FM Hum & Noise-40 dB @ 12.5kHz -45 dB @ 20/25kHz Conducted/Radiated Emission (ETS)-36 dBm 1 GHz Adjacent Channel Power-60 dB @ 12.5 kHz -70 dB @ 25 kHz Audio Response (300 - 3000 Hz)+1 to -3 dB Audio Distortion @1000Hz, 60% Rated Maximum Deviation65 dB Base Mode: >70dB (1-25W model only) Adjacent Channel Selectivity (ETS) 65 dB @ 12.5 kHz 70 dB @ 20 kHz 75 dB @ 25 kHz Spurious Rejection (ETS)70 dB @ 12.5 kHz 75 dB @ 20/25 kHz Rated Audio3W Internal 13W External Audio Distortion @ Rated Audio
1-4Technical Specifications *Availability subject to the laws and regulations of individual countries. Audio Response (300 - 3000Hz @ 20/25kHz) (300 - 2550Hz @12.5kHz)+1 to -3 dB Conducted Spurious Emission (ETS)-57 dBm 1 GHz Receiver UHF
2-1 Section 2 THEORY OF OPERATION 1.0 Introduction This Chapter provides a detailed theory of operation for the UHF circuits in the radio. For details of the theory of operation and troubleshooting for the the associated Controller circuits refer to the Controller Section of this manual. 2.0 UHF (403-470 MHz) Receiver 2.1 Receiver Front-End The receiver is able to cover the UHF range from 403 to 470 MHz. It consists of four major blocks: front-end bandpass filters and pre-amplifier, first mixer, high-IF, low-IF and receiver back-end . Two varactor-tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode mixer converts the signal to the first IF of 44.85 MHz. Low-side first injection is used. Figure 2-1 UHF Receiver Block Diagram Demodulator 1. Crystal Filter Mixer Va r a c t o r Tuned Filter RF Amp Va r a c t o r Tuned Filter Pin Diode Antenna Switch RF Jack Antenna Control Voltage from PCICFirst LO from FGU Recovered Audio RSSI Second LO 2. Crystal Filter 455kHz Filter (25kHz)455kHz Filter (25kHz) 455kHz Filter (12.5kHz)455kHz Filter (12.5kHz)SwitchSwitchSwitchSwitch Limiter 1. IF Amp 2. IF Amp Filter Bank Selection from Synthesizer IC Harmonic Filter BWSELECT
2-2UHF (403-470 MHz) Receiver There are two 2-pole 44.85 MHz crystal filters in the high-IF section and 2 pairs of 455 kHz ceramic filters in the low-IF section to provide the required adjacent channel selectivity .The correct pair of ceramic filters for 12.5 or 25KHz channel spacing is selected via control line BWSELECT. The second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The processing of the demodulated audio signal is performed by an audio processing IC located in the controller section. 2.2 Front-End Band-Pass Filters & Pre-Amplifier The received signal from the radio’s antenna connector is first routed through the harmonic filter and antenna switch, which are part of the RF power amplifier circuitry, before being applied to the receiver pre-selector filter (C4001, C4002, D4001 and associated components). The 2-pole pre- selector filter tuned by the varactor diodes D4001 and D4002 pre-selects the incoming signal (RXIN) from the antenna switch to reduce spurious effects to following stages. The tuning voltage (FECTRL_1) ranging from 2 volts to 8 volts is controlled by pin 20 of PCIC (U4501) in the Transmitter section. A dual hot carrier diode (D4003) limits any inband signal to 0 dBm to prevent damage to the pre-amplifier. The RF pre-amplifier is an SMD device (Q4003) with collector base feedback to stabilize gain, impedance, and intermodulation. The collector current of approximately 11-16 mA is drawn from the voltage 9V3 via L4003 and R4002. A switchable 3dB pad (R4066,R4007,R4063, R4064 and R4070), controlled via line FECTRL_2 and Q4004 stabilizes the output impedance and intermodulation performance. A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal. The varactor diodes D4004 and D4005 are controlled by the same signal FECTRL_1, which controls the pre-selector filter. A following 1 dB pad (R4013 - R4015) stabilizes the output impedance and intermodulation performance. 2.3 First Mixer and High Intermediate Frequency (IF) The signal coming from the front-end is converted to the first IF (44.85 MHz) using a cross over quad diode mixer (D4051). Its ports are matched for incoming RF signal conversion to the 44.85 MHz IF using low side injection via matching transformers T4051 and T4052. The injection signal (RXINJ) coming from the RX VCO buffer (Q4332) is filtered by the lowpass filter consisting of (L4053, L4054, C4053 - C4055) followed by a matching transformer T4052 and has a level of approximately 15dBm. The mixer IF output signal (IF) from transformer T4501pin 2 is fed to the first two pole crystal filter FL3101. The filter output in turn is matched to the following IF amplifier. The IF amplifier Q3101 is actively biased by a collector base feedback (R3101, R3106) to a current drain of approximately 5 mA drawn from the voltage 5V. Its output impedance is matched to the second two pole crystal filter FL3102. The signal is further amplified by a preamplifier (Q3102) before going into pin 1 of IFIC (U3101). A dual hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at RF input levels above -27 dBm.
UHF (403-470 MHz) Transmitter Power Amplifier (PA) 25 W 2-3 2.4 Low Intermediate Frequency (IF) and Receiver Back End The 44.85 high IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the IF IC the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO) to produce the low IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The low IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters FL3112, FL3114 for 20/25 kHz channel spacing or FL3111,FL3113/F3115 for 12.5 kHz channel spacing. These pairs are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter input pin of the IF IC (pin 14). The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% deviation) from U3103 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (part of the Controller circuitry). A Received Signal Strength Indicator (RSSI) signal is available at U3101 pin 5, having a dynamic range of 70 dB. The RSSI signal is interpreted by the microprocessor (U0101 pin 63) and in addition is available at accessory connector J0501-15. 3.0 UHF (403-470 MHz) Transmitter Power Amplifier (PA) 25 W The radio’s 25W PA is a three stage amplifier used to amplify the output from the VCOBIC to the radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U4401) is adjustable, controlled by pin 4 of PCIC (U4501) via U4402-1. It is followed by an LDMOS stage (Q4421) and LDMOS final stage (Q4441). Figure 2-2 UHF Transmitter Block Diagram Devices U4401, Q4421 and Q4441 are surface mounted. A pressure pad between board and the radios cover provides good thermal contact between the devices and the chassis.PCIC Pin Diode Antenna Switch RF JackAntenna Harmonic Filter PowerSensePA - F i n a lStag e From VCOControlledStag e VcontrolBias 1Bias 2 To Microprocessor Temperature Sense SPI BUS ASFIC_CMP PA PWR SET To Microprocessor PADriver
2-4 UHF (403-470 MHz) Transmitter Power Amplifier (PA) 25 W 3.1 First Power Controlled Stage The first stage (U4401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U4401 is controlled by a DC voltage applied to pin 1 from the op-amp U4402-1, pin 1. The control voltage simultaneously varies the bias of two FET stages within U4401. This biasing point determines the overall gain of U4401 and therefore its output drive level to Q4421, which in turn controls the output power of the PA. Op-amp U4402-1 monitors the drain current of U4401 via resistor R4444 and adjusts the bias voltage of U4401 so that the current remains constant. The PCIC (U4501) provides a DC output voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A raising power output causes the DC voltage from the PCIC to fall, and U4402-1 adjusts the bias voltage for a lower drain current to lower the gain of the stage. In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q4442, which in turn switches off the biasing voltage to U4401. Switch S5440 is a pressure pad with a conductive strip which connects two conductive areas on the board when the radios cover is properly screwed to the chassis. When the cover is removed, S5440 opens and the resulting high voltage level at the inverting inputs of the current control op-amps U4402-1 & 2 switches off the biasing of U4401 and Q4421. This prevents transmitter key up while the devices do not have proper thermal contact to the chassis. 3.2 Power Controlled Driver Stage The next stage is an LDMOS device (Q4421) providing a gain of 12dB. This device requires a positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit mode by the drain current control op-amp U4402-2, and fed to the gate of Q4421 via the resistive network R4429, R4418, R4415 and R4416. Op-amp U4402-2 monitors the drain current of U4421 via resistors R4424-27 and adjusts the bias voltage of Q4421 so that the current remains constant. The PCIC (U4501) provides a DC output voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A raising power output causes the DC voltage from the PCIC to fall, and U4402-2 adjusts the bias voltage for a lower drain current to lower the gain of the stage. In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q4422, which in turn switches off the biasing voltage to Q4421. 3.3 Final Stage The final stage is an LDMOS device (Q4441) providing a gain of 12dB. This device also requires a positive gate bias and a quiescent current flow for proper operation. The voltage of the line MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the gate of Q4441 via the resistive network R4404, R4406, and R4431-2. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be tuned using the Global Tuner. Care must be taken not to damage the device by exceeding the maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage input, PASUPVLTG, via L4436 and L4437. A matching network consisting of C4441-49 and striplines transforms the impedance to 50 ohms and feeds the directional coupler.
UHF (403-470 MHz) Transmitter Power Amplifier (PA) 25 W 2-5 3.4 Directional Coupler The directional coupler is a microstrip printed circuit, which couples a small amount of the forward power delivered by Q4441. The coupled signal is rectified by D4451. The DC voltage is proportional to the RF output power and feeds the RFIN port of the PCIC (U4501 pin 1). The PCIC controls the gain of stages U4401 and Q4421 as necessary to hold this voltage constant, thus ensuring the forward power out of the radio to be held to a constant value. 3.5 Antenna Switch The antenna switch consists of two PIN diodes, D4471 and D4472. In the receive mode, both diodes are off. Signals applied at the antenna jack J4401 are routed, via the harmonic filter, through network L4472, C4474 and C4475, to the receiver input. In the transmit mode, K9V1 turns on Q4471 which enables current sink Q4472, set to 96 mA by R4473 and VR4471. This completes a DC path from PASUPVLTG, through L4437, D4471, L4472, D4472, L4471, R4474 and the current sink, to ground. Both diodes are forward biased into conduction. The transmitter RF from the directional coupler is routed via D4471 to the harmonic filter and antenna jack. D4472 also conducts, shunting RF power and preventing it from reaching the receiver port (RXIN). L4472 is selected to appear as a broadband lambda/4 wave transmission line, making the short circuit presented by D4472 appear as an open circuit at the junction of D4472 and the receiver path. 3.6 Harmonic Filter Components L4491-L4493 and L4472, C4491, C4496-98 form a Butterworth low-pass filter to attenuate harmonic energy of the transmitter to specifications level. R4491 is used to drain electrostatic charge that might otherwise build up on the antenna. The harmonic filter also prevents high level RF signals above the receiver passband from reaching the receiver circuits, improving spurious response rejection. 3.7 Power Control The transmitter uses the Power Control IC (PCIC, U4501) to control the power output of the radio. A portion of the forward RF power from the transmitter is sampled by the directional coupler and rectified, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is proportional to the sampled RF power. The ASFIC (U0221) has internal digital to analog converters (DACs) which provide a reference voltage of the control loop to the PCIC via R4505. The reference voltage level is programmable through the SPI line of the PCIC. This reference voltage is proportional to the desired power setting of the transmitter, and is factory programmed at several points across the frequency range of the transmitter to offset frequency response variations of the transmitter’s power detector circuit. The PCIC provides a DC output voltage at pin 4 (INT) which sets the drain current of the first (U4401) and second (Q4421) transmitter stage via current control op-amps U3402-1 and U3402-2. This adjusts the transmitter power output to the intended value. Variations in forward transmitter power cause the DC voltage at pin 1 to change, and the PCIC adjusts the control voltage above or below its nominal value to raise or lower output power. Capacitors C4502-4, in conjunction with resistors and integrators within the PCIC, control the transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into adjacent channels.
2-6UHF (403-470 MHz) Frequency Synthesis U4502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity of the transmitter driver and final devices, and provides a DC voltage to the PCIC (TEMP, pin 30) proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the transmitter output power will be reduced so as to reduce the transmitter temperature. 4.0 UHF (403-470 MHz) Frequency Synthesis The synthesizer subsystem consists of the reference oscillator (Y4261 or Y4262), the Low Voltage Fractional-N synthesizer (LVFRAC-N, U4201), and the Voltage Controlled Oscillator VCO. 4.1 Reference Oscillator The reference oscillator (Y4262) contains a temperature compensated crystal oscillator with a frequency of 16.8 MHz. An Analogue to Digital (A/D) converter internal to U4201 (LVFRAC-N) and controlled by the microprocessor via serial interface (SRL) sets the voltage at the warp output of U4201 pin 25 to set the frequency of the oscillator. The output of the oscillator (pin 3 of Y4262) is applied to pin 23 (XTAL1) of U4201 via a RC series combination. In applications where less frequency stability is required the oscillator inside U4201 is used along with an external crystal Y4261, varactor diode D4261, C4261, C4262 and R4262. In this case, Y4262, R4263, C4235 and C4251 are not used. When Y4262 is used, Y4261, D4261, C4261, C4262 and R4262 are not used, and C4263 is increased to 0.1 uF.