Motorola Gm328 Gm338 Gm398 Detailed 6804112j18 E Manual

							UHF (403-470 MHz) Transmitter Power Amplifier (PA) 40 W 2-3
2.4 Low Intermediate Frequency (IF) and Receiver Back End
The 44.85 high IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the IF 
IC the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO) to 
produce the low IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The 
low IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters FL3112, FL3114 
for 20/25 kHz channel spacing or FL3111,FL3113/F3115 for 12.5 kHz channel spacing. These pairs 
are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter 
input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide 
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% 
deviation) from U3103 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (part of 
the Controller circuitry). 
A Received Signal Strength Indicator (RSSI) signal is available at U3101 pin 5, having a dynamic 
range of 70 dB. The RSSI signal is interpreted by the microprocessor (U0101 pin 63) and in addition 
is available at accessory connector J0501-15.
3.0 UHF (403-470 MHz) Transmitter Power Amplifier (PA) 40 W
The radio’s 40W PA is a three stage amplifier used to amplify the output from the VCOBIC to the 
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U4401) is 
adjustable, controlled by pin 4 of PCIC (U4501).  It is followed by an LDMOS  stage (Q4421) and 
LDMOS final stage (Q4441).
Figure 2-2 UHF Transmitter Block Diagram 
Devices U4401, Q4421 and Q4441 are surface mounted. A pressure pad between board and the 
radios cover provides good thermal contact between the devices and the chassis.PCIC
Pin Diode 
Antenna 
Switch
RF JackAntenna
Harmonic 
Filter
PowerSensePA - F i n a lStag e From VCOControlledStag e
VcontrolBias 1Bias 2 & Bias 3
To Microprocessor
Temperature
Sense SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
PADriver 
						

							2-4 UHF (403-470 MHz) Transmitter Power Amplifier (PA) 40 W
3.1 First Power Controlled Stage
The first stage (U4401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier 
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U4401 is 
controlled by a DC voltage applied to pin 1 from Q4473. The control voltage simultaneously varies 
the bias of two FET stages within U4401. This biasing point determines the overall gain of U4401 
and therefore its output drive level to Q4421, which in turn controls the output power of the PA.
Switch S4440 is a pressure pad with a conductive strip which connects two conductive areas on the 
board when the radios cover is properly screwed to the chassis. When the cover is removed, S4440 
opens and cuts the supply voltage to Q4473 thus disabling control voltage to U4401. This prevents 
transmitter key up while the devices do not have proper thermal contact to the chassis.
3.2 Power Controlled Driver Stage
The next stage is an LDMOS device (Q4421) providing a gain of 12dB. This device requires a 
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit 
mode by U4501-24 and fed to the gate of Q4421 via the resistive network R4480, R4408, R4415 
and R4416.
3.3 Final Stage
The final stage is an LDMOS MRF 1570 device Q4441. It provides a gain of 11dB. It integrates two 
MRF1535 die inside. These two die are being run in parallel. The output of each of the device (die) 
inside are combined to constitute the total output power. This device also requires a positive gate 
bias and a quiescent current flow for proper operation. The voltage of the line MOSBIAS_2 and 
MOSBIAS_3 are set in transmit mode by the ASFIC and fed to the gate of Q4441 via two resistive 
network R4631, R4634, R4485, R4486 and R4632, R4635, R4481, R4489. These bias voltages are 
tuned in the factory. If the transistor is replaced, the bias voltage must be tuned using the Global 
Tuner.  Care must be taken not to damage the device by exceeding the maximum allowed bias 
voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage input, 
PASUPVLTG, via L4421, L4437 and L4436, L4438.
A matching network consisting of C4440-45, C4466-67, C4476-77, C4487, C4491, C4489, C4490, 
C4455-56, C4449-50 and striplines transforms the impedance to 50 ohms and feeds the directional 
coupler. 
						

							UHF (403-470 MHz) Transmitter Power Amplifier (PA) 40 W 2-5
3.4 Directional Coupler
The directional coupler is a microstrip printed circuit, which couples a small amount of the forward 
power delivered by Q4441. The coupled signal is rectified by D4451. The DC voltage is proportional 
to the RF output power and feeds the RFIN port of the PCIC (U4501 pin 1). The PCIC controls the 
gain of stage U4401 as necessary to hold this voltage constant, thus ensuring the forward power out 
of the radio to be held to a constant value.
3.5 Antenna Switch
The antenna switch consists of two PIN diodes, D4471 and D4472. In the receive mode, both diodes 
are off. Signals applied at the antenna jack J4401 are routed, via the harmonic filter, through 
network L4472, C4474 and C4475, to the receiver input. In the transmit mode, K9V1 turns on 
Q4471 which enables current sink Q4472, set to 96 mA by R4512 and VR4471. This completes a 
DC path from PASUPVLTG, through L4437, D4471, L4472, D4472, L4473, R4496 and the current 
sink, to ground. Both diodes are forward biased into conduction. The transmitter RF from the 
directional coupler is routed via D4471 to the harmonic filter and antenna jack. D4472 also 
conducts, shunting RF power and preventing it from reaching the receiver port (RXIN). L4472 is 
selected to appear as a broadband lambda/4 wave transmission line, making the short circuit 
presented by D4472 appear as an open circuit at the junction of D4472 and the receiver path.
3.6 Harmonic Filter
Components L4491-L4493 and L4472, C4448, C4494, C4496 and C4498 form a Butterworth low-
pass filter to attenuate harmonic energy of the transmitter to specifications level.  R4491 is used to 
drain electrostatic charge that might otherwise build up on the antenna. The harmonic filter also 
prevents high level RF signals above the receiver passband from reaching the receiver circuits, 
improving spurious response rejection.
3.7 Power Control
The transmitter uses the Power Control IC (PCIC, U4501) to control the power output of the radio. A 
portion of the forward RF power from the transmitter is sampled by the directional coupler and 
rectified, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is proportional to the 
sampled RF power. 
The ASFIC (U0221) has internal digital to analog converters (DACs) which provide a reference 
voltage of the control loop to the PCIC via R4483. The reference voltage level is programmable 
through the SPI line of the PCIC. This reference voltage is proportional to the desired power setting 
of the transmitter, and is factory programmed at several points across the frequency range of the 
transmitter to offset frequency response variations of the transmitter’s power detector circuit.
The PCIC provides a DC output voltage at pin 4 (INT) which sets the drain current of the first 
(U4401). This adjusts the transmitter power output to the intended value. Variations in forward 
transmitter power cause the DC voltage at pin 1 to change, and the PCIC adjusts the control voltage 
above or below its nominal value to raise or lower output power.
Capacitors C4502-4, in conjunction with resistors and integrators within the PCIC, control the 
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into 
adjacent channels. 
						

							2-6UHF (403-470 MHz) Frequency Synthesis
U4502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity 
of the transmitter driver and final devices, and provides a DC voltage to the PCIC (TEMP, pin 30) 
proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the 
transmitter output power will be reduced so as to reduce the transmitter temperature.
4.0 UHF (403-470 MHz) Frequency Synthesis
The synthesizer subsystem consists of the reference oscillator (Y4261 or Y4262), the Low Voltage 
Fractional-N synthesizer (LVFRAC-N, U4201), and the Voltage Controlled Oscillator VCO.
4.1 Reference Oscillator
The reference oscillator (Y4262) contains a temperature compensated crystal oscillator with a 
frequency of 16.8 MHz. An Analogue to Digital (A/D) converter internal to U4201 (LVFRAC-N) and 
controlled by the microprocessor via serial interface (SRL) sets the voltage at the warp output of 
U4201 pin 25 to set the frequency of the oscillator. The output of the oscillator (pin 3 of Y4262) is 
applied to pin 23 (XTAL1) of U4201 via a RC series combination.
In applications where less frequency stability is required the oscillator inside U4201 is used along 
with an external crystal Y4261, varactor diode D4261, C4261, C4262 and R4262. In this case, 
Y4262, R4263, C4235 and C4251 are not used. When Y4262 is used, Y4261, D4261, C4261, 
C4262 and R4262 are not used, and C4263 is increased to 0.1 uF. 
						

							UHF (403-470 MHz) Frequency Synthesis2-7
4.2 Fractional-N Synthesizer
The LVFRAC-N synthesizer IC (U4201) consists of a pre-scaler, a programmable loop divider, 
control divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital 
modulation, a balance attenuator to balance the high frequency analogue modulation and low 
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and 
finally a super filter for the regulated 5 volts.
Figure 2-3 UHF Synthesizer Block Diagram
A voltage of 5V applied to the super filter input (U4201 pin 30) supplies an output voltage of 4.5 
VDC(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R4322) and the 
synthesizer charge pump resistor network (R4251, R4252). The synthesizer supply voltage is 
provided by the 5V regulator U4211.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at 
pin 47 VCP (U4201-47), a voltage of 13 VDC is being generated by the positive voltage multiplier 
circuitry (D4201, C4202, C4203). This voltage multiplier is basically a diode capacitor network driven 
by two (1.05MHz) 180 degrees out of phase signals (U4201-14 and -15).
Output LOCK (U4201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U4201 provides the 16.8 MHz reference frequency at 
pin 19.
The serial interface (SRL) is connected to the microprocessor via the data line DATA (U4201-7), 
clock line CLK (U4201-8), and chip enable line CSX (U4201-9).
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U4211 PIN 1)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
        1540FILTERED 5VSTEERING LOCK (U0101 PIN 56)
PRESCALER INFREF (U0221 PIN 34)
39 BIAS2
41
 48 5, 20, 34, 36
+5V (U4211 PIN 1)
AUX1 VDD, DC5VMODOUT
U4201 
LOW VOLTAGEFRACTIONAL-N
SYNTHESIZER
AUX21 (NU)
BWSELECTVCO Bias
TRB
To IF
SectionTX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
2-POLE
LOOP
FILTER 
						

							2-8UHF (403-470 MHz) Frequency Synthesis
4.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U4301), the TX 
and RX tank circuits, the external RX buffer stages, and the modulation circuitry.
Figure 2-4 UHF VCO Block Diagram
The VCOBIC together with Fractional-N synthesizer (U4201) generates the required frequencies in 
both  transmit and receive modes. The TRB line (U4301 pin 19) determines which tank circuits and 
internal buffers are to be enabled. A high level on TRB enables TX tank and TX output (pin 10), and  
a low enables RX tank and RX output (pin 8). A sample of the signal from the enabled output is 
routed from U4301 pin 12 (PRESC_OUT), via a low pass filter, to pin 32 of U4201 (PREIN).
A steering line voltage (VCTRL) between 3.0V and 10.0V at varactor diode CR4311 will tune the full 
TX frequency range (TXINJ) from 403 MHz to 470 MHz, and at varactor diodes CR4301, CR4302 
and CR4303 will tune the full RX frequency range (RXINJ) from 358 MHz to 425 MHz. The tank 
circuits uses the Hartley configuration for wider bandwidth. For the RX tank circuit, an external 
transistor Q4301 is used in conjunction with the internal transistor for better side-band noise.
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U4201 Pin28)
VCC Buffers
TX RF Injection U4201 Pin 32 AUX3 (U4201 Pin 2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U4301
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U4201 Pin 28)Rx-SW
Tx-SW
Vcc-Logic
(U4201 Pin 28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION
Q4301
Q4332 
						

							UHF (403-470 MHz) Frequency Synthesis2-9
The external RX buffers (Q4332) are enabled by a high at U4201 pin 3 (AUX4) via transistor switch 
Q4333.  In TX mode the modulation signal (VCOMOD) from the LVFRAC-N synthesizer IC (U4201 
pin41) is applied modulation circuitry CR4321, R4321, R4322 and C4324, which modulates the TX 
VCO frequency via coupling capacitor C4321.  Varactor CR4321 is biased for linearity from VSF.
4.4 Synthesizer Operation
The complete synthesizer subsystem comprises mainly of low voltage FRAC-N (LVFRACN) IC, 
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop 
filter circuitry and DC supply. The output signal PRESC_OUT of the VCOBIC (U4301 pin 12) is fed 
to pin 32 of U4201 (PREIN) via a low pass filter (C4229, L4225) which attenuates harmonics and 
provides the correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U4201) is basically a dual modulus pre-scaler with selectable 
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn 
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output 
of the loop divider is connected to the phase detector, which compares the loop divider´s output 
signal with the reference signal.The reference signal is generated by dividing down the signal of the 
reference oscillator (Y4261 or Y4262).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump. 
The charge pump outputs a current at pin 43 of U4201 (IOUT). The loop filter (which consists of 
R4221-R4223, C4221-C4225,L4221) transforms this current into a voltage that is applied to the 
varactor diodes CR4311 for transmit, CR4301, CR4302 & CR4303 for receive and alters the output 
frequency of the VCO .The current can be set to a value fixed in the LVFRAC-N IC or to a value 
determined by the currents flowing into BIAS 1 (U4201-40) or BIAS 2 (U4201-39). The currents are 
set by the value of R4251 or R4252 respectively. The selection of the three different bias sources is 
done by software programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the 
magnitude of the loop current is increased by enabling the IADAPT  (U4201-45) for a certain 
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high 
transient of the CSX line. When the synthesizer is within the lock range the current is determined 
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled 
synthesizer loop is indicated by a high level of signal LOCK (U4201-4). 
The LOCK (U4201-4) signal is routed to one of the µP´s ADCs input U101-56. From the voltage the 
µP determines whether LOCK  is active. In order to modulate the PLL the two spot modulation 
method is utilized. Via pin 10 (MODIN) on U4201 the audio signal is applied to both the A/D 
converter (low freq path) as well as the balance attenuator (high freq path). The A/D converter 
converts the low frequency analogue modulating signal into a digital code that is applied to the loop 
divider, thereby causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s 
deviation sensitivity to high frequency modulating signals. The output of the balance attenuator is 
present at the MODOUT port (U4201-41) and connected to the VCO modulation diode CR4321 via 
R4321, C4325. 
						

							2-10UHF (403-470 MHz) Frequency Synthesis
THIS PAGE INTENTIONALLY LEFT BLANK 
						

							3-1
Section 3
TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)
Bad SINAD
Bad 20dB Quieting
No Recovered AudioSTART
Audio at 
pin 8 of 
U3101 ?Check Controller
(in the case of no audio)
OR ELSE go to “B” Ye s
No
Spray or inject 44.85MHz 
into XTAL Filter FL3101
Audio heard ?BYe s
No
Check 2nd LO 
(44.395MHz) at C3135 
LO present ?BYe s
 Check voltages on 
U3101Biasing OK ?
No
No
A
Ye s
Check Q3102  bias 
for faults
Replace Q3102
Go to B
Ye s
No
Check circuitry 
around U3101.
Replace 
U3101 if defect
Check circuitry around Y3101. 
Replace Y3101 if defectVoltages
 OK? 
						

							3-2Troubleshooting Flow Chart for Receiver
1.1Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
IF Signal at 
C3101?
No
RF 
Signal at 
T4051?
RF
Signal at 
C4015?
No
No
RF
Signal at 
C4025?
No or 
Check harmonic filter
L4491-L4493, C4492, J4401
and ant. switch
D4471, D4472, L4472.
Check filter between 
C4025 & C4009. 
Check tuning voltage 
at R4060.
Inject RF into J4401
Is
tuning voltage
OK?
No
Ye s
Check RF amp (Q4003) 
Stage.
Check filter between 
C4015 & T4051.
Ye s
Check T4051, T4052, 
D4051, R4052, L4008.
Ye s
1st LO level 
OK?
Locked?Ye s
Check FGU
Ye s
Trace IF signal 
from C3101 to 
Q3101. Check for 
bad XTAL filter.
No
Ye sIF
signal at Q3102 
collector?
Before replacing 
U3101, check 
U3101 voltages.
Ye s
Check for 
5VDC
Is 9V3 
present?
Check Supply Voltage 
circuitry. Check Q0681, 
U4211 and U0641.
No
No
No
Check U4501. 
Check varactor filter.
NoYe s
Ye s
Ye s
A
A
B
weak RFRF
Signal at 
C4009?