Motorola Gm328 Gm338 Gm398 Detailed 6804112j18 E Manual

							i
Table of Contents
Section 1 Model Chart and Technical Specifications
1.0 GM338 Model Chart............................................................................................. 1-1
2.0 Technical Specifications ...................................................................................... 1-1
Section 2 Theory of Operation
1.0 Introduction .......................................................................................................... 2-1
2.0 VHF (136-174 MHz) Receiver.............................................................................. 2-1
2.1 Receiver Front-End ........................................................................................ 2-1
2.2 Front-End Band-Pass Filters & Pre-Amplifier ................................................. 2-2
2.3 First Mixer and 1st Intermediate Frequency (IF) ............................................ 2-2
2.4 2nd Intermediate Frequency (IF) and Receiver Back End ............................. 2-3
3.0 Transmitter Power Amplifier (PA) 45 W ............................................................... 2-3
3.1 Power Controlled Stage.................................................................................. 2-4
3.2 Pre Driver Stage ............................................................................................. 2-4
3.3 Driver Stage.................................................................................................... 2-4
3.4 Final Stage ..................................................................................................... 2-4
3.5 Directional Coupler ......................................................................................... 2-4
3.6 Antenna Switch............................................................................................... 2-5
3.7 Harmonic Filter ............................................................................................... 2-5
3.8 Power Control ................................................................................................. 2-5
4.0 Frequency Synthesis ........................................................................................... 2-6
4.1 Reference Oscillator ....................................................................................... 2-6
4.2 Fractional-N Synthesizer ................................................................................ 2-6
4.3 Voltage Controlled Oscillator (VCO) ............................................................... 2-7
4.4 Synthesizer Operation .................................................................................... 2-8
Section 3 Troubleshooting Charts
1.0 Troubleshooting Flow Chart for Receiver ............................................................ 3-1
2.0 Troubleshooting Flow Chart for 45W Transmitter ................................................ 3-3
3.0 Troubleshooting Flow Chart for Synthesizer ........................................................ 3-5
4.0 Troubleshooting Flow Chart for VCO ................................................................... 3-6 
						

							ii
Section 4 VHF PCB/Schematics/Parts List
1.0 Allocation of Schematics and Circuit Boards ....................................................... 4-1
1.1 Controller Circuits ........................................................................................... 4-1
2.0 VHF 25-45W PCB / Schematics / Parts List ........................................................ 4-3
VHF (136-174 MHz) 25-45W 8486140B13 Top Side ............................................. 4-3
VHF (136-174 MHz) 25-45W 8486140B13  Bottom Side ....................................... 4-4
VHF (136-174 MHz) Power Amplifier 25-45W........................................................ 4-5
VHF (136-174 MHz) FRACN .................................................................................. 4-6
VHF (136-174 MHz) Voltage Controlled Oscillator ................................................. 4-7
VHF (136-174 MHz) Receiver Front End ............................................................... 4-8
VHF (136-174 MHz) IF ........................................................................................... 4-9
VHF PCB 8486140B13 Parts List 25-45W ........................................................... 4-10 
						

							1-1
Section 1
MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM338 Model Chart
2.0 Technical Specifications
Data is specified for +25°C unless otherwise stated.
GM Series, VHF 136-174 MHz
Model Description
AZM25KKF9AA5GM338 136-174 MHz 25-45W
Item Description
XGCN6114_GM338 Control Head Direct Mount
X IMUD6011_ Tanapa WM 136-174 MHz 25-45W
XRAD4198_BNC 136-144 MHz, 1/4 Wave Roof Mount
X RAD4199_ BNC 146-150.8 MHz, 1/4 Wave Roof Mount
XRAD4200_BNC 150.8-162 MHz, 1/4 Wave Roof Mount
X RAD4201_ BNC 162-174 MHz, 1/4 Wave Roof Mount
XRAD4202_BNC 146-172 MHz, 3dB Gain Roof Mount
X 6804112J06 GM338 User Guide
x = Indicates one of each is required.
General Specifications
Channel Capacity
GM338
128
Power Supply 13.2Vdc (10.8 - 15.6Vdc)
Dimensions:  H x W x D (mm)  Depth excluding knobsGM338
59mm x 179mm x 198mm (25 - 45W)
(add 9mm for Volume Knob)
Weight GM338 1400 g
Sealing:Withstands rain testing per 
MIL STD 810 C/D /E and IP54
Shock and Vibration: Protection provided via impact
resistant housing exceeding MIL STD 
810-C/D /E
Dust, Salt & FogProtection provided via environment 
resistant housing exceeding MIL STD 
810 C/D /E  
						

							1-2Technical Specifications
*Availability subject to the laws and regulations of individual countries.Transmitter VHF
*Frequencies - Full BandsplitVHF 136-174 MHz
Channel Spacing12.5/20/25 kHz
Frequency Stability
(-30°C to +60°C, +25° Ref.)±2.5 ppm
Power 25-45W 
Modulation Limiting
±2.5 @ 12.5 kHz 
±4.0 @ 20 kHz
±5.0 @ 25 kHz
FM Hum & Noise-40 dB @ 12.5kHz
-45 dB @ 20/25kHz
Conducted/Radiated Emission (ETS)-36 dBm 1 GHz
Adjacent Channel Power-60 dB @ 12.5 kHz
-70 dB @ 25 kHz
Audio Response (300 - 3000Hz)+1 to -3 dB
Audio Distortion
@1000Hz, 60%
Rated Maximum Deviation
65 dB
Adjacent Channel Selectivity (ETS)
65 dB @ 12.5 kHz 
75 dB @ 20 kHz
80 dB @ 25 kHz
Spurious Rejection (ETS)75 dB @ 12.5 kHz
80 dB @ 20/25 kHz
Rated Audio
3W Internal
7.5W External
13W External
Audio Distortion @ Rated Audio
						

							2-1
Section 2
THEORY OF OPERATION
1.0 Introduction
This Chapter provides a detailed theory of operation for the VHF circuits in the radio. For details of 
the theory of operation and troubleshooting for the the associated Controller circuits refer to the 
Controller Section of this manual.
2.0 VHF (136-174 MHz) Receiver
2.1 Receiver Front-End
The receiver is able to cover the VHF range from 136 to 174 MHz. It consists of four major blocks: 
front-end bandpass filters and pre-amplifier, first mixer, 1st IF, 2nd IF, and receiver back-end. Two 
varactor-tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode mixer 
converts the signal to the first IF of 44.85 MHz. High-side injection is used..
Figure 2-1 VHF Receiver Block Diagram
Demodulator
1. Crystal 
Filter Mixer Va r a c t o r  
Tuned Filter RF Amp Va r a c t o r  
Tuned Filter Pin Diode 
Antenna 
Switch
RF Jack
Control Voltage
from PCICFirst LO
from FGU
Recovered Audio
RSSI
IF
Second LO
2. Crystal 
Filter
455kHz Filter
(25kHz)455kHz Filter
(25kHz)
455kHz Filter
(12.5kHz)455kHz Filter
(12.5kHz)SwitchSwitchSwitchSwitch
Limiter
1. IF Amp
2. IF Amp
Filter Bank Selection
from Synthesizer IC 
						

							2-2VHF (136-174 MHz) Receiver
There are two 2-pole 44.85 MHz crystal filters in the 1st IF section and 2 pairs of 455 kHz ceramic 
filters in the 2nd IF section to provide the required adjacent channel selectivity. The correct pair of 
ceramic filters for 12.5 or 25kHz channel spacing is selected via control line BWSELECT. The 
second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The processing of the 
demodulated audio signal is performed by an audio processing IC located in the controller section.
2.2 Front-End Band-Pass Filters & Pre-Amplifier 
The received signal from the radio’s antenna connector is first routed through the harmonic filter and 
antenna switch, which are part of the RF power amplifier circuits, before being applied to the receiver 
pre-selector filter (C3001, C3002, D3001 and associated components). The 2-pole pre-selector filter 
tuned by the dual varactor diode D3001 pre-selects the incoming signal (RXIN) from the antenna 
switch to reduce spurious effects to following stages. The tuning voltage (FECTRL_1) ranging from 2 
volts to 8 volts is controlled by pin 20 of PCIC (U3501) in the Transmitter section. A dual hot carrier 
diode (D3003) limits any inband signal to 0 dBm to prevent damage to the pre-amplifier.
The RF pre-amplifier is a surface mount device (SMD) Q3001 with collector-base feedback to 
stabilize gain, impedance, and intermodulation. Transistor Q3002 compares the voltage drop across 
resistor R3002 with a fixed base voltage from divider R3011, R3000 and R3012, and adjusts the 
base current of Q3001 as necessary to maintain its collector current constant at approximately 15-20 
mA. Operating voltage is from the regulated 9.3V supply (9V3). During transmit, 9.1 volts (K9V1) 
turns off both transistors Q3002 and Q3001. This protects the RF pre-amplifier from excessive 
dissipation during transmit mode. A following 3dB pad (R3006 – R3008 and R3016 – R3018) 
stabilizes the output impedance and intermodulation performance.
A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal. 
The dual varactor diode D3004 is controlled by the same signal FECTRL_1, which controls the pre-
selector filter.
2.3 First Mixer and 1st Intermediate Frequency (IF)
The signal coming from the front-end is converted to the 1st IF frequency of 44.85 MHz using a cross 
over quad diode mixer (D3031). Its ports are matched for incoming RF signal conversion to the 44.85 
MHz IF using high side injection. The high-side injection signal (RXINJ) from the frequency 
synthesizer circuit has a level of approximately +13 dBm and is injected via matching transformer 
T3002.
The IF output signal (IF) from transformer T3001 pin 2 is fed to the first 2- pole crystal filter FL3101. 
The filter output in turn is matched to IF amplifier Q3101 which is actively biased by a collector base 
feedback (R3101, R3106) to a current drain of approximately 5 mA drawn from the 5 volt supply. Its 
output impedance is matched to the second 2-pole crystal filter FL3102. The signal is further 
amplified by a preamplifier (Q3102) before going into pin 1 of IFIC (U3101).
A dual hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at 
RF input levels above -27 dBm. 
						

							Transmitter Power Amplifier (PA) 45 W2-3
2.4 2nd Intermediate Frequency (IF) and Receiver Back End
The 44.85 MHz 1st IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the 
IF IC, the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO) to 
produce the 2nd IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The 
2nd IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters FL3112, FL3114 
for 20/25 kHz channel spacing or FL3111, FL3113/F3115 for 12.5 kHz channel spacing. These pairs 
are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter 
input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide 
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% 
deviation) from U3101 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (part of the 
Controller circuits). 
A received signal strength indicator (RSSI) signal is available at U3101, pin 5, having a dynamic 
range of 70 dB. The RSSI signal is interpreted by the µP (U0101, pin 63) and in addition is available 
at accessory connector J0501-15. 
3.0 Transmitter Power Amplifier (PA) 45 W
The radio’s 45 W PA is a four-stage amplifier used to amplify the output from the VCOBIC to the 
radio transmit level. The line-up consists of three stages which utilize LDMOS technology, followed 
by a final stage using a bipolar device. The gain of the first stage (U3401) is adjustable, controlled by 
pin 4 of PCIC (U3501) via Q3501 and Q3502 (VCONT). It is followed by an LDMOS pre-driver stage 
(Q3421), an LDMOS driver stage (Q3431) and a bipolar final stage (Q3441).
Figure 2-2 VHF Transmitter Block Diagram 
Devices U3401 and Q3421 are surface mounted. The remaining devices are directly attached to the 
heat sink.
Antenna
To Microprocessor
PCIC
Pin Diode 
Antenna 
Switch
RF Jack
Harmonic 
Filter
PowerSensePA - F i n a lStagePADriver From VCOControlledStag e
VcontrolBias 1Bias 2
To Microprocessor
Temperature
Sense SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
PreDriver 
						

							2-4Transmitter Power Amplifier (PA) 45 W
3.1 Power Controlled Stage
The first stage (U3401) is a 20 dB gain integrated circuit containing two LDMOS FET amplifier 
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U3401 is 
controlled by a dc voltage applied to pin 1 from the power control circuit (U3501 pin 4, with 
transistors Q3501 and Q3502 providing current gain and level-shifting). The control voltage 
simultaneously varies the bias of two FET stages within U3401. This biasing point determines the 
overall gain of U3401 and therefore its output drive level to Q3421, which in turn controls the output 
power of the PA.
In receive mode the voltage control line is at ground level and turns off Q3501-2, which in turn 
switches off the biasing voltage to U3401.
3.2 Pre Driver Stage
The next stage is an LDMOS device (Q3421) providing a gain of +13 dB. This device requires a 
positive gate bias and a quiescent current flow for proper operation. The voltage of the line 
PCIC_MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q3421 via 
the resistive network R3410, R3415, and R3416. The bias voltage is factory tuned.
3.3 Driver Stage
The following stage is an enhancement-mode N-Channel MOSFET device (Q3431) providing a gain 
of 10 dB. This device also requires a positive gate bias and a quiescent current flow for proper 
operation. The voltage of the line MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the 
gate of Q3431 via the resistive network R3404, R3406, and R3431-5. This bias voltage is also tuned 
in the factory. If the transistor is replaced, the bias voltage must be tuned using the Customer 
Programming Software (CPS). Care must be taken not to damage the device by exceeding the 
maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s dc 
supply voltage input, PASUPVLTG, via L3431 and L3432.
3.4 Final Stage
The final stage uses bipolar device Q3441. The device’s collector current is also drawn from the 
radio’s dc supply voltage input. To maintain class C operation, the base is dc-grounded by a series 
inductor (L3441) and a bead (L3442).   A matching network consisting of C3446-52, C3467, L3444-
5, and two striplines, transforms the impedance to approximately 50 ohms and feeds the directional 
coupler.
3.5 Directional Coupler
The directional coupler is a microstrip printed circuit, which couples a small amount of the forward 
and reflected power delivered by Q3441. The coupled signals are rectified by D3451-2 and 
combined by R3463-4. The resulting dc voltage is proportional to RF output power and feeds the 
RFIN port of the PCIC (U3501, pin 1). The PCIC controls the gain of stage U3401 as necessary to 
hold this voltage constant, thus ensuring the forward power out of the radio to be held to a constant 
value.
An abnormally high reflected power level, such as may be caused by a damaged antenna, also 
causes the dc voltage applied to the PCIC to increase, and this will cause a reduction in the gain of 
U3401, reducing transmitter output power to prevent damage to the final device due to an improper 
load. 
						

							Transmitter Power Amplifier (PA) 45 W2-5
3.6 Antenna Switch
The antenna switch consists of two PIN diodes, D3471 and D3472. In the receive mode, both diodes 
are off. Signals applied at the antenna jack J3401 are routed, via the harmonic filter, through 
network L3472, C3474 and C3475, to the receiver input. In the transmit mode, the keyed 9 volts 
turns on Q3471 which enables current sink Q3472, set to 96 mA by R3473 and VR3471. This 
completes a dc path from PASUPVLTG, through L3473, D3471, L3477, L3472, D3472, L3471, 
R3474 and the current sink, to ground. Both diodes are forward biased into conduction. The 
transmitter RF from the directional coupler is routed via D3471 to the harmonic filter and antenna 
jack. D3472 also conducts, shunting RF power and preventing it from reaching the receiver port 
(RXIN). L3472 is selected to appear as a broadband guarter-wave transmission line, making the 
short circuit presented by D3472 appear as an open circuit at the junction of D3472 and the receiver 
path.
3.7 Harmonic Filter
Components L3491-L3494 and C3490-C3498 form a nine-pole Chebychev low-pass filter to 
attenuate harmonic energy of the transmitter. R3490 is used to drain electrostatic charge that might 
otherwise build up on the antenna. The harmonic filter also prevents high level RF signals above the 
receiver passband from reaching the receiver circuits, improving spurious response rejection.
3.8 Power Control
The transmitter uses the power control IC (PCIC, U3501) to control the power output of the radio. A 
portion of the forward and reflected RF power from the transmitter is sampled by the directional 
coupler, rectified and summed, to provide a dc voltage to the RFIN port of the PCIC (pin 1) which is 
proportional to the sampled RF power. 
The ASFIC contains a digital to analog converter (DAC) which provides a reference voltage of the 
control loop to the PCIC via R3517. The reference voltage level is programmable through the SPI 
line of the PCIC. This reference voltage is proportional to the desired power setting of the transmitter, 
and is factory programmed at several points across the frequency range of the transmitter to offset 
frequency response variations of the transmitter’s power detector circuit.
The PCIC provides a dc output voltage at pin 4 (INT) which is amplified and shifted in dc level by 
stages Q3501 and Q3502. The 0 to 4 Vdc range at U1503, pin 4 is translated to a 0 to 8.5 Vdc range 
at the output of Q3501, and applied as VCONT to the power-adjust input pin of the first transmitter 
stage U3401. This adjusts the transmitter power output to the intended value. Variations in forward 
or reflected transmitter power cause the dc voltage at pin 1 to change, and the PCIC adjusts the 
control voltage above or below its nominal value to raise or lower output power.
Capacitors C3502-4, in conjunction with resistors and integrators within the PCIC, control the 
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into 
adjacent channels.
U3502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity 
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29) 
proportional to temperature. If the dc voltage produced exceeds the set threshold in the PCIC, the 
transmitter output power is reduced so as to reduce the transmitter temperature. 
						

							2-6Frequency Synthesis
4.0 Frequency Synthesis
The frequency synthesizer subsystem consists of the reference oscillator (Y3261 or Y3262), the 
Low Voltage Fractional-N synthesizer (LVFRAC-N, U3201), and the voltage-controlled oscillators 
and buffer amplifiers (U3301, Q3301-2 and associated circuits).
4.1 Reference Oscillator
The reference oscillator (Y3262) contains a temperature compensated crystal oscillator with a 
frequency of 16.8 MHz. An analog-to-digital (A/D) converter internal to U3201 (LVFRAC-N) and 
controlled by the µP via serial interface (SRL) sets the voltage at the warp output of U3201 (pin 25) 
to set the frequency of the oscillator. The output of the oscillator (U3262 pin 3) is applied to pin 23 
(XTAL1) of U3201 via R3263 and C3235.
In applications were less frequency stability is required, the oscillator inside U3201 is used along 
with an external crystal Y3261, varactor diode D3261, C3261, C3262 and R3262. In this case, 
Y3262, R3263, C3235 and C3251 are not used. When Y3262 is used, Y3261, D3261, C3261, 
C3262 and R3262 are not used, and C3263 is increased to 0.1 uF.
4.2 Fractional-N Synthesizer
The LVFRAC-N synthesizer IC (U3201) consists of a pre-scaler, a programmable loop divider, 
control divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital 
modulation, a balance attenuator to balance the high frequency analog modulation and low 
frequency digital modulation, a 13 volt positive voltage multiplier, a serial interface for control, and 
finally a super filter for the regulated 5 volts.
Figure 2-3 VHF Synthesizer Block Diagram
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U3211 PIN 1)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
        1540FILTERED 5VSTEERING LOCK (U0101 PIN 56)
PRESCALER INFREF (U0221 PIN 34)
39 BIAS2
41
 48 5, 20, 34, 36
+5V (U3211 PIN 1)
AUX1 VDD, DC5VMODOUT
U3201 
LOW VOLTAGEFRACTIONAL-N
SYNTHESIZER
AUX2
TRBTX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
2-POLE
LOOP
FILTER
1