Acer Travelmate 7300 Service Guide

2-24Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
SUSA# O
SUSPEND PLANE A CONTROL. Control signal asserted during power
management suspend states. SUSA# is primarily used to control the primary
power plane. This signal is asserted during POS, STR, and STD suspend states.
During Reset: Low After Reset: High During POS: Low
SUSB#/
GPO15O
SUSPEND PLANE B CONTROL. Control signal asserted during power
management suspend states. SUSB# is primarily used to control the secondary
power...

Major Chips Description 2-25
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
GPO[30:0] O
GENERAL PURPOSE OUTPUTS. These output signals can be controlled via the
GPIREG register located in Function 3 (Power Management) System IO Space at
address PMBase+34h.
If a GPO pin is not multiplexed with another signal or defaults to GPO, then its
state after reset is the reset condition of the GPOREG register. If the GPO
defaults to another signal, then it defaults to that signal’s state after reset.  The...

2-26Service Guide
SignalNameMultiplexedWithDefaultControl Registerand Bit (PCIFunction 1)
Notes
GPO[9:11] GNT[A:C]# GPO GENCFG
Bits [8:10]Not available as GPO if using for PC/PCI. Can be
individually enabled, so GPO[11] is available if
REQ[C]# not used.
GPO12 APICACK# GPO XBCS
Bit 8Not available as GPO if using external APIC.
GPO13 APICCS# GPO XBCS
Bit 8Not available as GPO if using external APIC.
GPO14 IRQ0 GPO XBCS
Bit 8Not available as GPO if using external APIC.
GPO15 SUSB# SUSB# GENCFG
Bit 17Not...

Major Chips Description 2-27
Table 2-2 82371AB Pin Descriptions (continued)
NameTypeDescription
CONFIG2 I
CONFIGURATION SELECT 2. This input signal is used to select the positive or
subtractive decode of FFFF0000h–FFFFFFFFh memory address range (top
64 Kbytes).  If CONFIG[2]=0, the PIIX4 will positively decode this range. If
CONFIG[2]=1, the PIIX4 will decode this range with subtractive decode timings
only. The input value of this pin must be static and may not dynamically
change during system...

2-28Service Guide
2.3 NM2160
The NM2160 is a high performance Flat Panel Video Accelerator that integrates in one single chip, 2
Mbytes of High Speed DRAM, 24-bit true-color RAMDAC, Graphics/Video Accelerator, Dual clock
synthesizer, TV Out support, ZV(Zoomed Video) port, Z-Buffer Data Stripping, PCI Bus Mastering and a
high speed glueless 32-bit PCI 2.1 compliance interface.
By integrating the display buffer DRAM and 128-bit graphics/video accelerator, the NM2160 achieves the
leading performance in the...

Major Chips Description 2-29
· High Speed 2Mbytes of integrated DRAM
· 128 bit Memory Interface
· Bus Support
· PCI 2.1 compliance Local Bus(Zero wait states)
· 3.3Volts or 5Volts operation
· EMI Reduction
· Spread Spectrum Clocking technology for reduced panel EMI
· Hardware Cursor and Icon
· Relocatable Hardware Cursor and Icon
· 64X64 Hardware Cursor
· 64X64 or 128X128 Hardware Icon
· Green PC Support
· VESA Display Power management(DPMS)
· DAC Power Down modes
· Suspend/Standby/Clock management
· VGA...

2-30Service Guide
2.3.2 Pin Diagram
Figure 2-3 NM2160 Pin Diagram 

Major Chips Description 2-31
2.3.3 Pin Descriptions
Conventions used in the pin description types:
I Input into NM2160
O Output from NM2160
I/O Input and Output to/from NM2160
T/S Tri-state during un-driven state
S/T/S Before becoming tri-state the pin will be driven inactive
O/D Open-drain type output
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
PCI Interface
61
60
58
56
55
54
53
52
50
49
48
47
46
45
43
41
39
38
37
36
35
34
33
32
30
28
26
24
22
21
20
19AD31
AD30
AD29
AD28
AD27
AD26...

2-32Service Guide
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
72 FRAME# I/O
Frame This active-low signal is driven by the bus master to
indicate the beginning and duration of an access. NM2160 drives
this pin in the Bus Master mode
65 PAR I/O
Parity Even parity across AD31:0&C/BE3:0# is driven by the bus
master during address and write data phases and driven by
NM2160 during read data phases
67 TRDY# I/O
S/T/STarget ready This active low signal indicates NM2160’s ability to
complete...

Major Chips Description 2-33
Table 2-3 NM2160 Pin Descriptions
NumberPin nameI/ODescription
83 XCKEN I
External Clock Enable This pin is used to select between
internally synthesized clocks or externally supplied clocks. A low
level on the pin selects internal mode and a high level selects
external mode. In the external clock mode, the internal clock
synthesizers will be disabled completely. Both PVCLK and PMCLK
pins should be driven with the desired clock rates in external
mode. This pin should be...