Acer Travelmate 7300 Service Guide

2-14Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
KBCCS#/
GPO26O
KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O
read or write accesses to KBC locations 60h and 64h. It is driven combinatorially
from the ISA addresses SA[19:0] and LA[23:17].  If the keyboard controller does
not require a separate chip select, this signal can be programmed to a general
purpose output.
During Reset: High After Reset: High During POS: High/GPO
MCCS# O
MICROCONTROLLER CHIP SELECT. MCCS#...

Major Chips Description 2-15
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
XOE#/
GPO23O
X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output
enable of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data
bus, SD[7:0].  XOE# is asserted anytime a PIIX4 supported X-Bus device is
decoded, and the devices decode is enabled in the X-Bus Chip Select Enable
Register (BIOSCS#, KBCCS#, RTCCS#, MCCS#) or the Device Resource B
(PCCS0#) and Device Resource C (PCCS1#). XOE# is...

2-16Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
INTERRUPT CONTROLLER/APIC SIGNALS
APICACK#/
GPO12O
APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after
its internal buffers are flushed in response to the APICREQ# signal. When the I/O
APIC samples this signal asserted it knows that PIIX4’s buffers are flushed and
that it can proceed to send the APIC interrupt. The APICACK# output is
synchronous to PCICLK.  If the external APIC is not used, then this is a...

Major Chips Description 2-17
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
IRQ 12/M I
INTERRUPT REQUEST 12. In addition to providing the standard interrupt
function as described in the pin description for IRQ[3:7,9:11,14:15], this pin can
also be programmed to provide the mouse interrupt function.  When the mouse
interrupt function is selected, a low to high transition on this signal is latched by
PIIX4 and an INTR is generated to the CPU as IRQ12. An internal IRQ12
interrupt continues to be...

2-18Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
INIT OD
INITIALIZATION. INIT is asserted in response to any one of the following
conditions.  When the System Reset bit in the Reset Control Register is reset to
0 and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by
asserting INIT. PIIX4 also asserts INIT if a Shut Down Special cycle is decoded
on the PCI Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h,
bit 0. When asserted, INIT remains...

Major Chips Description 2-19
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
PCICLK I
FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK
provides timing for all transactions on the PCI Bus. All other PCI signals are
sampled on the rising edge of PCICLK, and all timing parameters are defined
with respect to this edge. Because many of the circuits in PIIX4 run off the PCI
clock, this signal MUST be kept active, even if the PCI bus clock is not active.
OSC I
14.31818-MHZ CLOCK....

2-20Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
PDDACK# O
PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device
DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices that
a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA data
transfer cycle. This signal is used in conjunction with the PCI bus master IDE
function. It is not associated with any AT compatible DMA channel.  If the IDE
signals are configured for Primary and...

Major Chips Description 2-21
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
SDA[2:0] O
SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in either
the ATA command block or control block is being addressed. If the IDE signals
are configured for Primary and Secondary, these signals are connected to the
corresponding signals on the Secondary IDE connector.  If the IDE signals are
configured for Primary Master and Primary Slave, these signals are used for the
Primary Slave connector....

2-22Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
SDIOR# O
SECONDARY DISK IO READ. In normal IDE mode, this is the command to the
IDE device that it may drive data onto the SDD[15:0] lines. Data is latched by the
PIIX4 on the negation edge of SDIOR#. The IDE device is selected either by the
ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0] lines, or the
IDE DMA slave arbitration signals (SDDACK#).  In an Ultra DMA/33 read cycle,
this signal is used as DMARDY# which...

Major Chips Description 2-23
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
POWER MANAGEMENT SIGNALS
BATLOW#/
GPI9I
BATTERY LOW. Indicates that battery power is low. PIIX4 can be programmed
to prevent a resume operation when the BATLOW# signal is asserted. If the
Battery Low function is not needed, this pin can be used as a general-purpose
input.
CPU_STP#/
GPO17O
CPU CLOCK STOP. Active low control signal to the clock generator used to
disable the CPU clock outputs. If this function is not needed,...