Acer Travelmate 7300 Service Guide
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Page 61
2-4Service Guide Enhanced Power Management PIIX4’s power management functions include enhanced clock control, local and global monitoring support for 14 individual devices, and various low-power (suspend) states, such as Power-On Suspend, Suspend-to-DRAM, and Suspend-to-Disk. A hardware-based thermal management circuit permits software-independent entrance to low-power states. PIIX4 has dedicated pins to monitor various external events (e.g., interfaces to a notebook lid, suspend/resume button, battery...
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Major Chips Description 2-5 · Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0 Specification and OS Directed Power Management · Integrated IDE Controller · Independent Timing of up to 4 Drives · PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec · Supports “Ultra DMA/33” Synchronous DMA Mode Transfers up to 33 Mbytes/sec · Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers · Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation · Enhanced DMA...
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2-6Service Guide The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-to- ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA channel supports...
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Major Chips Description 2-7 2.2.3 Block Diagram Figure 2-2 PIIX4 Simplified Block Diagram
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2-8Service Guide 2.2.4 Pin Descriptions This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. W hen “#” is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid...
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Major Chips Description 2-9
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
PCI BUS INTERFACE
AD[31:0] I/O
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits).
During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction
consists of an address phase followed by one or more data phases. Little-endian
byte ordering is used. AD[7:0] define the least significant byte (LSB) and...](http://img.usermanuals.tech/thumb/5/59855/w300_acer-travelmate-7300-service-guide-65.png "Page 66
Major Chips Description 2-9
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
PCI BUS INTERFACE
AD[31:0] I/O
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits).
During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction
consists of an address phase followed by one or more data phases. Little-endian
byte ordering is used. AD[7:0] define the least significant byte (LSB) and...")
Major Chips Description 2-9 Table 2-2 82371AB Pin Descriptions NameTypeDescription PCI BUS INTERFACE AD[31:0] I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction consists of an address phase followed by one or more data phases. Little-endian byte ordering is used. AD[7:0] define the least significant byte (LSB) and...
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2-10Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
IRDY# I/O
INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete
the current data phase of the transaction. It is used in conjunction with TRDY#. A
data phase is completed on any clock both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates PIIX4 has valid data present on
AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY# is an
input to PIIX4 when PIIX4 is the...](http://img.usermanuals.tech/thumb/5/59855/w300_acer-travelmate-7300-service-guide-66.png "Page 67
2-10Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
IRDY# I/O
INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete
the current data phase of the transaction. It is used in conjunction with TRDY#. A
data phase is completed on any clock both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates PIIX4 has valid data present on
AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY# is an
input to PIIX4 when PIIX4 is the...")
2-10Service Guide Table 2-2 82371AB Pin Descriptions NameTypeDescription IRDY# I/O INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates PIIX4 has valid data present on AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY# is an input to PIIX4 when PIIX4 is the...
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Major Chips Description 2-11
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
TRDY# I/O
TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase
is completed when both TRDY# and IRDY# are sampled asserted. During a read,
TRDY# indicates that PIIX4, as a Target, has place valid data on AD[31:0].
During a write, it indicates PIIX4, as a Target is prepared to latch data. TRDY# is
an input to PIIX4 when...](http://img.usermanuals.tech/thumb/5/59855/w300_acer-travelmate-7300-service-guide-67.png "Page 68
Major Chips Description 2-11
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
TRDY# I/O
TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase
is completed when both TRDY# and IRDY# are sampled asserted. During a read,
TRDY# indicates that PIIX4, as a Target, has place valid data on AD[31:0].
During a write, it indicates PIIX4, as a Target is prepared to latch data. TRDY# is
an input to PIIX4 when...")
Major Chips Description 2-11 Table 2-2 82371AB Pin Descriptions NameTypeDescription TRDY# I/O TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that PIIX4, as a Target, has place valid data on AD[31:0]. During a write, it indicates PIIX4, as a Target is prepared to latch data. TRDY# is an input to PIIX4 when...
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2-12Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
IOW# I/O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns
the ISA Bus. IOW# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
LA[23:17]/
GPO[7:1]I/O
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on
the ISA Bus up to 16 Mbytes. LA[23:17]...](http://img.usermanuals.tech/thumb/5/59855/w300_acer-travelmate-7300-service-guide-68.png "Page 69
2-12Service Guide
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
IOW# I/O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns
the ISA Bus. IOW# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
LA[23:17]/
GPO[7:1]I/O
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on
the ISA Bus up to 16 Mbytes. LA[23:17]...")
2-12Service Guide Table 2-2 82371AB Pin Descriptions NameTypeDescription IOW# I/O I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns the ISA Bus. IOW# is an input when an external ISA master owns the ISA Bus. During Reset: High-Z After Reset: High During POS: High LA[23:17]/ GPO[7:1]I/O ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes. LA[23:17]...
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Major Chips Description 2-13
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
SA[19:0] I/O
SYSTEM ADDRESS[19:0]. These bi-directional address lines define the
selection with the granularity of 1 byte within the 1-Megabyte section of memory
defined by the LA[23:17] address lines. The address lines SA[19:17] that are
coincident with LA[19:17] are defined to have the same values as LA[19:17] for
all memory cycles. For I/O accesses, only SA[15:0] are used, and SA[19:16] are
undefined. SA[19:0] are...](http://img.usermanuals.tech/thumb/5/59855/w300_acer-travelmate-7300-service-guide-69.png "Page 70
Major Chips Description 2-13
Table 2-2 82371AB Pin Descriptions
NameTypeDescription
SA[19:0] I/O
SYSTEM ADDRESS[19:0]. These bi-directional address lines define the
selection with the granularity of 1 byte within the 1-Megabyte section of memory
defined by the LA[23:17] address lines. The address lines SA[19:17] that are
coincident with LA[19:17] are defined to have the same values as LA[19:17] for
all memory cycles. For I/O accesses, only SA[15:0] are used, and SA[19:16] are
undefined. SA[19:0] are...")
Major Chips Description 2-13 Table 2-2 82371AB Pin Descriptions NameTypeDescription SA[19:0] I/O SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection with the granularity of 1 byte within the 1-Megabyte section of memory defined by the LA[23:17] address lines. The address lines SA[19:17] that are coincident with LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles. For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined. SA[19:0] are...