Acer Travelmate 7300 Service Guide

2-44Service Guide
2.5.2 Block Diagram
Figure 2-6 87C552 Block Diagram 

Major Chips Description 2-45
2.5.3 Pin Diagram
9 P4.2/CMSR2
8 P4.1/CMSR1
7 P4.0/CMSR0
6 EW#
5 PWM1#
4 PWM0#
3 STADC
2 VDD
1 P5.0/ADC0
68 P5.1/ADC1
67 P5.2/ADC2
66 P5.3/ADC3
65 P5.4/ADC4
64 P5.5/ADC5
63 P5.6/ADC6
62 P5.7/ADC7
61 AVDD
60 AVSS
59 AVref+
58 AVref–
57 P0.0/AD0
56 P0.1/AD1
55 P0.2/AD2
54 P0.3/AD3
53 P0.4/AD4
52 P0.5/AD5
51 P0.6/AD6
50 P0.7/AD7
49 EA#/VPP
48 ALE/PROG#
47 PSEN#
46 P2.7/A15
45 P2.6/A14
44 P2.5/A13
43 P2.4/A12
42 P2.3/A11
41 P2.2/A10
40 P2.1/A09
39 P2.0/A08
38 NC
37 VSS
36 VSS
35...

2-46Service Guide
2.5.4 Pin Descriptions
Table 2-5 87C552 Pin Descriptions
MnemonicPin No.TypeName And Function
VDD2I
Digital Power Supply: 
+5V power supply pin during normal operation,
idle and power-down mode.
STADC 3 I
Start ADC Operation: 
Input starting analog to digital conversion (ADC
operation can also be started by software).
PWM0# 4 O
Pulse Width Modulation: 
Output 0.
PWM1# 5 O
Pulse Width Modulation: 
Output 1
EW# 6 I
Enable Watchdog Timer: 
Enable for T3 watchdog timer and disable...

Major Chips Description 2-47
Table 2-5 87C552 Pin Descriptions
MnemonicPin No.TypeName And Function
P4.0-P4.7 7-14 I/O
Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
7-12 O
CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs
on a match with timer T2. 13, 14
13, 14 O
CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a
match with timer T2.
P5.0-P5.7 68-62, I
Port 5: 8-bit input port.
1
ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to...

2-48Service Guide
2.6  NS97338VJG Super I/O Controller
The PC97338VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA
based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs, and an
IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the peripherals and a
set of configuration registers are also implemented in this highly integrated member of the Super l/O
family. Advanced power management features, mixed voltage...

Major Chips Description 2-49
· The Bidirectional Parallel Port:
· Enhanced Parallel Port(EPP) compatible
· Extended Capabilities Port(ECP) compatible, including level 2 support
· Bidirectional under either software or hardware control
· Compatible with ISA, and EISA, architectures
· Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk
Drive(FDD)
· Includes protection circuit to prevent damage to the parallel port when a connected printer is
powered up or is...

2-50Service Guide
2.6.2 Block Diagram
Configuration
Re
gisters
UART
(16550 or 16450)UART
+ IrDA/HP & Sharp IR
(16550 or 16450)
General
Purpose
Re
gisters
Power
Down Lo
gic
IEEEE1284
Parallel Port
Hifh Current Driver
Floppy Disk
Controller with
Di
gital Data
Separator
(Enhabced 8477)
I/O Ports Control
InterruptData HandshakeFloppy
Drive
Interface
OSCInterrupt
and
DMAFloppy
Drive
Interface InterruptIR
Interface Serial
Interface Interrupt Serial
Interface Confi
g.
Inputs
Figure 2-8 NS97338VJG Block Diagram 

Major Chips Description 2-51
2.6.3 Pin Diagram
Figure 2-9 NS97338VJG Pin Diagram 

2-52Service Guide
2.6.4 Pin Description
Table 2-6 NS97338VJG Pin Descriptions
PinNo.I/ODescription
A15-A0 67, 64,
62-60,
29, 19-
28I
Address.
  These address lines from the microprocessor determine
which internal register is accessed.  A0-A15 are dont cares during
DMA transfer.
/ACK 83 I
Parallel Port Acknowledge.
  This input is pulsed low by the printer to
indicate that it has received the data from the parallel port.  This pin
has a nominal 25 KW pull-up resistor attached to it.
ADRATE0,
ADRATE196,...

Major Chips Description 2-53
Table 2-6 NS97338VJG Pin Descriptions
PinNo.I/ODescription
/CTS1,
/CTS272, 64 I
UARTs Clear to Send.  W hen low, this indicates that the modem or
data set is ready to exchange data.  The /CTS signal is a modem
status input.  The CPU tests the condition of this /CTS signal by
reading bit 4 (CTS) of the Modem Status Register (MSR) for the
appropriate serial channel.  Bit 4 is the complement of the CTS signal.
Bit 0 (DCTS) has no effect on the transmitter.
/CTS2 is multiplexed...