Acer Travelmate 7100 Service Guide

Major Chips Description2-23Table 2-282371AB Pin DescriptionsNameTypeDescriptionUSBP0+,
USBP0–I/O
SERIAL BUS PORT 0. This signal pair comprises the differential data signal for
USB port 0.
During Reset: High-Z After Reset: High-Z During POS: High-ZUSBP1+,
USBP1–I/O
SERIAL BUS PORT 1. This signal pair comprises the differential data signal for
USB port 1.
During Reset: High-Z After Reset: High-Z During POS: High-ZPOWER MANAGEMENT SIGNALSBATLOW#/
GPI9I
BATTERY LOW. Indicates that battery power is low. PIIX4...

2-24Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionSMBALERT#/
GPI11I
SM BUS ALERT. Input used by System Management Bus logic to generate an
interrupt (IRQ or SMI) or power management resume event when enabled. If this
function is not needed, this pin can be used as a general-purpose input.SMBCLKI/O
SM BUS CLOCK. System Management Bus Clock used to synchronize transfer
of data on SMBus.
During Reset: High-Z After Reset: High-Z During POS: High-ZSMBDATAI/O
SM BUS DATA. Serial data line...

Major Chips Description2-25Table 2-282371AB Pin DescriptionsNameTypeDescriptionGENERAL PURPOSE INPUT AND OUTPUT SIGNALSSome of the General Purpose Input and Output signals are multiplexed with other PIIX4 signals. The usage
is determined by the system configuration.  The default pin usage is shown in Table 1 and Table 2. The
configuration can be selected via the General Configuration register and X-Bus Chip Select register.GPI[21:0]IGENERAL PURPOSE INPUTS. These input signals can be monitored via the...

2-26Service GuideSignalNameMultiplexedWithDefaultControl Registerand Bit (PCIFunction 1)NotesGPO0GPONon-multiplexed GPO which is always available.GPO[1:7]LA[17:23]GPOGENCFG
Bit 0Available as GPO only if EIO mode.GPO8GPONon-multiplexed GPO which is always available.
The GPO[8] signal will be driven low upon removal
of power from the PIIX4 core power plane.GPO[9:11]GNT[A:C]#GPOGENCFG
Bits [8:10]Not available as GPO if using for PC/PCI. Can be
individually enabled, so GPO[11] is available if
REQ[C]# not...

Major Chips Description2-27Table 2-282371AB Pin Descriptions (continued)NameTypeDescriptionCONFIG1ICONFIGURATION SELECT 1. This input signal is used to select the type of
microprocessor being used in the system. If CONFIG1=0, the system contains
a Pentium microprocessor. If CONFIG1=1, the system contains a Pentium II
microprocessor. It is used to control the polarity of INIT and CPURST signals.CONFIG2ICONFIGURATION SELECT 2. This input signal is used to select the positive or
subtractive decode of...

2-28Service Guide2.3 NM2160
The NM2160 is a high performance Flat Panel Video Accelerator that integrates in one single chip, 2
Mbytes of High Speed DRAM, 24-bit true-color RAMDAC, Graphics/Video Accelerator, Dual clock
synthesizer, TV Out support, ZV(Zoomed Video) port, Z-Buffer Data Stripping, PCI Bus Mastering and a
high speed glueless 32-bit PCI 2.1 compliance interface.
By integrating the display buffer DRAM and 128-bit graphics/video accelerator, the NM2160 achieves the
leading performance in the...

Major Chips Description2-29· High Speed 2Mbytes of integrated DRAM
· 128 bit Memory Interface
· Bus Support
· PCI 2.1 compliance Local Bus(Zero wait states)
· 3.3Volts or 5Volts operation
· EMI Reduction
· Spread Spectrum Clocking technology for reduced panel EMI
· Hardware Cursor and Icon
· Relocatable Hardware Cursor and Icon
· 64X64 Hardware Cursor
· 64X64 or 128X128 Hardware Icon
· Green PC Support
· VESA Display Power management(DPMS)
· DAC Power Down modes
· Suspend/Standby/Clock management
· VGA...

2-30Service Guide2.3.2 Pin DiagramFigure 2-3NM2160 Pin Diagram 

Major Chips Description2-312.3.3 Pin Descriptions
Conventions used in the pin description types:
IInput into NM2160
OOutput from NM2160
I/OInput and Output to/from NM2160
T/STri-state during un-driven state
S/T/SBefore becoming tri-state the pin will be driven inactive
O/DOpen-drain type output
Table 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescriptionPCI Interface61
60
58
56
55
54
53
52
50
49
48
47
46
45
43
41
39
38
37
36
35
34
33
32
30
28
26
24
22
21
20
19AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23...

2-32Service GuideTable 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescription72FRAME#I/O
Frame This active-low signal is driven by the bus master to
indicate the beginning and duration of an access. NM2160 drives
this pin in the Bus Master mode65PARI/O
Parity Even parity across AD31:0&C/BE3:0# is driven by the bus
master during address and write data phases and driven by
NM2160 during read data phases67TRDY#I/O
S/T/STarget ready This active low signal indicates NM2160’s ability to
complete the current...