Acer Travelmate 7100 Service Guide

Major Chips Description2-53Table 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/CTS1,
/CTS272, 64I
UARTs Clear to Send.  When low, this indicates that the modem or
data set is ready to exchange data.  The /CTS signal is a modem
status input.  The CPU tests the condition of this /CTS signal by
reading bit 4 (CTS) of the Modem Status Register (MSR) for the
appropriate serial channel.  Bit 4 is the complement of the CTS signal.
Bit 0 (DCTS) has no effect on the transmitter.
/CTS2 is multiplexed with...

2-54Service GuideTable 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/DR1
(PPM Mode)83O
FDC Drive Select 1.  This pin offers an additional Drive Select signal
in PPM Mode when PNF = 0.  It is drive select 1 when bit 4 of FCR is
0.  It is drive select 0 when bit 4 of FCR is 1.  This signal is active low./DR2347O
FDC Drive 2 or 3.  /DR23 is asserted when either Drive 2 or Drive 3 is
assessed(except during logical drive exchange)./DRATE0
/DRATE1
(Normal Mode)50, 49O
FDC Data Rate 0, 1.  These outputs...

Major Chips Description2-55Table 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/HDSEL
(Normal Mode)32O
FDC Head Select.  This output determines which side of the FDD is
accessed.  Active selects side 1, inactive selects side 0./HDSEL
(PPM Mode)77O
FDC Head Select.  This pin offers an additional Head Select signal in
PPM Mode when PNF = 0.IDLE41O
FDD IDLE.  IDLE indicates that the FDC is in the IDLE state and can
be powered down.  Whenever the FDC is in IDLE state, or in power-
down state, the pin is...

2-56Service GuideTable 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescriptionIRTX63O
Infrared Transmit. Infrared serial data output.  Software configuration
selects either IrDA or Sharp-IR protocol.
This pin is multiplexed with SOUT2/BOUT/CFG0.MR100I
Master Reset.  Active high output that resets the controller to the idle
state and resets all disk interface outputs to their inactive states.  The
DOR, DSR, CCR, Mode command, Configure command, and Lock
command parameters are cleared to their default values....

Major Chips Description2-57Table 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/RI1
/RI268, 60I
UARTs Ring Indicator.  When low, this indicates that a telephone ring
signal has been received by the modem.  The /RI signal is a modem
status input whose condition is tested by the CPU by reading bit 6 (RI)
of the Modem Status Register (MSR) for the appropriate serial
channel.  Bit 6 is the complement of the RI signal.  Bit 2 ( TERI) of the
MSR indicates whether the RI input has changed from low to high...

2-58Service GuideTable 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/TRK0
(Normal Mode)35I
FDC Track 0.  This input indicates the controller that the head of the
selected floppy disk drive is at track zero./TRK0
(PPM Mode)91I
FDC Track 0.  This pin gives an additional Track 0 signal in PPM
Mode when PNF = 0.VDDB, C48, 97
Power Supply.  This is the 3.3V/5V supply voltage for the
PC87332VJG circuitry.VSSB-E40, 7,
88, 59Ground.  This is the ground for the PC87332VJG circuitry./WAIT82I
EPP Wait.  This...

Major Chips Description2-592.7 CL-PD6832: PCI-to-CardBus Host Adapter
The CL-PD6832 is a single-chip PC Card host adapter solution capable of controlling two fully
independent CardBus sockets. The chip is compliant with PC Card Standard, PCMCIA 2.1, and
JEDIA 4.1 and is optimized for use in notebook and handheld computers where reduced form
factor and low power consumption are critical design objectives.
The CL-PD6832 chip employs energy-efficient, mixed-voltage technology that can reduce system
power...

2-60Service Guide· 208-pin PQFP
2.7.2 Pin DiagramFigure 2-10CL-PD6832 Pin Diagram
2.7.3 Pin Descriptions
The following conventions apply to the pin description tables:
· A pound sign (#) at the end of a pin name indicates an active-low signal for the PCI bus.
· A dash (-) at the beginning of a pin name indicates an active-low signal for the PCMCIA bus. 

Major Chips Description2-61· An asterisk (*)  at the end of a pin name indicates an active-low signal that is a general-
interface for the CL-PD6832.
· A double-dagger superscript (‡) at the end of the pin name indicates signals that are used for
power-on configuration switches.
· The l/O-type code (I/O) column indicates the input and output configurations of the pins on the
CL-PD6832.The possible types are defined below.I/O TypeDescriptionIInput pinI-PUInput pin with internal pull-up...

2-62Service GuideThe following table lists the pin descriptions
Table 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin NumberI/OPowerPCI Bus Interface PinsAD[31:0]
PCI Bus Address Input / Data
Input/Outputs: These pins connect to PCI bus
signals AD[31:0].4-5, 7-12, 16-20,
22-24, 38-43, 45-
46, 48 49, 51-56I/O4C/BE[3:0]#
PCI Bus Command / Byte Enables: The
command signaling and byte enables are
multiplexed on the same pins. During the
address phase of a transaction, C/BE[3:0]# are
interpreted as the...