Acer Travelmate 7100 Service Guide

Major Chips Description2-13Table 2-282371AB Pin DescriptionsNameTypeDescriptionSA[19:0]I/O
SYSTEM ADDRESS[19:0]. These bi-directional address lines define the
selection with the granularity of 1 byte within the 1-Megabyte section of memory
defined by the LA[23:17] address lines. The address lines SA[19:17] that are
coincident with LA[19:17] are defined to have the same values as LA[19:17] for
all memory cycles.  For I/O accesses, only SA[15:0] are used, and SA[19:16] are
undefined. SA[19:0] are outputs...

2-14Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionKBCCS#/
GPO26O
KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O
read or write accesses to KBC locations 60h and 64h. It is driven combinatorially
from the ISA addresses SA[19:0] and LA[23:17].  If the keyboard controller does
not require a separate chip select, this signal can be programmed to a general
purpose output.
During Reset: High After Reset: High During POS: High/GPOMCCS#O
MICROCONTROLLER CHIP SELECT. MCCS# is...

Major Chips Description2-15Table 2-282371AB Pin DescriptionsNameTypeDescriptionXOE#/
GPO23O
X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output
enable of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data
bus, SD[7:0].  XOE# is asserted anytime a PIIX4 supported X-Bus device is
decoded, and the devices decode is enabled in the X-Bus Chip Select Enable
Register (BIOSCS#, KBCCS#, RTCCS#, MCCS#) or the Device Resource B
(PCCS0#) and Device Resource C (PCCS1#). XOE# is...

2-16Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionINTERRUPT CONTROLLER/APIC SIGNALSAPICACK#/
GPO12O
APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after
its internal buffers are flushed in response to the APICREQ# signal. When the
I/O APIC samples this signal asserted it knows that PIIX4’s buffers are flushed
and that it can proceed to send the APIC interrupt. The APICACK# output is
synchronous to PCICLK.  If the external APIC is not used, then this is a general-...

Major Chips Description2-17Table 2-282371AB Pin DescriptionsNameTypeDescriptionIRQ 12/MI
INTERRUPT REQUEST 12. In addition to providing the standard interrupt
function as described in the pin description for IRQ[3:7,9:11,14:15], this pin can
also be programmed to provide the mouse interrupt function.  When the mouse
interrupt function is selected, a low to high transition on this signal is latched by
PIIX4 and an INTR is generated to the CPU as IRQ12. An internal IRQ12
interrupt continues to be generated...

2-18Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionINITOD
INITIALIZATION. INIT is asserted in response to any one of the following
conditions.  When the System Reset bit in the Reset Control Register is reset to
0 and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by
asserting INIT. PIIX4 also asserts INIT if a Shut Down Special cycle is decoded
on the PCI Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h,
bit 0. When asserted, INIT remains...

Major Chips Description2-19Table 2-282371AB Pin DescriptionsNameTypeDescriptionPCICLKI
FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK
provides timing for all transactions on the PCI Bus. All other PCI signals are
sampled on the rising edge of PCICLK, and all timing parameters are defined
with respect to this edge. Because many of the circuits in PIIX4 run off the PCI
clock, this signal MUST be kept active, even if the PCI bus clock is not active.OSCI
14.31818-MHZ CLOCK. Clock...

2-20Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionPDDACK#O
PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device
DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices
that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA
data transfer cycle. This signal is used in conjunction with the PCI bus master
IDE function. It is not associated with any AT compatible DMA channel.  If the
IDE signals are configured for Primary and Secondary,...

Major Chips Description2-21Table 2-282371AB Pin DescriptionsNameTypeDescriptionPIORDYI
PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is
directly driven by the corresponding IDE device IORDY signal.  In an Ultra
DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching data
on rising and falling edges of STROBE. In an Ultra DMA/33 write cycle, this
signal is used as the DMARDY# signal which is negated by the drive to pause
Ultra DMA/33 transfers.  If the IDE signals are...

2-22Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionSDDREQI
SECONDARY DISK DMA REQUEST. This input signal is directly driven from
the IDE device DMARQ signal. It is asserted by the IDE device to request a data
transfer, and used in conjunction with the PCI bus master IDE function. It is not
associated with any AT compatible DMA channel.  If the IDE signals are
configured for Primary and Secondary, this signal is connected to the
corresponding signal on the Secondary IDE connector.  If...