Acer Travelmate 7100 Service Guide
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Major Chips Description2-3The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, refresh request, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for these three counters. PIIX4 provides an ISA-Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt controllers. The two interrupt...
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2-4Service GuideEnhanced Power Management PIIX4’s power management functions include enhanced clock control, local and global monitoring support for 14 individual devices, and various low-power (suspend) states, such as Power-On Suspend, Suspend-to-DRAM, and Suspend-to-Disk. A hardware-based thermal management circuit permits software-independent entrance to low-power states. PIIX4 has dedicated pins to monitor various external events (e.g., interfaces to a notebook lid, suspend/resume button, battery...
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Major Chips Description2-5· Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0 Specification and OS Directed Power Management · Integrated IDE Controller · Independent Timing of up to 4 Drives · PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec · Supports “Ultra DMA/33” Synchronous DMA Mode Transfers up to 33 Mbytes/sec · Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers · Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation · Enhanced DMA...
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2-6Service GuideThe 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI- to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA channel supports...
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Major Chips Description2-72.2.3 Block DiagramFigure 2-2PIIX4 Simplified Block Diagram
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2-8Service Guide2.2.4 Pin Descriptions This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid...
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Major Chips Description2-9Table 2-282371AB Pin DescriptionsNameTypeDescriptionPCI BUS INTERFACEAD[31:0]I/O
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical byte address (32
bits). During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction
consists of an address phase followed by one or more data phases. Little-endian
byte ordering is used. AD[7:0] define the least significant byte (LSB) and
AD[31:24] the...](http://img.usermanuals.tech/thumb/5/59850/w300_acer-travelmate-7100-service-guide-66.png "Page 67
Major Chips Description2-9Table 2-282371AB Pin DescriptionsNameTypeDescriptionPCI BUS INTERFACEAD[31:0]I/O
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical byte address (32
bits). During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction
consists of an address phase followed by one or more data phases. Little-endian
byte ordering is used. AD[7:0] define the least significant byte (LSB) and
AD[31:24] the...")
Major Chips Description2-9Table 2-282371AB Pin DescriptionsNameTypeDescriptionPCI BUS INTERFACEAD[31:0]I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction consists of an address phase followed by one or more data phases. Little-endian byte ordering is used. AD[7:0] define the least significant byte (LSB) and AD[31:24] the...
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2-10Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionIRDY#I/O
INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete
the current data phase of the transaction. It is used in conjunction with TRDY#.
A data phase is completed on any clock both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates PIIX4 has valid data present on
AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY# is an
input to PIIX4 when PIIX4 is the Target...](http://img.usermanuals.tech/thumb/5/59850/w300_acer-travelmate-7100-service-guide-67.png "Page 68
2-10Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionIRDY#I/O
INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete
the current data phase of the transaction. It is used in conjunction with TRDY#.
A data phase is completed on any clock both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates PIIX4 has valid data present on
AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY# is an
input to PIIX4 when PIIX4 is the Target...")
2-10Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionIRDY#I/O INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates PIIX4 has valid data present on AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY# is an input to PIIX4 when PIIX4 is the Target...
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Major Chips Description2-11Table 2-282371AB Pin DescriptionsNameTypeDescriptionTRDY#I/O
TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data
phase is completed when both TRDY# and IRDY# are sampled asserted. During
a read, TRDY# indicates that PIIX4, as a Target, has place valid data on
AD[31:0]. During a write, it indicates PIIX4, as a Target is prepared to latch data.
TRDY# is an input to PIIX4 when PIIX4 is...](http://img.usermanuals.tech/thumb/5/59850/w300_acer-travelmate-7100-service-guide-68.png "Page 69
Major Chips Description2-11Table 2-282371AB Pin DescriptionsNameTypeDescriptionTRDY#I/O
TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data
phase is completed when both TRDY# and IRDY# are sampled asserted. During
a read, TRDY# indicates that PIIX4, as a Target, has place valid data on
AD[31:0]. During a write, it indicates PIIX4, as a Target is prepared to latch data.
TRDY# is an input to PIIX4 when PIIX4 is...")
Major Chips Description2-11Table 2-282371AB Pin DescriptionsNameTypeDescriptionTRDY#I/O TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that PIIX4, as a Target, has place valid data on AD[31:0]. During a write, it indicates PIIX4, as a Target is prepared to latch data. TRDY# is an input to PIIX4 when PIIX4 is...
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2-12Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionIOW#I/O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4
owns the ISA Bus. IOW# is an input when an external ISA master owns the ISA
Bus.
During Reset: High-Z After Reset: High During POS: HighLA[23:17]/
GPO[7:1]I/O
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on
the ISA Bus up to 16 Mbytes. LA[23:17] are...](http://img.usermanuals.tech/thumb/5/59850/w300_acer-travelmate-7100-service-guide-69.png "Page 70
2-12Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionIOW#I/O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4
owns the ISA Bus. IOW# is an input when an external ISA master owns the ISA
Bus.
During Reset: High-Z After Reset: High During POS: HighLA[23:17]/
GPO[7:1]I/O
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on
the ISA Bus up to 16 Mbytes. LA[23:17] are...")
2-12Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionIOW#I/O I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns the ISA Bus. IOW# is an input when an external ISA master owns the ISA Bus. During Reset: High-Z After Reset: High During POS: HighLA[23:17]/ GPO[7:1]I/O ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes. LA[23:17] are...