Acer Extensa 390 Service Guide
Here you can view all the pages of manual Acer Extensa 390 Service Guide. The Acer manuals for Notebook are available online for free. You can easily download all the documents as PDF.
Page 71
Major Chips Description2-25 Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionKENJ/INVO Group ACache Enable Output. This signal is connected to the CPUs KENJ and INV pins. KENJ is used to notify the CPU whether the address of the current transaction is cacheable. INV is used during L1 snoop cycles. The M1531 drives this signal high (low) during the EADSJ assertion of a PCI master write (read) snoop cycle.SMIACTJI Group ASMM Interrupt Active. This signal is asserted by the CPU to inform the...
Page 72
![Page 72
2-26Service GuideTable 2-3M1531 Signal DescriptionsSignalTypeDescriptionCLKEN[1]/
GNTJ[4]O
Group CSDRAM Clock Enable Copy 1 or PCI Master Grant. This signal is used as
SDRAM clock enable copy 1 to do self refresh during suspend. It can also be
used as grant signal of the fifth PCI master. This function is controlled by
Index -5Dh bit 1.Secondary Cache Interface 3.3V/2.5V ToleranceCADVJO
Group ASynchronous SRAM Advance. This signal will make PBSRAM/Memory Cache
internal burst address counter...](http://img.usermanuals.tech/thumb/5/59713/w300_acer-extensa-390-service-guide-71.png "Page 72
2-26Service GuideTable 2-3M1531 Signal DescriptionsSignalTypeDescriptionCLKEN[1]/
GNTJ[4]O
Group CSDRAM Clock Enable Copy 1 or PCI Master Grant. This signal is used as
SDRAM clock enable copy 1 to do self refresh during suspend. It can also be
used as grant signal of the fifth PCI master. This function is controlled by
Index -5Dh bit 1.Secondary Cache Interface 3.3V/2.5V ToleranceCADVJO
Group ASynchronous SRAM Advance. This signal will make PBSRAM/Memory Cache
internal burst address counter...")
2-26Service GuideTable 2-3M1531 Signal DescriptionsSignalTypeDescriptionCLKEN[1]/ GNTJ[4]O Group CSDRAM Clock Enable Copy 1 or PCI Master Grant. This signal is used as SDRAM clock enable copy 1 to do self refresh during suspend. It can also be used as grant signal of the fifth PCI master. This function is controlled by Index -5Dh bit 1.Secondary Cache Interface 3.3V/2.5V ToleranceCADVJO Group ASynchronous SRAM Advance. This signal will make PBSRAM/Memory Cache internal burst address counter...
Page 73
Major Chips Description2-27 Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionDEVSELJI/O Group BDevice Select. When the target device has decoded the address as its own cycle, it will assert DEVSELJ.IRDYJI/O Group BInitiator Ready. This signal indicates the initiator is ready to complete the current data phase of transaction.TRDYJI/O Group BTarget Ready. This pin indicates the target is ready to complete the current data phase of transaction.STOPJI/O Group BStop. This signal indicates the target...
Page 74
2-28Service GuideTable 2-3M1531 Signal DescriptionsSignalTypeDescriptionPower PinsVCC_APVcc 3.3V or 2.5V Power for Group A. This power is used for CPU interface and L2 control signals. If this power connects to 3.3V, the relative signals will output 3.3V and accept 3.3V input. If this power connects to 2.5V, the relative signals will output 2.5V and accept 2.5V input.VCC_BPVcc 3.3V Power for Group B. This power is used for PCI interface and Tag signals. It must connect to 3.3V. The relative signals...
Page 75
Major Chips Description2-29 Table 2-4M1531 Numerical Pin...
Page 76
2-30Service GuideTable 2-4M1531 Numerical Pin...
Page 77
Major Chips Description2-31 Table 2-4M1531 Numerical Pin...
Page 78
2-32Service GuideTable 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeY10A3I/OB5AD7I/OB7CBEJ1I/OY11A28I/OA5AD8I/OC9CBEJ2I/OY12A26I/OD6AD9I/OC11CBEJ3I/OY13A27I/OC6AD10I/OU9CCSJOY14TIO3I/OB6AD11I/OT10COEJOY15TIO5I/OA6AD12I/OE1DCJIY16TIO7I/OE7AD13I/OB8DEVSELJI/OY17MA6OD7AD14I/OE3EADSJOY18MA9OC7AD15I/OD9FRAMEJI/OY19MA11OB9AD16I/OH10GNDPY20----A9AD17I/OH11GNDPA1...
Page 79
Major Chips Description2-33 Table 2-4M1531 Numerical Pin...
Page 80
2-34Service GuideTable 2-4M1531 Numerical Pin...