Acer Extensa 390 Service Guide
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Major Chips Description2-15 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCINTY04A10ICardBus interrupt. This signal is asserted low by a CardBus PC Card to request interrupt servicing from the host.CIRDYT02A16I/OCardBus initiator ready. CIRDY indicates the CardBus initiators ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of CCLK where both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states...
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2-16Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionSystem Interrupt TerminalsGPIO3/INTAV13I/OGPI03/lNTA Parallel PCI Interrupt. This terminal can be connected to an available PCI interrupt if parallel PCI interrupts are used, and the PCI1250A will output PCI INTA through this terminal. Refer to the Interrupt Subsystem description in this document for details on interrupt signaling. This terminal defaults to a general purpose inputIRQSER/INTBW13I/OIRQSER Serial Interrupt Signal /...
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Major Chips Description2-17 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCLOCKU12I/O3-Line Power Switch Clock. Information on the DATA line is sampled at the rising edge of CLOCK. This terminal defaults to an input, but can be changed to a PCI1250A output by using the P2CCLK bit in the I/O System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2MHz. If a system design defines this terminal an output, then this terminal requires an external pull-up resister....
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2-18Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPC/PCI DMA TerminalsPCREQ/ IRQMUX7Y12OPC/PCI DMA Request. This signal is used to request DMA transfers as DREQ in a system supporting the PC. PCI DMA scheme. IRQMUX7. When this terminal is configured for IRQMUX7, it provides the IRQMUX7 interrupt output of the interrupt mux, and can be mapped to any of 15 ISA type IRQs. The IRQMUX7 signal takes precedence over PCREQ, and should not be enabled in a system using PC/PCI DMA. This pin...
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Major Chips Description2-19 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionSPKROUTY10OSpeaker Output. This signal is the output to the host system that can carry the SPKR or CAUDIO signal through the PCI1250A from the PC Card interface. This signal is driven as the exclusive OR combination of card SPKR//CAUDIO inputs.
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2-20Service Guide2.2 Aladdin IV (M1531/M1533) The Aladdin-IV is the succeeding generation chipset of Aladdin-III from Acer Labs. It maintains the best system architecture (two-chip solution) to achieve the best system performance with the lowest system cost (TTL-free). The Aladdin-IV consists of two BGA chips to give the 586-class system a complete solution with most up-to-date features and architecture for multimedia/ multithreading OS and software applications. It utilizes the modern BGA package to...
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Major Chips Description2-21 2.2.1.1 Features · Supports all Intel/Cyrix/AMD/TI/IBM 586 processors. Host bus at 83.3, 75, 66, 60 and 50 MHz at 3.3V/2.5V · Supports Linear Wrap mode for Cyrix M1 and M2 · Write-Allocation feature for K6 · Pseudo-Synchronous PCI bus access (CPU bus: 75 MHz - PCI bus: 30 MHz, CPU bus: 83.3 MHz - PCI bus: 33 MHz) · Supports Pipelined-burst SRAM/Memory Cache · Direct mapped, 256 KB/512 KB/1 MB · Write-Back/Dynamic-Write-Back cache policy · Built-in 8K x 2 bit SRAM for MESI...
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2-22Service Guide· Supports the most flexible six 32-bit populated banks of DRAM for easy DRAM upgrade · Supports SIMM and DIMM · Synchronous/Pseudo Synchronous 25/30/33MHz 3.3V/5V tolerance PCI interface · Concurrent PCI architecture · PCI bus arbiter: five PCI masters and M1533/ M1543 (ISA Bridge) supported · 6 DWords for CPU-to-PCI memory write posted buffers · Converts back-to-back CPU to PCI memory write to PCI burst cycle · 38/22 Dwords for PCI-to-DRAM Write-posted/ Read-prefetching buffers ·...
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Major Chips Description2-23 2.2.1.2 Pin Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A NCPHLDAJAD3AD6AD8AD12PARTRDYJ AD17AD22 AD25AD30REQJ3 GNTJ2GNTJ3MPD2MPD0 MD61 MD29 MD62 B BEJ0PHLDJAD2AD5AD7AD11CBEJ1 DEVSELJ AD16AD21AD24AD29REQJ2 GNTJ1MPD5 MPD1 MD63 MD27 MD60 MD28 C BEJ3BEJ2BEJ1AD4 CBEJ0AD10AD15 STOPJCBEJ2 AD20CBEJ3AD28REQJ1 GNT0JMPD4 MD30 MD25MD58 MD26MD59 D BEJ6BEJ5BEJ4AD0AD1AD9AD14 LOCKJ FRAMEJAD19AD23 AD27REQJ0MPD7MPD3MD55MD23MD56 MD24MD57 E DCJHITMJEADSJBEJ7RSTJ...
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2-24Service Guide2.2.1.3 Signal Descriptions
Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionHost Interface 3.3V/2.5VA[31:3]I/O
Group AHost Address Bus Lines. A[31:3] have two functions. As inputs, along with
the byte enable signals, these pins serve as the address lines of the host
address bus which define the physical area of memory or I/O being accessed.
As outputs, the M1531 drives them during inquiry cycles on behalf of PCI
masters.BEJ[7:0]I
Group AByte Enables. These are the byte enable...](http://img.usermanuals.tech/thumb/5/59713/w300_acer-extensa-390-service-guide-69.png "Page 70
2-24Service Guide2.2.1.3 Signal Descriptions
Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionHost Interface 3.3V/2.5VA[31:3]I/O
Group AHost Address Bus Lines. A[31:3] have two functions. As inputs, along with
the byte enable signals, these pins serve as the address lines of the host
address bus which define the physical area of memory or I/O being accessed.
As outputs, the M1531 drives them during inquiry cycles on behalf of PCI
masters.BEJ[7:0]I
Group AByte Enables. These are the byte enable...")
2-24Service Guide2.2.1.3 Signal Descriptions Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionHost Interface 3.3V/2.5VA[31:3]I/O Group AHost Address Bus Lines. A[31:3] have two functions. As inputs, along with the byte enable signals, these pins serve as the address lines of the host address bus which define the physical area of memory or I/O being accessed. As outputs, the M1531 drives them during inquiry cycles on behalf of PCI masters.BEJ[7:0]I Group AByte Enables. These are the byte enable...