Acer Extensa 390 Service Guide

Major Chips Description2-65 2.4.4.3 Bottom View: BGA Ball AssignmentsFigure 2-865555 BGA Ball Assignments (Bottom View) 

2-66Service Guide2.4.4.4 Pin Functions
Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionPCI Bus InterfaceC1RST#InLowReset. This input sets all signals and registers in
the chip to a known slate. All outputs from the
chip are tri-stated or driven to an inactive state.
This pin is ignored during Standby mode
(STNDBY# pin low). The remainder of the
system (therefore the system bus) may be
powered down if desired (all bus output pins
are tri-stated in Standby mode).D2BCLKInHighBus Clock. This...

Major Chips Description2-67 Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionL4DEVSEL#S/TSLowDevice Select. Indicates the current target has
decoded its address as the target of the current
accessL2PERR#S/TSLowParity Error. This signal reports data parity errors
(except for Special Cycles where SERR# is
used). The PERR# pin is Sustained Tri-state. The
receiving agent will drive PERR# active two
clocks after detecting a data parity error PERR#
will be driven high for one clock before being...

2-68Service GuideTable 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionU2
T3
R4
T2
U1
R3
T1
R2
R1
P2
N3
P1
N2
M4
M3
N1
J1
J2
H1
J3
J4
H2
G1
H3
G3
F2
E1
F3
D1
E2
F4
E3AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31I/O
I/O
I/O
 I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OHigh
High
High
High
High
High
High
High
High
High
High...

Major Chips Description2-69 Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionDisplay Memory InterfaceD18
Cl9
B20
C18
A20
Bl9
Al9
B18
C17
D16AA0(CFG0)
AAI(CFG1)
AA2(CFG2)
AA3(CFG3)
AA4(CFG4)
AA5(CFG5)
AA6(CFG6)
AA7(CFG7)
AA8(CFG8)
AA9(CFG9)I/O
l/O
l/O
l/O
l/O
I/0
l/O
l/O
l/O
I/OBoth
Both
Both
Both
Both
Both
Both
Both
Both
BothDRAM address bus for Bank 0 and Bank
AA0 through AA9 also serve as configuration bits
CFG0 through CFG9. Please see the
descriptions for registers XR70 and XR71 for...

2-70Service GuideTable 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionJ18
J17
H19
G20
H18
G19
F20
G18
F19
D20
E19
F17
E18
D19MC0
MC1
MC2
MC3
MC4
MC5
MC6
MC7
MC8
MC11
MC12
MC13
MC14
MC15I/0
l/O
l/O
l/O
l/O
l/O
l/O
l/O
l/O
I/0
l/O
l/O
l/O
l/OHigh
High
High
High
High
High
High
High
High
High
High
High
High
HighDRAM data bits 32-47.R20
P19
N18
P20
N19
M17
M18
N20
M19
M20
L18
L19
L20
L17
K17
K20MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11(RMA16)
MD12(rma17)
MD13
MD14
MD15I/0
l/O
l/O
l/O
l/O
l/O...

Major Chips Description2-71 Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionFlat Panel Display InterfaceW6
V7
Y6
W7
V8
Y7
W8
U9
V9
Y8
W9
Y9
V10
W10
Y10
U10
U11
Y11
W11
V11
Y12
Y13
V12
U12
W13
Y14
V13
W14
Y15
V14
W15
Y16
V15
Y17
W16
U15P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out...

2-72Service GuideTable 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionNote:All signals listed above are powered by DVCC and GND. 

Major Chips Description2-73 Notes for table below:
· To accommodate a wide variety of panel types, the graphics controller has been designed to output its
data in any of a number of formats. These formats include different data widths for the colors belonging
to each pixel, and the ability to accommodate different pixel data transfer timing requirements.
· For STN-DD panels, pins PO through P35 are organized into groups corresponding to the upper and
lower parts of the panel. The names of the signals for...

2-74Service GuideTable 2-865555 Pin Functions (continued)BallPin NameTypeActiveDescriptionCRT InterfaceU3HYSNC(CSYNC)OutBothCRT Horizontal Sync (polarity is programmable) or
Composite Sync for support of various external
NTSC/PAL encoder chipsV2VSYNCOutBothCRT Vertical Sync (polarity is programmable)Y3
V4
W3RED
GREEN
BLUEOut
Out
OutAnalog
Analog
AnalogCRT analog video outputs from the internal color
palette DAC. The DAC is designed for a 37.5S2
equivalent load on each pin (e.g. 75Q resistor on
the board,...