Acer Extensa 390 Service Guide
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Major Chips Description2-5 2.1.3 Terminal Functions This section describes the PCI1250A terminal functions. The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc. for quick reference. The terminal numbers are also listed for convenient reference. Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPower Supply TerminalsGNDA01, D04, D08, D13, 17, H04, H17, N04, N17, U04, U08, U13, U17,IDevice ground terminalsVCCD06, D11, D15, F04, F17, 04,...
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2-6Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPCI Address and Data TerminalsAD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0K18 K19 L20 L18 L19 M20 M19 M18 N19 N18 P20 P19 R20 R19 P17 R18 V18 Y19 W18 V17 U16 Y18 W17 V16 W16 U14 Y16 W15 V14 Y15 W14 Y14PCI address data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the...
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Major Chips Description2-7 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPCI Interface Control TerminalsDEVSEV20I/OPCI device select. The PCI1250A asserts this signal to claim a PCI cycle as the target device. As a PCI initiator on the bus. the PCI1250A monitors this signal until a target responds. If no target responds before time-out occurs, then the PCI1250A will terminate the cycle with an initiator abort.FRAMET19I/OPCI cycle frame. This signal is driven by the initiator of a bus cycle....
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2-8Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionSTOPT17I/OPCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus tranaction. This signal is used for target disconnects and is commonly asserted by target devices which do not support burst data transfers.TRDYU20I/OPCI target ready. TRDY indicates the primary bus target s ability to complete the current data phase of the transaction. A data phase is completed upon a rising...
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Major Chips Description2-9 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0K03 J02 J04 H02 G01 W08 Y07 V07 J01 J03 H01 H03 G02 V08 W07 Y06E19 E20 G18 G19 H18 B07 C08 A08 G17 F19 F20 F19 H19 A07 B08 D09I/OCard Data. 16-bit PC Card data lines. D15 is the most significant16-Bit PC Card Interface Control Terminals (Slot A And Slot B)Slot A3 Slot B4BVD1 (STSCHG/RI)V06A09Battery Voltage Detect 1. Generated by 16-bitmemory PC Cards that include...
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2-10Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionBVD2 (SPKR)Y05D10IBattery Voltage Detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost....
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Major Chips Description2-11 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionIOWRM02C19OI/O Write IOWR is driven low by the PCI1250A to strobe write data into 16-bit l/O PC Cards during host l/O write cycles. DMA Read. This pin is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1250A asserts this signal during transfers from host memory to the PC Card.OEL03C20OOutput Enable. OE is driven low by the PCl1250A to enable 16-bit Memory PC Card data...
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2-12Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionWEP03D16OWrite enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also use for memory PC Cards that employ programmable memory technologies. DMA terminal count. This pin is used as TC during DMA operations to a 16-bit PC Card which supports DMA. The PC1031 asserts this signal to indicate terminal count for a DMA read operation.WP (IOIS16)U07B09IWrite protect. This signal applies to 16-bit memory PC...
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Major Chips Description2-13 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCRSSTW01C13I/OCardBus PC Card Reset. This signal is used to bring CardBus PC Card specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-statedt and the PCI1250A will drive these signals to a valid logic level. Assertion may be asynchronous to the CCLK. But deassertion must be synchronous to the CCLK.CCLKRUNU07B09OCardBus PC Card Clock Run. This signal...
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2-14Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCC/BE3 CC/BE2 CC/BE1 CC/BE0Y02 T03 N01 K01B12 D14 B19 D20I/OCardBus Bus Commands and Byte Enables. The command and byte enable signals are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3:0 defines the bus command. During the data phase, this four-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32- bit data bus carry meaningful data. CC/BE0...