Motorola Sse 5000 6881094c12 A Manual

							6881094C12-ANovember 11, 2004
Theory of Operation: VOCON Board2-19
21, and 22. Connections to the external accessory connector, which include serial communication 
data lines, external audio, and option select lines for controlling audio modes, are present at pins 1 
through 13. Switched battery voltage (B+SENSE) is provided on pin 32. Most of the pins at this 
connector have ESD protection devices and components. See Section 2.5.2.3.3: “Universal 
Connector Interface Circuitry” on page 2-29 for more details on this connection circuitry.
2.5.1.3  Internal Speaker and Microphone Flex Connector M102
The audio switching between the internal and accessory microphones is controlled via flex connector 
M102. See Section 2.5.2.2.1: “GCAP II IC U501” on page 2-24 for a discussion of this audio 
switching.
2.5.1.4  Control Top Flex Connector J707
The control top switches and side controls are connected through a flex circuit to the controller at 
J707. See Section 2.5.4: “Controls and Control Top Flex” on page 2-31 for a discussion of these 
controls.
2.5.1.5  Encryption Module Connector J701
This 40-pin connector provides the interface between the VOCON board and the encryption module. 
Two voltages are provided to the encryption board: UNSWB+ and SWB+. The SAP (Serial Audio 
Port) SSI lines, serial communication data lines, and general-purpose I/O lines from the dual-core 
processor are included in the interface to the encryption board. 
2.5.1.6  Display Module Connector J301
This 20-pin connector (J301) mates the VOCON board to the display module flex. The VOCON kits 
have a serial data interface to the display module. In this design, only 2.9 V is provided to the display 
module on pins 11 and 14. The display’s serial dataline (pin 18), serial clock line (pin 7), and chip 
select line (pin 3) are at 2.9V logic levels. See Section 2.5.3: “Display Module” on page 2-31 for 
details on the display module.
2.5.2 Functional Blocks
2.5.2.1  Controller and Memory
The controller and memory section contains the following components:
• Dual-core processor (U401), which acts as both the microcontroller unit (MCU) and the digital 
signal processor (DSP) for the radio 
• Static RAM (SRAM) IC (U403), a volatile device, which is used as working memory and shares 
the address and data bus with the Flash memory device
• Flash memory IC (U402), which contains host firmware, DSP firmware, and some codeplug 
data
2.5.2.1.1  Dual-Core Processor U401
The dual-core processor U401 contains a 32-bit microcontroller unit (MCU) and a 16-bit digital signal 
processor (DSP) in one IC package. It comes in a 256-pin, ball-grid array (BGA) package with 1mm 
pitch solder balls. Most of the pins on the dual-core processor operate from the 3 V supply. A 1.55 V 
supply is used for the core voltage and the clock amplifier module. The remaining pins of the 
processor use a 2.9 V supply. The External Interface Module (EIM) utilizes a 1.85 V supply.
There are also two system clocks provided to the dual-core processor.  
						

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2-20Theory of Operation: VOCON Board
Microcontroller Unit (MCU)
The MCU portion of the dual-core processor controls receive/transmit frequencies, power levels, 
display, and other radio functions, using either direct logic control or serial communications paths to 
the devices. The microcontrol unit executes a stored program located in the FLASH memory device. 
Data is transferred to and from memory by the microcontrol unit data bus. The memory location from 
which data is read, or to which data is written, is selected by the address lines. The microcontrol unit 
requires a 16.8 MHz clock and a 32.768 kHz clock. 
The MCU portion of the dual-core processor has 22.5k x 32 bits of internal RAM and 1k x 32 bits of 
internal ROM, which is used for the bootstrapping code. The MCU has several peripherals including 
an External Interface Module (EIM), the Multiple Queue Serial Peripheral Interface (MQSPI), two 
Universal Asynchronous Receiver/Transmitter (UART) modules, and the One-Wire Interface 
module. The MCU communicates internally to the DSP through the MCU/DSP Interface (MDI).
External Interface Module (EIM)
The External Interface Module (EIM) is the MCU interface to the SRAM U403 and Flash Memory 
U402. The EIM lines include 24 external address lines, 16 external bi-directional data lines, 6 chip 
selects lines, read/write line, and output enable line among others. All of the EIM lines operate at 1.8-
V logic levels, and the EIM operates at the MCU clock speed.
Multiple Queue Serial Peripheral Interface (MQSPI)
The Multiple Queue Serial Peripheral Interface (MQSPI) is the MCUs programming interface to other 
ICs. The dual-core processor has two independent SPI busses, and each has its own clock line (test 
points SCKA and SCKB), data-out line (test points MOSIA and MOSIB), and data-in line (test points 
MISOA and MISOB). There are 10 SPI chip selects (SPICS) that are programmable to either SPI A, 
the transceiver board SPI bus, or to SPI B, the dedicated VOCON SPI bus.
The devices on the SPI A bus include the PCIC and FracN IC on the SPICS4 (R131), the Abacus III 
IC on SPICS5 (R126), an analog-to-digital converter (ADC) on SPICS6 (R133), and the serial 
EEPROM on SPICS7 (R132). The two SPI B chip selects are for the GCAP II IC U501 on SPICS2 
(R539) and the digital-support IC U301 on SPICS3. All of the SPI module lines operate at GPIO 
voltage logic levels.
There are several devices on the transceiver board that only have one bi-directional SPI data line. 
Components U404, U405, and U406 are configurable by MCU GPIO pin TOUT13 (MISOA_SEL) to 
route the data line to the appropriate pin on the dual-core processor depending on which SPI device 
is being accessed.
Universal Asynchronous Receiver/Transmitter (UART)
The dual-core processor has two Universal Asynchronous Receiver/Transmitter (UART) modules. 
UART1 handles the RS232 lines while UART 2 is connected to the SB9600 lines. Each UART has a 
receive data line (URXD), a transmit data line (UTXD), and hardware flow control signals (RTS–
request to send) and (CTS–clear to send). All UART lines operate at GPIO voltage logic levels. The 
translation to 5 V logic levels for the accessory side connector is discussed in Section 2.5.2.3.1: 
“Digital-Support IC U301” on page 2-26.
One-Wire Interface
The MCU has a One-Wire Interface module that is used to communicate to a One-Wire device like a 
USB cable or a smart battery using the Dallas Semiconductor protocol. This module uses a GPIO 
voltage logic level. 
						

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Theory of Operation: VOCON Board2-21
Digital Signal Processor (DSP)
The DSP portion of the dual-core processor performs signaling and voice encoding and decoding, as 
well as audio filtering and volume control. The DSP performs Private-Line/Digital Private-Line (PL/
DPL) encode and alert-tone generation. The DSP transmits pre-emphasis on analog signals, and 
applies a low-pass (splatter) filter to all transmitted signals. The DSP controls squelch, deviation, and 
executes receiver and transmitter filtering. The DSP executes a stored program located in the 
FLASH memory device.
The DSP requires a 16.8 MHz clock. The DSP uses the 16.8 MHz clock to generate a 256 kHz clock 
and an 8 kHz frame synchronization signal that is supplied to the CODEC. Additionally, the DSP 
requires clock and frame synchronization from the Abacus III digital back-end IC on the transceiver 
board to generate another clock and frame synchronization signal, and these signals are supplied to 
transmit DAC on the transceiver board.
The DSP has 84k x 24 bits of program RAM and 62k x 16 bits of data RAM. It has its own set of 
peripherals including the Baseband Interface Port (BBP), the DSP Timer module, and the Serial 
Audio CODEC Port (SAP). Additionally, the DSP shares some peripherals with the MCU, including 
the USB interface and the General Purpose Input/Output module (GPIO).
Baseband Interface Port (BBP)
The Baseband Interface Port (BBP) module is the DSP’s serial synchronous interface (SSI) to the 
transceiver board. The BBP has independent sections for the receiver and the transmitter. The 
receiver BBP pins include the receive data pin SRDB (U703 pin 4), the receive clock signal pin SC0B 
(U705 pin 4), and the receive frame synchronization (sync) signal pin SC1B (U704 pin 4). The 
transmitters BBP pins include the transmit data pin STDB (R717), the transmit clock signal pin 
SCKB (R715), and the transmit frame sync signal pin SC2B (R711). All BBP lines use GPIO voltage 
logic levels.
DSP Timer Module
While the BBP receive clock and frame sync signals are supplied by the Abacus III IC from the 
transceiver board, the BBP transmit clock and frame sync signals are generated by the DSP Timer. 
The BBP receive clock, connected to the DSP Timer input pin T10, is reference used to generate the 
BBP transmit clock and frame sync signals. These two signals, along with the BBP transmit data 
signal, are connected to the DAC on the transceiver board.
Serial Audio CODEC Port (SAP)
The Serial Audio CODEC Port (SAP) module is the DSP’s serial synchronous interface (SSI) to the 
audio CODEC on the GCAP II IC. The SAP also interfaces with the encryption module.
The SAP interface consists of four signals including the SAP clock line pin SCKA (component R405), 
the SAP frame sync line pin SC2A (component R406), the SAP receive data line pin SRDA 
(component R402), and the transmit data line pin STDA (component R403). 
The SAP clock is generated by the dual-core processor U401, and is a 256 kHz, 2.9 V peak-to-peak 
square wave. The SAP frame sync signal is generated by the dual-core processor U401, and is an 8 
kHz, 2.9 V peak-to-peak square wave.
Universal Serial Bus (USB)
The dual-core processor USB peripheral, shared by the MCU and the DSP, provides the required 
buffering and protocol to communicate on the Universal Serial Bus. The dual-core processor 
supports USB slave functionality.
The receive data path is routed from the discrete USB receiver (U302 pin 8) and is buffered by U308. 
Single-ended positive data is generated at U302 pin 3 and is sent to the dual-core processor pin 
URXD_RTS.  
						

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2-22Theory of Operation: VOCON Board
USB data minus comes from U302 pin 4 and this signal is sent to URXD1 of the dual-core processor.
General-Purpose Input/Output (GPIO) Module
The General-Purpose Input/Output (GPIO) module is shared by the MCU and the DSP. This module 
consists of four 16-pin bi-directional ports and a 15 pin bi-directional port. While some of the pins on 
these ports are being used for other functions (UART, SPI, SAP, BBP, and Interrupt pins), the 
remaining pins can be programmed to become GPIOs that can be used by either the DSP or the 
MCU. Each GPIO pin has up to 8 alternate output functions and up to 4 alternate input functions.
This allows for the GPIO pins to be routed internally to pertinent dual-core processor modules. 
Additionally, the GPIO module adds selectable edge-triggered or level-sensitive interrupt 
functionality to the GPIO pins. Some examples of GPIO pins include the Audio PA control signals 
(EXT_SPKR_SEL, AUDIO_PA_EN, and AUDIO_MODE_SEL), the EEPOT control signals 
(EEPOT_INC*, EEPOT_U_D*, EEPOT_CS*, and EEPOT_CS_EXT*), and the LED control signals 
(RED_LED and GREEN_LED).
System Clocks
Two main clocks are provided to the dual-core processor. The first clock, a 16.8 MHz sine wave, 
comes from the RF interface connector P201 pin 7. This is the most important clock, since it is used 
internally to generate the clocks for both the MCU and DSP cores, as well as most of the peripherals. 
It is conditioned by the clock buffer circuit, which includes Q601, R603, R605, R615, L601, C606, 
C609, R608, and C607. The output of this buffer (C452) goes to the dual-core processor CKIH pin, 
as well as to the digital-support IC REF_16_IN.
The other clock supplied to the dual-core processor is a 3 V peak-to-peak 32.768 kHz square wave 
(32 kHz test point). It is generated by the digital-support IC U301 internal oscillator and an external 
32.768 kHz crystal Y301, and is supplied to the CKIL pin on the dual-core processor. While not as 
widely used as the 16.8 MHz clock, the 32.768 kHz clock is needed by some components in the 
dual-core processor, including the reset circuitry.
2.5.2.1.2  Static RAM (SRAM) U403
The static RAM (SRAM) IC U403 is an asynchronous, 1 MB, CMOS device that is capable of 70 ns 
access speed. It is supplied with 1.8 volts. The SRAM has its 19 address lines and 16 data lines 
connected to the EIM of the dual-core processor through the Address(23:0) and Data(15:0) busses.
The SRAM has an active-high chip select CS2 that is tied directly to the 1.8 V supply and an active 
low chip select CS1 that is connected to the EIM CS2_N pin (test point CS2). When the SRAM CS1 
pin is not asserted, the SRAM is in standby mode, which reduces current consumption.
Two other control signals from the EIM that change the mode of the SRAM are the read/write signal, 
R/W, and the output enable signal, OE. The R/W of the EIM is connected to the SRAM EN_WE pin 
(test point R_W), while the OE signal from the EIM is connected to the SRAM EN_OE pin. The 
SRAM is in read mode when the EN_WE pin is not asserted and the EN_OE pin is asserted. The 
SRAM is in write mode when the EN_WE pin is asserted, regardless of the state of the EN_OE pin.
The other SRAM pins are the lower-byte enable pin LB and the upper-byte enable pin UB. These 
pins are used to determine which byte (LB controls data lines 0-7 and UB controls data lines 8-15) is 
being used when there is a read or a write request from the dual-core processor. The LB pin is 
controlled by the EIM EB1_N signal, while the UP pin is controlled by the EB0_N signal.
2.5.2.1.3  FLASH Memory U402
The Flash memory IC is an 8 MB CMOS device with simultaneous read/write or simultaneous read/ 
erase operation capabilities with 70 ns access speed. It is supplied with 1.8 volts. The Flash memory 
has its 22 address lines and 16 data lines connected to the EIM of the dual-core processor through  
						

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Theory of Operation: VOCON Board2-23
the Address(23:0) and Data(15:0) busses. The Flash memory contains host firmware, DSP firmware, 
and codeplug data with the exception of the tuning values that reside on the transceiver board’s 
serial EEPROM. The Flash memory IC is not field repairable.
The RESET_OUT of the dual-core processor is at a GPIO voltage logic level. Components D401 and 
R401 are used to convert the voltage down to a 1.8 V logic level, and this 1.8 V reset signal is fed to 
the Flash RESET pin. When this pin is asserted (active low logic), the Flash is in reset mode. In this 
mode, the internal circuitry powers down, and the outputs become high-impedance connections.
The Flash active-low chip select pin, EN_CE, is connected to the active-low CS0_N pin (CS0 test 
point) of the EIM. When the EN_CE is not asserted, the Flash is in standby mode, which reduces 
current consumption.
Several other active-low control pins determine what mode the Flash memory is in: the address valid 
pin ADV that is connected to the EIM LBA_N signal, the output enable pin EN_OE that is connected 
to the EIM OE_N signal, and the write enable pin EN_WE that is connected to the EIM EB1_N 
signal. For read mode, the ADV and EN_OE pins are asserted while the EN_WE pin is not asserted. 
When the EN_WE is asserted and the EN_OE pin is unasserted, the Flash operates in the write 
mode.
Figure 2-8 illustrates the EIM and memory ICs block diagram.
 
Figure 2-8.  Dual-Core Processor EIM and Memory Block Diagram
2.5.2.2  Audio and Power
The audio and power section contains the following components:
• GCAP II IC U501
• 5 V regulator U505
• 1.55 V regulator 
• Audio pre-amplifier U502
• Audio power amplifier (PA) U503
• EEPOT U509
Dual-Core
Processor
U401Flash
U402
SRAM
U403
RESET_OUT
LBA_N
CS0_N
EB1_N
OE_N
A(23:0)
D(15:0)
EB0_N
CS2_N
RW_NVoltage
TranslatorRESET
ADV
EN_CE
EN_WE
EN_OE
A(22:0)
D(15:0)
A(18:0)
D(15:0)
EN_OE
LB
UB
CS1
EN_WE
CSO
A(23:1)
A(19:1)
CS2
R_W
MAEPF-27414-A 
						

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2-24Theory of Operation: VOCON Board
The audio and power supply IC (GCAP II IC) has many functions. It supplies most of the voltages 
used on the VOCON board, while external linear regulators supply 5 Vdc and 1.55 Vdc. It also has 
microphone audio amplifiers, switching between internal and accessory microphones, multiplexing 
capability for receive and transmit audio, filtering, voltage regulators, a real-time clock (RTC), and the 
audio CODEC. The audio CODEC performs analog-to-digital and digital-to-analog conversions on 
audio signals. The GCAP IC also has an analog/digital converter (ADC), which is used to monitor 
volume setting and battery voltage. The GCAP II IC is programmed by the dual-core processor.
The audio pre-amplifier and the audio PA condition the received audio signal from the analog output 
of the CODEC from the GCAP IC before the audio is routed to the speaker. The dual EEPOT sets 
the gain of the microphone signal. The audio PA is sourced from the battery, and both of these 
devices are programmed by the dual-core processor.
2.5.2.2.1  GCAP II IC U501
The GCAP II IC is a mixed-signal (analog and digital) IC that provides control, audio, and voltage 
regulation functionality. It comes in a 100-pin, ball-grid array (BGA) package with 0.8 mm pitch solder 
balls. The GCAP II IC is supplied with switched battery voltage GCAP_B+ (R581).
Voltage Regulation
The GCAP II IC contains several voltage regulators that are used in the design of the VOCON board: 
VSW1, VSW2, and V2. The VSW1 regulator is a programmable switching regulator that uses the 
switched battery voltage as its input on pin PSRC1. The output voltage of VSW1 (R502) is 
programmable by the dual-core processor U401 through the SPI bus. The initial output of VSW1 is 
3.2 volts, which is then programmed to 3.8 volts. The VSW1 voltage is supplied to the RF Interface 
connector P201 pin 15 and to the input pins of the VSW2 and V2 regulators.
The VSW2 regulator is a SPI programmable switching regulator that uses VSW1 as its input on pin 
PSRC2. The initial output of VSW2 (R501) is 2.2 volts, which is then programmed to 1.875 volts 
(referred to as 1.8 volts throughout this document). The VSW2 voltage is supplied to the dual-core 
processor (core voltage and the EIM voltage), the SRAM U403, the Flash memory U402, and the 
display module connector J301 
The V2 regulator is a SPI programmable linear regulator that uses VSW1 as its input on pin VIN2. 
The initial output of V2 (R560) is 2.775 volts, which is then programmed to 2.9 volts. The V2 voltage 
is supplied to the dual-core processor (I/O ring - SPI, BBP, SAP, UART, GPIO, etc.), the digital-
support IC U301, the EEPOT U509, the display module connector J301, and the many discrete 
components that interface with the dual-core processor and the digital-support IC.
MCU Interface
The GCAP II IC has a four-wire, SPI connection to the dual-core processor (SPI B). The SPI B clock 
is connected to the SPI_CLK pin (test point SCKB). The SPI B MOSI line is connected to the 
SPI_DW pin (test point MOSIB). The SPI B MISO line is connected to the SPI_DR pin (test point 
MISOB). The GCAP SPI B chip-select signal is connected to the CE pin (R539). Through this 
interface, the dual-core processor can program the voltage regulators, the CODEC, the transmit and 
receive audio filters and amplifiers, as well as read information from the ADC and the real-time clock.
The GCAP II IC has an 8-bit ADC with general-purpose six channels and four voltage-monitoring 
channels. The six general-purpose analog-to-digital (A/D) channels are assigned to the display 
backlight button on the control head (AD0), the monitor volume (AD5); the two-position toggle switch 
(AD1); the OPT_SEL_IN  (AD2) (for determining accessory attachment), VOCON board ID (AD3), 
and RF board ID (AD4). Battery voltage is also monitored by the ADC. The dual-core processor 
activates and reads the A/D values through the SPI bus. 
						

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Theory of Operation: VOCON Board2-25
Audio Circuitry
A 13-bit CODEC, internal to the GCAP II IC and programmable by the dual-core processor through 
the SPI bus, converts microphone audio into a digital bit stream for processing by the DSP. The 
CODEC also converts receive audio data that was processed by the DSP into an analog audio signal 
for amplification to a speaker. The CODEC interfaces to the DSP through the 4-wire SAP bus. The 
CODEC clock, which is 256 kHz and is supplied to the DCLK pin. The CODEC 8 kHz CODEC frame 
synchronization signal is supplied to the FSYNC pin. The CODEC transmit data signal is on the TX 
pin, while the CODEC receive data signal is on the RX pin. For the CODEC to operate with those 
clock and frame sync signals, a 13 MHz clock (R302), generated by the digital-support IC, is 
supplied to the GCAP CLK_IN pin.
The GCAP II IC contains internal amplification, filtering, and multiplexing functionality for both 
receive and transmit audio. These functions are dual-core processor-programmable through the SPI 
bus. The input for the internal microphone audio (R540) is the MICIN_NEG pin, while the input for 
the external microphone audio (R566) is the AUX_MIC_NEG pin. The output for the speaker audio is 
the EXTOUT pin (C533).
2.5.2.2.2  5 V Regulator U505
The 5 V regulator uses UNSW_B+ as its input voltage. The digital-support IC WDI line controls the 
regulator’s SHUTDOWN pin. The 5 V supply (R503) is used by the digital-support IC U301, audio 
preamplifier U502, microphone bias circuitry (R531 and R563), digital-support IC protection diodes, 
bi-directional voltage translators, battery data-line isolation circuitry, and ESD protection circuitry.
2.5.2.2.3  1.55 V Regulator
The 1.55 V regulator is made up of the following components: R600, Q600, U600, C601, C600, 
R601, R602, R617, C605, C603, and C604. This circuit uses VSW1 to bias the regulator while 
VSW2 sources the current. This voltage is used by the dual-core processor U401 for its core voltage 
and clock amplifier.
2.5.2.2.4  Audio Pre-Amplifier U502
The audio pre-amplifier U502 is a single-package, 5-pin, op-amp supplied with 5 volts. This pre-amp 
is an active low-pass filter and provides a fixed gain, which is selected by the components R551 and 
R537. The input (U502 pin 4) of stage is the EXTOUT pin from the GCAP II IC, while the output 
(U502 pin 1) of this stage goes to the audio PA.
2.5.2.2.5  Audio Power Amplifier U503
The audio PA U503 consists of two BTL amplifiers, complementary outputs, and control logic. Each 
of the amplifiers has a fixed gain—the external audio PA gain is set by components R553 and R554, 
while the internal audio PA gain is set by components R549 and R550.
The MODE pin (U503 pin 4) voltage determines the operation of the amplifier. That voltage is 
controlled by the dual-core processor GPIO lines AUDIO_PA_EN (to Q505) and 
AUDIO_MODE_SEL (to Q506). Table 2-9 describes how the dual-core processor GPIO lines 
configure the audio PA.
The SELECT pin (U503 pin 6) is used to switch the audio path between internal and external 
speaker. The voltage on that pin is determined by the EXT_SPKR_SEL line from the dual-core 
processor and the Q505 transistor. When the voltage at the SELECT pin is high (B+), the audio is 
routed to the internal speaker lines. When the voltage at the SELECT pin is low (V_select < 0.5V), 
the audio is routed to the external speaker lines. 
						

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2-26Theory of Operation: VOCON Board
2.5.2.2.6  EEPOT U509
The EEPOT is a digitally programmable potentiometer with 256 taps and a total resistance of 50 
Kohms. This 10-pin package contains two independent potentiometers, one for each microphone 
line. The EEPOT resistance values are programmed by the dual-core processor GPIOs 
EEPOT_INC* (U509 pin 9) and EEPOT_U_D* (U509 pin 2). The EEPOT_INC* signal increments the 
resistance value up or down, which depends on the EEPOT_U_D* signal. The EEPOT_CS* line 
(U509 pin 10) is asserted when the internal microphone gain is being changed. Similarly, the 
EEPOT_CS_EST* (U509 pin 1) is asserted for external microphone gain changes. The EEPOT is 
supplied with voltage from the GCAP II V2 regulator.
2.5.2.3  Interface Support
The interface support section consists of the following:
• Digital-support IC U301
• ESD protection circuitry
• Universal connector interface circuitry
The digital-support IC contains a USB transceiver, switching logic between RS232 and boot data 
path, One- Wire side connector support, and several clock generators. The digital-support IC is 
programmed by the dual-core processor.
ESD protection devices include zener diodes and low-capacitance ESD suppressors.
Side connector interface circuitry includes current-limiting resistors and noise-suppressing shunt 
capacitors.
2.5.2.3.1  Digital-Support IC U301
NOTE:See Figure 12-14. NCN6186_ VOCON Flipper Circuit on page 12-20.
The digital-support IC U301 is an application-specific integrated circuit (ASIC) device designed for 
the SSE 5000. It is contained in a 64-pin µBGA package with 0.8 mm pitch solder balls. The digital-
support IC is supplied with 5 V and the processor’s GPIO voltage. It is supplied with a 16.8 MHz 
clock from the transceiver board. Using this clock, the digital-support IC generates a 13 MHz clock 
for the GCAP II IC. Additionally, the digital-support IC uses a crystal to generate the 32 kHz clock 
used by the dual-core processor and GCAP II IC.
The digital-support IC supports many functions, including the radio’s universal (accessory) side 
connector interface, One-Wire option detect support, watchdog timer, and 32 kHz oscillator with 
CMOS output. It also monitors the position of the on/off switch and controls the shutdown of the 
regulators on the GCAP II IC. 
The digital-support IC is programmable by the dual-core processor through the SPI bus. Table 2-9.  Audio PA Status
AUDIO_PA_ENAUDIO_MODE_SELAudio PA StatusMODE Voltage
0 0 Standby V_Mode > 7 V
0 1 Mute 1.5 V < V_Mode < 6 V
1 0 On V_Mode < 0.5 V
1 1 On V_Mode < 0.5 V 
						

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Theory of Operation: VOCON Board2-27
Side Connector Interface, Logic Level Translation, and Boot Data Path Control
The digital-support IC facilitates the interface to the radios side connector. Some of the side 
connector lines are at 5 V logic levels, so the digital-support IC converts those lines to GPIO voltage 
logic levels to interface to the dual-core processor. These lines include the SB9600 bus busy line 
LH_BUSY (R242), and the RS 232 CTS (R245).The SB9600 data line uses an external, bi-direc 
tional, voltage translation circuit that includes Q304, D302, R328, R329, R330, U303, and C314.
USB Transceiver
The USB transceiver, U302, is capable of transmitting and receiving serial data at a rate of 12 
megabits per second. The differential USB data comes from the side connector, through the 33-ohm 
resistors R252 and R253 and the isolation switch Q301, and then to the VP and VM pins on U302. 
The USB receive interface from the digital-support IC to the dual-core processor is as follows: VP 
routed to PA2_USB_VPIN VM, routed to USB_VMI_RXD, and the differential decoded data is output 
at the RCV pin and goes to the dual-core processor URTS1 pin.
The USB transmitter is enabled when the SUSPND and OE_EN signals are both driven low by the 
dual-core processor. The single-ended data is output from the dual-core processor on the UTXD1 
pin and goes to  VO_VPO on U302. The data is driven out differentially on the DPOS  and DNEG 
pins, which go to the side connector. The dual-core processor sends the single-ended zero signal 
from pin PC0_USB_VMOUT to the FSE0_VMO pin on U302. 
When a USB cable is detected, Q302 pin 2 goes high. This controls the isolation switch Q301 so that 
the data that is on those lines are routed to the USB transceiver. If a USB cable is not detected, the 
Q302 pin is low and the USB transceiver is isolated. This isolation is done primarily because the 
RS232 data lines are 5 V lines, so the switch protects the transceiver since it operates at a lower 
voltage, and the USB data lines to the side connector also act as the RS232 lines.
On the VOCON board, the USB transceiver on the digital-support IC is not used. Instead, a discrete 
USB transceiver U310 is used. The transceiver is provided with 5 V and 2.9 V. The 5 V powers an 
internal 3.3 V voltage regulator on the transceiver, which is used as the voltage for the USB data pins 
D+ and D- as well as the VPU pin. The 2.9 V is used by the remaining pins as they interface to the 
dual-core processor U401.
One-Wire Support
New options and accessories that attach to the side connector are identified by the dual-core 
processor using the One-Wire protocol. The One-Wire pin on the side connector serves as the One-
Wire data pin. This signal is connected to the ONE_WIRE_OPT pin. This pin is connected to the 
dual-core processor One-Wire bus ONE_WIRE_UP through an internal isolation switch controlled by 
a dual-core processor GPIO line to the digital-support IC ONE_WIRE_EN_X pin. This isolation is 
needed to prevent possible contention on the One-Wire bus when a smart battery is attached to the 
radio.
These new accessories are to ground, CTS (TP208), of the side connector. When this occurs, the 
digital-support IC pin KVL_USB_DET_X is asserted and the dual-core processor detects the 
change. The dual-core processor then asserts the ONE_WIRE_EN_X pin on the digital-support IC to 
connect the side connector One-Wire line to the dual-core processor One-Wire bus. In the case of 
the USB cable, the dual-core processor reads the One-Wire data from the cable and, upon 
determining that a USB cable is attached, programs the digital-support IC for USB mode. 
						

							November 11, 20046881094C12-A
2-28Theory of Operation: VOCON Board
Watchdog Timer
The digital-support IC monitors the position of the radio’s On/Off switch on the BP_SEN_X pin, and 
that signal is located on Q508 pin 3. If the voltage on pin 3 is ground, then the radio is turned on. If 
the voltage on pin 3 is 3 volts, then the radio is off. When the radio is turned off, a counter inside the 
digital-support IC begins incrementing. That counter can be refreshed by the dual-core processor 
through the SPI bus.
This is done so that the software has enough time to complete its tasks before the power is taken 
away from the dual-core processor. If the counter is not refreshed by the time the count is complete, 
the digital-support IC pin WD_OUT goes low, which shuts down the GCAP II voltage regulators. 
During normal radio operation, WD_OUT should be high (V2 regulated voltage).
32 kHz Oscillator and CMOS Output
The 32 kHz oscillator circuitry uses a separate voltage supply pin (VDD3_XTL) than the other 3-V
portions of the digital-support IC. The oscillator circuitry is internal to the digital-support IC, and the 
32.768 kHz crystal Y301 and additional load capacitors C308 and C309 are located next to the IC.
The output of the 32 kHz oscillator is an LI_CELL voltage (approximately 3 volts peak-to-peak), 
32.768 kHz square wave on pin REF32_OUT. This clock goes to two destinations: the dual-core 
processor CKIL pin (32 kHz test point) as a square wave and the GCAP II IC XTAL1 pin (C306) as a 
sine wave.
Components C306 and C313 are used to filter the square wave into a sine wave before the signal 
goes to the GCAP II IC.
13 MHz Reference Generation for GCAP II IC
The 13 MHz reference is required by the GCAP II IC for the CODEC time base and the SSI clock
generator module internal to the digital-support IC. A phase locked loop (PLL) is used to generate 
the 13 MHz using the 16.8 MHz clock, which is provided to the digital-support IC REF_16_IN pin 
(C307). An external RC loop filter network, consisting of R301, C301, and C302, is connected to the 
PLL_LFT pin.
The 13 MHz reference output pin, REF_13_OUT, is conditioned by the RC network of R302 and 
C303. The signal at REF_13_OUT is a 3-V peak-to-peak square wave, and the RC filter produces a 
lower-level triangle wave that is suitable for the GCAP II IC.
The 13 MHz reference is disabled as the digital-support IC powers up. The 13 MHz reference is 
enabled by the dual-core processor through the SPI bus, and, during normal radio operation, this 
signal should be present.