Motorola Sse 5000 6881094c12 A Manual

							6881094C12-ANovember 11, 2004
Theory of Operation: Transceiver Board2-9
2.4.1.5  Power Conditioning Components
DC power-conditioning components include zener diodes, capacitors, ferrite beads, a power 
inductor, and the fuse. Diodes VR1 and VR2 provide over-voltage protection. Ferrite beads 
(designated E1, E4, E101) and capacitors suppress electromagnetic interference from the 
transceiver. The power-line filter consisting of L1, C13, and C14 suppresses digital noise from the 
VOCON board switching power supplies that could degrade the transmitter spectral purity.
Pass transistor Q1 switches the battery voltage to the transceiver when control signal SWB+ or SB+ 
from the VOCON board is asserted high. This increases the transceiver’s immunity to conducted 
interference that might be present on SWB+ or SB+, such as from switching voltage regulators on 
the VOCON board.
Ground clip G9 makes contact between the transceiver board ground and the radio chassis. The 
chassis connection is a necessary electrical reference point to complete the antenna circuit path. 
Shields SH201 through SH702 and the tool hole appear on the schematic to show their connection 
to ground.
2.4.2 Receiver
The SSE 5000 transceiver has a dual-conversion superheterodyne receiver. Figure 2-2 illustrates 
the major receiver components:
• Receiver front-end
• Receiver back-end
2.4.2.1  Receiver Front-End
NOTE:Refer to Figure 2-2 for the receiver block diagram, Table 2-7 for local oscillator (LO) and first 
IF information, and Figure 12-2 for the receiver front-end schematic.
The receiver front-end tunes to the desired channel and down converts the RF signal to the first 
intermediate frequency (IF). Channel selection is by way of a tunable local oscillator, RXLO, from the 
FGU.
The receiver front-end consists of a preselector filter, an RF amplifier, a second preselector, mixer, 
and an IF crystal filter. The SSE 5000 radio also contains a switchable attenuator between the 
antenna switch and the first preselector filter. The RF amplifier is a discrete RF transistor with 
associated circuitry. The mixer is a double-balanced, active mixer IC, coupled by transformers. The 
receiver (RX) local oscillator (LO) is provided by the FGU.
2.4.2.1.1  Preselector Filters
The receiver front-end uses two discrete bandpass filters to achieve its required out-of-band 
rejection. The first preselector filter precedes the RF amplifier, while the second preselector filter 
follows the RF amplifier. Table 2-7.  Local Oscillator and First IF Frequencies
UHF Range 2 
(450–488 MHz)
LO Frequency Range 376.65–414.65 MHz
First IF Frequency 73.35 MHz 
						

							November 11, 20046881094C12-A
2-10Theory of Operation: Transceiver Board
2.4.2.1.2  LNA (Low-Noise Amplifier)
The SSE 5000 radio uses a discrete transistor for the low-noise amplifier (Q430). A feedback 
network between the collector and base improves stability and gain balance across the frequency 
band. Input and output LC networks match the LNA impedance to 50 ohms.
A diode limiter (D400) protects the amplifier damage by strong input signals.
2.4.2.1.3  Mixer
The mixer (U470) down-converts the received RF to the first intermediate frequency (IF). The IF is 
73.35 MHz. Low-side LO injection is used. Transformers are used as baluns to convert signals from 
single-ended to balanced at pins MI, MIX, LO, and LOX. An output transformer converts the 
balanced signal at pins MO and MOX to a single-ended output.
2.4.2.1.4  IF Filter
The IF filter (FL400) is a leadless, surface-mount, 3-pole, quartz crystal filter. This narrow bandpass 
filter gives the radio its adjacent-channel and alternate-channel rejection performance.
Input and output LC networks match the filter impedance to 50 ohms. 
2.4.2.2  Receiver Back-End
NOTE:Refer to Figure 2-2 for the receiver block diagram and Figure 12-3 for the receiver back-end 
schematic.
The receiver back-end, which consists of the Abacus III (AD9874 IF digitizing subsystem) IC and its 
associated circuitry, processes the down-converted IF signal to produce digital data for final 
processing by the VOCON DSP.
2.4.2.2.1  Abacus III IC U500
The AD9874 is a general-purpose, IF subsystem that digitizes a low-level 10–300 MHz IF input with 
a bandwidth up to 270 kHz. The output of the Abacus III IC is SSI data to the VOCON.
The signal chain of the AD9874 consists of a low-noise amplifier, a mixer, a bandpass sigma-delta 
A/D converter, and a decimation filter with programmable decimation factor. An automatic gain 
control (AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment. The high 
dynamic range and inherent anti-aliasing provided by the bandpass sigma-delta converter allow the 
AD9874 to cope with blocking signals 80 dB stronger than the desired signal.
Auxiliary blocks include frequency synthesizers for the second LO and sampling clock LO, as well as 
an SPI port. The second LO uses a discrete external loop filter and VCO. The clock oscillator has an 
external loop filter and resonator. 
						

							6881094C12-ANovember 11, 2004
Theory of Operation: Transceiver Board2-11
Figure 2-5.  Abacus III (AD9874) Functional Block Diagram
Input signal RXIF is 73.35 MHz IF from crystal filter FL400 in the receiver front-end. Components 
L547 and C542 match the input impedance to 50 ohms.  Formatted SSI data is output to the VOCON 
board on ports FS, DOUTA, and CLKOUT.
2.4.2.2.2  Second Local Oscillator
The second LO is controlled by the Abacus LO synthesizer, which mixes with IFIN to produce a 2.25 
MHz final IF. The external VCO consists of Q502 and its bias network and frequency-determining 
elements. Signal FREF is the 16.8 MHz reference from the FGU. Darlington transistor Q501 with 
C550 and R501 form an active power-line filter.
The second LO frequency is 71.1 MHz by default or 75.6 MHz in special cases as needed to avoid 
radio self-quieters. The loop filter is composed of R551, C558, C559, R552, and C512.
2.4.2.2.3  Sampling Clock Oscillator
The Abacus sampling clock synthesizer operates at 18 MHz = 8 x 2.25 MHz. The VCO uses an 
internal transistor and external resonator. The resonator is composed of L503, C535, C929, and 
D501.
The loop filter is composed of R512, C536, R514, C570, and C571.
2.4.3 Transmitter
NOTE:Refer to Figure 2-6 for the transmitter block diagram and Figure 12-4 for the transmitter 
schematic.
The transmitter takes modulated RF from the FGU and amplifies it to the radio’s rated output power 
to produce the modulated transmitter carrier at the antenna.
The transmitter consists of an RF driver IC that receives its input signal from the voltage-controlled 
oscillator (VCO) and a high-power output transistor. Transmitter power is controlled by a power-
DAC AGC
LNA IFIN
FREF
LO
Synth.Samp. Clock
SynthesizerVoltage/
Current
ReferenceControl Logic
SPI Decimation
Filter
MADC AD9874
-16dB
......=13-26MHz
DOUTA
DOUTB
FS
CLKOUT
LO VCO and
Loop FilterCLK VCO and
Loop Filter
IOUTL
LOP
LON
IOUTC
CLKP
CLKN
VREFP
RREF
VREFN
PC
PD
PE
SYNCBMXOP
MXON
IF2P
IF2N
GCP
GCN
Formatting/SSI
MAEPF-27412-O 
						

							November 11, 20046881094C12-A
2-12Theory of Operation: Transceiver Board
control IC (PCIC) that senses the output of a directional coupler and adjusts PA control voltages to 
maintain a constant power level. The signal passes through a dual antenna switch and harmonic 
filters to the antenna or to the remote RF port.
Figure 2-6.  Transmitter Block Diagram
2.4.3.1  Power Distribution
To minimize voltage drop to the power amplifiers, net RAWB+ connects to power module Q107 and 
the second stage of driver amplifier U102 through components having minimal series resistance— 
ferrite beads and chokes only. During receive, no RF or DC bias is applied, and leakage current 
through U102 and Q107 is less than 100 microamps. 
At the rated transmitter power of 5 Watts, the radio consumes approximately 1800 mA, and at the 
rated transmitter power of 2 Watts the radio consumes approximately 1100 mA.
2.4.3.2  Driver Amplifier
The driver amplifier IC (U102) contains two LDMOS FET amplifier stages and two internal resistor 
bias networks. Pin 16 is the RF input. Modulated RF from the FGU, at a level of +3 dBm ±2 dB, is 
coupled through a DC blocking capacitor to the gate of FET-1. An LC interstage matching network 
connects the first stage output VD1 to the second stage input G2. The RF output from the drain of 
FET-2 is pin 6 (RFOUT1). Gain control is provided by a voltage applied to pin 1 (VCNTRL). Typical 
output power is about +27 dBm (500 mW) with VCNTRL at 5.0 V.
L109 and C113 are the interstage matching network. Components L105 and C110 match the output 
impedance to 50 ohms; capacitor C107 is a DC block.
2.4.3.3  Power Amplifier Transistor Q107
The power amplifier transistor, Q107, is an LDMOS FET housed in a high-power, surface-mount, ring 
package. To prevent thermal damage, it is essential that the heat sink of the power module be held in 
place against the radio chassis. The input impedance-matching network uses discrete inductors and 
capacitors. The low-pass output matching network uses both transmission lines and lumped LCs. 
Drain bias is applied through E101 and L101. Gain is dynamically controlled by adjusting the gate 
bias. The gate is insulated from the drain and source so that gate bias current is essentially zero.
The input impedance-matching network is L106, L107, C108, and C109. A transmission-line 
structure and C137, C111, L110 and C112 form the output-matching network. Gate bias is applied 
through R105 and L108.
Modulated RF
from FGUDriver 
amplifierPower
amplifierDirectional
couplerDual
Antenna
switchHarmonic
filters
Antenna
Forward power detector
Vd = m*sqrt(P) + b
RFIN INT
PCIC
MAEPF-27408-O
To
Remote
RFRX
VVVVV 
						

							6881094C12-ANovember 11, 2004
Theory of Operation: Transceiver Board2-13
2.4.3.4  Directional Coupler
A directional coupler senses the transmitter forward power as a control signal in the transmitter’s 
automatic level control (ALC) loop. Isolated ports are terminated with external resistors.
The directional coupler is U101, a low-loss, bidirectional coupler.
2.4.3.5  Antenna Switch 
The SSE 5000 has two antenna switches: one standard antenna switch and a remote antenna 
switch. 
The standard antenna switch is a quarterwave switch that determines whether the radio is in receive 
or transmit mode. The standard antenna switch consists of part numbers D701, D702, C706, C704, 
C701, C707, L702, L703, and R701. When the standard antenna switch is in receive mode, the 
diodes D701 and D702 are unbiased and radio signals are able to travel to the receive front-end. 
When the standard antenna switch is in transmit mode, radio signals travel from the transmitter to 
the selected port and radio signals from the transmitter to the receive front-end are redirected by the 
large impedance presented by L702 and C704. The receive front-end is also protected from the 
transmitter because of the combined effect of the radio wave redirection and the short produced by 
C703 when the standard antenna switch is enabled. 
The circuitry that enables the standard antenna switch consists of part numbers L703, C707, and 
U104. When the radio is in transmit mode, pin 32 (also known as ANO) on U104 provides 
approximately 6.7 volts to diode D702. This voltage is dropped approximately 1.4 volts, or two diode 
drops, and applied to R701. R701 sets the current through the antenna switch (approximately 14 
mA). L703 and C707 are used as a DC bias network designed to only transmit DC signals. 
The remote antenna switch is also a quarterwave switch, but this switch determines which antenna 
the radio uses for transmit or receive. The remote antenna switch consists of part numbers D602, 
D601, C724, C725, C726, C727, C728, L701, L704, L711, R703, R704, R705, Q702, and Q703.
When the radio is receiving from the standard antenna, no diodes are forward biased. In order to 
activate the remote antenna port, the VOCON must supply 2.9 volts (+/– 3%) to pin 19 of the 26-pin 
connector. Pin 19 is also known as TX_INH. TX_INH going high causes the voltage on the collector 
of Q703 to become the voltage on the emitter. The voltage on the emitter for this circuit is zero volts. 
The collector is connected to the gate of Q702, which in turn forces the voltage on the drain of Q702 
to become the voltage on the source of Q702. The voltage on the source of Q702 is switched B+, or 
battery voltage. Switched B+ is dropped approximately 1.4 volts, or two diode drops, and applied to 
R705. R705 sets the current through the remote port switch (approximately 12 mA). 
L701 and C724 are used as a DC bias network designed to only transmit dc signals. When the radio 
is receiving or transmitting through the remote port, radio signals travel through diode D602. The 
signals are directed away from the standard antenna by the large impedance presented by L704 and 
C727. Accidental radiation through the standard antenna is prevented, because of the combined 
effect of the radio wave redirection and the short produced by C725 when the remote port is 
enabled. 
NOTE:Part numbers C728 and L711 are used to resonate the parasitic capacitance created by diode 
D602. The parasitic capacitance was creating a degradation in the transmit response through 
the standard antenna port. Essentially, C728 is a DC block to prevent reverse biasing D602, 
and L711 resonates with the parasitic capacitance of D602 to create a large impedance. 
2.4.3.6  Harmonic Filter 
RF from the power amplifier is routed through the coupler (U101), passed through the antenna 
switch, passed through the remote port switch, and applied to a harmonic filtering network. The SSE 
5000 harmonic filters are five-pole elliptical low-pass filters.  
						

							November 11, 20046881094C12-A
2-14Theory of Operation: Transceiver Board
The initial design utilizes a cutoff frequency of 750 MHz, even though the actual design cutoff 
frequency is 488 MHz. The reasoning behind using a significantly higher cutoff frequency is due to 
the lower frequency response of realized circuits. The design tables used for the filter synthesis can 
be located in the Handbook of Filter Synthesis (Zverev, pp. 218–219), where θ = 47.0. This design 
was chosen because the attenuation at the stop band was the closest to the desired ratio for the 
SSE 5000 design. 
The remote port harmonic filter consists of parts C709, C710, C711, C712, C713, L706, and L707. 
The antenna port harmonic filter consists of parts C716, C717, C718, C719, C720, L709, and L710. 
The filters are optimized for the impedance match seen for their respective ports and terminations. 
NOTE:Capacitor C720 was changed to 2pF, because this value improved the radiated response of 
the radio with the antenna removed. Also, Capacitors C710 and C711 were increased in order 
to remove a spur located at the (2*LO)-IF frequency point (680.075 MHz), where LO is 
450.0625 MHz – 73.35 MHz and IF is 73.35 MHz. Essentially, C710 and C711 decreased the 
cutoff frequency of the remote port harmonic filter.
2.4.3.7  RF Detector D101 
Schottky diode D101 is used as a forward-power detector. Forward-coupled RF from the power 
amplifier is converted to a DC voltage. Detector output is a positive DC voltage, proportional to the 
amplitude of the RF signal at the input, and is applied to the ALC input of the PCIC.
2.4.3.8  Power-Control IC (PCIC) U104
The PCIC, U104, contains all of the digital, and most of the analog, circuits needed to control the 
transmitter power amplifier. Host control is through a 3-wire, smart SPI interface. Pin descriptions are 
shown in Table 2-8.
Table 2-8.  Power Control IC (U104) Pin Descriptions
PinNameDescription
1 RFIN Detector voltage input to ALC
2 T1 Test point
3 CI External capacitor for integrator time constant
4 INT Integrator output; control voltage to amplifiers
5 CJ External capacitor for PA rise and fall times
6, 7 VL, CL External capacitor for PA rise and fall times
8 GND1 Ground
9 F168 Reference clock input, 2.1 MHz
10, 13 QX, CQX External capacitor for voltage multiplier
11, 12 Q, CQ External capacitor for voltage multiplier
14 V10 Voltage multiplier output
15 VG Internal band-gap reference voltage
16 V45 Regulated 4.5 Vdc output
17 V5EXT Power supply input for internal voltage regulator 
						

							6881094C12-ANovember 11, 2004
Theory of Operation: Transceiver Board2-15
2.4.3.8.1  Power and Control
Since U104 is powered from switched B+, it makes its own regulated 4.5 Vdc to power the internal 
logic. The supply input is V5EXT at pin 17, and the output is V45 at pin 16. ANO at pin 32 is the 
control signal to the RX/TX antenna switch control circuit.
2.4.3.8.2  Automatic Level Control (ALC)
In TX mode, the PCIC disables the receiver, turns on the transmitter, and controls the TX power 
level. The automatic level control (ALC) circuit operates as follows:
The power level is set by programming an internal DAC to a calibrated reference voltage. D/A 
settings for the power set points were determined during radio tuning and stored in EEPROM. An 
internal op-amp compares the D/A reference voltage to the detector voltage at pin 1(RFIN) (TP101) 
and produces an error signal output. This signal is buffered by another op-amp, configured as a low- 
pass filter, or integrator, to produce the INT output at pin 4 (TP111). 
This INT output supplies voltage to drive the gain control pins of amplifiers U102 and Q107. 
Resistors R105 and R106 determine the voltage ratio between U102 pin 1 (VCNTRL) and the Q107 
gate. Transient response during key-up and key-down is controlled by the power amplifier rise and 
fall times. External capacitors at pins CI, CJ, and CL, along with internal programmable resistors, 
determine the ALC time constants.
2.4.3.8.3  Temperature Cut Back
The PCIC contains a temperature cut-back circuit to protect the power amplifier (PA) from thermal 
damage that might result from incorrect assembly of the radio. External sensor U103 is a linear 
temperature-to-voltage transducer, placed near the hottest spot in the radio: power module Q107. 
18 VAR2 Buffered D/A output
19 VLIM Test point for internal D/A No.2 voltage
20 VAR1 Buffered D/A output
21 RS Asynchronous reset input
22 NA Spare pin
23 RX RX/TX mode control-bit output
24 VAR3 Buffered D/A output
25 GND2 Ground
26 CLK SPI clock input
27 BPOS Power supply input
28 DATA SPI data input/output
29 CEX SPI chip select input
30 TEMP Temperature sensor input
31 RSET External resistor; used to set the temperature cutback rate
32 ANO Switched BPOS output 
Table 2-8.  Power Control IC (U104) Pin Descriptions (Continued)
PinNameDescription 
						

							November 11, 20046881094C12-A
2-16Theory of Operation: Transceiver Board
The output is a DC voltage at pin 2 (VOUT) proportional to the temperature at pin 3 (GND). VOUT is 
750 mV at 25°C and increases by 10 mV/°C. The PCIC temperature cut-back threshold is 
programmed to correspond to 85 or 90°C. Above this threshold, the ALC gradually cuts back the 
transmitter until it is fully turned off at 125°C. The slope of cut-back versus temperature is set by 
external resistor R111. Diode D104 clamps TEMP to a voltage not much less than VG (pin 15), about 
1.3 V, to improve the transient response of the cut-back circuit.
2.4.4 Frequency Generation Unit (FGU)
The frequency-generation function is performed by several ICs, two voltage-controlled oscillators 
(VCOs) (one transmit and one receive), and associated circuitry. The reference oscillator provides a 
frequency standard to the fractional-N frequency synthesizer (FracN) IC, which controls the VCOs 
and VCO buffer IC (VCOBIC). The VCOBIC amplifies the VCO signal to the correct level for the next 
stage.
NOTE:Refer to Figure 12-5 and Figure 12-6 for the FGU schematics.
2.4.4.1  Reference Oscillator Y200
The radio’s frequency stability and accuracy derive from the Voltage-Controlled Temperature- 
Compensated Crystal Oscillator (VCTCXO), Y200. This 16.8 MHz oscillator is controlled by the 
voltage from the WARP pin of the FracN IC, U202, that can be programmed through a serial 
peripheral interface (SPI). The oscillator output at pin 3 is coupled through capacitor C234 to the 
FracN synthesizer reference oscillator input and through C236 to the non-invertive input of the op-
amp, U201.
Op-amp U201 buffers the 16.8 MHz output to the VOCON board. Components L205 and C214 form 
a low-pass filter to reduce harmonics of the 16.8 MHz.
The Digital-to-Analog Converter (DAC) IC, U203, and Switched Capacitors Filter (SCF) IC, FL200, 
form the interface between radios DSP and the analog modulation input of the FracN IC.
2.4.4.2  Fractional-N Frequency Synthesizer (FracN) IC U202
The FracN IC, U202, is a mixed-mode, Motorola-proprietary, CMOS, fractional-N frequency 
synthesizer with built-in dual-port modulation. The SSE 5000 radio uses a low-voltage version of the 
device, sometimes called LVFracN, for compatibility with the 3 V logic used throughout the radio.
The FracN IC incorporates frequency division and comparison circuitry to keep the VCO signals 
stable. The FracN IC is controlled by the MCU through a serial bus. All of the synthesizer circuitry is 
enclosed in rigid metal cans on the transceiver board to reduce interference effects.
Separate power supply inputs are used for the various functional blocks on the IC. Inductors L203 
and L204 provide isolation between supply pins 20 (AVDD) and 36 (DVDD) connected to Vdd3. Host 
control is through a three-wire, smart SPI interface (pins 7, 8, and 9) with a bi-directional data pin. 
FracN functions include frequency synthesis, reference clock generation, modulation control, voltage 
multiplication and filtering, and auxiliary logic outputs.
2.4.4.2.1  Synthesizer
Frequency synthesis functions include a dual-modulus prescaler, a phase detector, a programmable 
loop divider and its control logic, a charge pump, and a lock detector output. Fractional-N synthesizer 
IC principles of operation are covered in detail in the manufacturers’ literature. No similar discussion 
will be attempted here.
2.4.4.2.2  Clocks
U202, pin 23 (XTAL1), is the 16.8 MHz reference oscillator input from the VCTCXO (Y200). 
						

							6881094C12-ANovember 11, 2004
Theory of Operation: VOCON Board2-17
2.4.4.2.3  Modulation
To support many voice, data, and signaling protocols, the SSE 5000 radio must modulate the 
transmitter carrier frequency over a wide audio frequency range, from less than 10 Hz up to more 
than 6 kHz. The FracN supports audio frequencies down to zero Hz by using dual-port modulation. 
The audio signal at pin 10 (MODIN) is internally divided into high- and low-frequency components, 
which modify both the synthesizer dividers and the external VCOs through signal MODOUT (pin 41). 
The IC is adjusted to achieve flat modulation frequency response during transmitter modulation 
balance calibration using a built-in modulation attenuator.
2.4.4.2.4  Voltage Multiplier and Superfilter
Pins 12 (VMULT3) and 11 (VMULT4) together with diode arrays D201 and D202 and their associated 
capacitors form the voltage multiplier. The voltage multiplier generates 11.5 Vdc to supply the phase 
detector and charge-pump output stage at pin 47 (VCP).
The superfilter is an active filter that provides a low-noise supply for the VCOs and VCOBIC. The 
input is regulated 5 Vdc from Vdd5 at pin 30 (SFIN). The output is superfiltered voltage FSF at pin 28 
(SFOUT).
The output from pin 15 (VMULT1) is used as a clock for the SCF IC, FL200.
2.4.4.3  Loop Filter
The components connected to pins 43 (IOUT) and 45 (IADAPT) form a 3rd-order, RC low-pass filter. 
Current from the charge-pump output, IOUT, is transformed to voltage VCTRL, which modulates the 
VCOs. Extra current is supplied by IADAPT for rapid phase-lock acquisition during frequency 
changes. The lock detector output pin 4 (LOCK) goes to a logic “1” to indicate when the phased-lock 
loop is in lock.
2.4.4.4  VCO Buffer IC (VCOBIC)
The VCOBIC (U250) is an analog IC containing two NPN transistors for use as oscillators, an active-
bias circuit, transmitter and receiver buffer amplifiers, and switching circuitry. The VCOBIC has three 
RF outputs:
• TX_OUT (pin 10)—the modulated transmitter carrier
• RX_OUT (pin 8)—the receiver first LO
• PRESC_OUT (pin 12)—connected to FracN pin 32 (PREIN) through a matching circuit
Transmit/receive control is a single 5.0 Vdc logic input, TRB_IN (pin 19). When TRB_IN is low, the 
receiver buffer is active and the transmitter circuits are disabled. The converse is also true.
This radio uses two external, discrete, varactor-tuned, Colpitts VCOs based on transistors Q211 and 
Q215. Bias current to the VCOs is switched on and off by transistors Q214 and Q210, which are 
controlled by FracN outputs AUX2 and AUX4. Transistors packged in Q301 form a 3.3 Vdc-to-5 Vdc 
logic-level shifter for the signal from the FracN AUX3 pin to the VCOBIC.
2.5 VOCON Board
This section provides a detailed circuit description of the SSE 5000 VOCON (vocoder and controller) 
board.
NOTE:Refer to Table 12-2 for a listing of VOCON schematics that will aid in the following discussion.
The VOCON board block diagram (see Figure 2-7) contains three functional blocks and six 
connector symbols.
The functional blocks consist of the following: 
						

							November 11, 20046881094C12-A
2-18Theory of Operation: VOCON Board
• Controller and Memory: The dual-core processor (U401) with the microcontroller unit (MCU) 
and a digital signal processor (DSP) in a single integrated circuit (IC) package, the SRAM 
(U403) and Flash (U402) memory devices.
• Audio and Power: The GCAP II (U501), a 5 Vdc linear regulator (U505), a 1.55 Vdc linear 
regulator, the audio pre-amplifier (U502), the audio power amplifier (U503), and the dual 
EEPOT (U509).
• Interface Support: The digital-support IC (U301) (Flipper), ESD protection circuitry, and side 
connector interface circuitry.
The connector symbols represent the following:
• Transceiver board connector
• Universal flex connector
• Internal speaker and microphone flex connector
• Control top flex connector
• Liquid-crystal display (LCD) board connector
• Encryption module connector (optional) 
Figure 2-7.  VOCON Board Block Diagram
2.5.1 Interconnections
2.5.1.1  Transceiver Board Connector P201
This is a 26-pin compression connector that interfaces between the VOCON board and the 
transceiver board. See Section 2.4.1.2: “VOCON Connector P1” on page 2-7 for a detailed 
description of the interface between the VOCON and transceiver boards through P201. 
2.5.1.2  Universal Flex Connector J102
This is a 40-pin connector that mates with the universal flex on the housing. A majority of the lines on 
the connector are for user interface: emergency and side buttons (pin 14), monitor button (pin 17), 
secure/clear switch (pin 23), channel switch (pins 24, 25, 26, and 27), volume knob (pin 31), and the 
three-position toggle switch (pin 34). The LEDs on the universal flex are controlled through pins 20, 
Dual-Core
Processor
MCU & DSP
SRAM
FLASH
Memory CONTROLLER & MEMORY
GCAP II
& Discrete 
Voltage 
Regulators
Audio 
EEPOT
Pre-amp &
Power Amp
AUDIO & POWER
Digital Support IC
Clocks & Side
Connector SupportVOCON
Board
Control Top
Display
Encryption Transceiver
Board
Universal/
Accessory
Connector
ESD Protection &
Side Connector
Circuitry
INTERFACE SUPPORT
Internal
Speaker &
Microphone 
MAEPF-27533-B