Casio Qt6000 Service Manual
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Page 71
Ñ 69 Ñ 8-12. DISPLAY CONTROLLER (IC45: SM712) 8-12-1. Pin Assignment MD3MD4MD5MD7MD31MD17MD28MD20MD25MD22AD0AD4AD7AD9AD12AD14PAR MD44 MD45 ~DQM4FPFPENCKINAVDDAVSS2 MD0MD11MD9MD8MD30MD18MD27MD21MD24AD1AD5~BE0AD10AD13~BE1 MD1MD13MD10MD6~DQM2MD16MD29MD19MD26MD23AD3AD6AD8AD11AD15AD17 ~DQM1MD14VDDVSSMVDDN/CMVDDVSSVSSAD2HVDDVSSHVDDVDDVSSHVDDAD19AD20 MD46 MD34 MD47LPDECRTH SYNCRVDDIREF BLUE P15 MD42 MD41 MD33~DQM5FPSCLKCVDDRVSS RED USR1TEST0 MD38 MD39 MD43MVDDN/CFDA22N/CFPVDDN/CN/CFPVDDN/CCVSSAVSS1USR0TEST1P13...
Page 72
![Page 72
Ñ 70 Ñ
PIN NAME I/O DESCRIPTION
AD [31:0]
C/
~BE [3:0]
PAR
~FRAME
~TRDY
~IRDY
~STOP
~DEVSEL
IDSEL
CLK
~RST
~REQ
~GNT
~INTA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
I
OPCI multiplexed Address and Data Bus. A bus transaction consists of an address cycle followed by one or
more data cycles.
PCI Bus Command and Byte Enables. These signals carry the bus command during the address cycle and
byte enable during data cycles.
Parity. LynxEM+ asserts this signal to verify even parity across AD [31:0] and C/~BE...](http://img.usermanuals.tech/thumb/16/104070/w300_qt6000-service-manual-1517931421_d-71.png "Page 72
Ñ 70 Ñ
PIN NAME I/O DESCRIPTION
AD [31:0]
C/
~BE [3:0]
PAR
~FRAME
~TRDY
~IRDY
~STOP
~DEVSEL
IDSEL
CLK
~RST
~REQ
~GNT
~INTA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
I
OPCI multiplexed Address and Data Bus. A bus transaction consists of an address cycle followed by one or
more data cycles.
PCI Bus Command and Byte Enables. These signals carry the bus command during the address cycle and
byte enable during data cycles.
Parity. LynxEM+ asserts this signal to verify even parity across AD [31:0] and C/~BE...")
Ñ 70 Ñ PIN NAME I/O DESCRIPTION AD [31:0] C/ ~BE [3:0] PAR ~FRAME ~TRDY ~IRDY ~STOP ~DEVSEL IDSEL CLK ~RST ~REQ ~GNT ~INTA I/O I/O I/O I/O I/O I/O I/O I/O I I I O I OPCI multiplexed Address and Data Bus. A bus transaction consists of an address cycle followed by one or more data cycles. PCI Bus Command and Byte Enables. These signals carry the bus command during the address cycle and byte enable during data cycles. Parity. LynxEM+ asserts this signal to verify even parity across AD [31:0] and C/~BE...
Page 73
![Page 73
Ñ 71 Ñ
PIN NAME I/O DESCRIPTION
MA [9:0]
MD [63:0]
~WE
~RAS
~CAS
~CS0
~DQM
[7:0]
DSF
BA
SDCK
SDCKEN
~ROMEN
O
I/O
O
O
O
O
O
O
O
I/O
I/O
OExternal Memory Address Bus. The video memory row and column addresses are multiplexed on these
lines.
External Memory Data Bus
External Memory Write Strobe
External Memory SDRAM Row Address Select
External SGRAM Column Address Select
External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB
memory
External SGRAM I/O mask [7:0]....](http://img.usermanuals.tech/thumb/16/104070/w300_qt6000-service-manual-1517931421_d-72.png "Page 73
Ñ 71 Ñ
PIN NAME I/O DESCRIPTION
MA [9:0]
MD [63:0]
~WE
~RAS
~CAS
~CS0
~DQM
[7:0]
DSF
BA
SDCK
SDCKEN
~ROMEN
O
I/O
O
O
O
O
O
O
O
I/O
I/O
OExternal Memory Address Bus. The video memory row and column addresses are multiplexed on these
lines.
External Memory Data Bus
External Memory Write Strobe
External Memory SDRAM Row Address Select
External SGRAM Column Address Select
External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB
memory
External SGRAM I/O mask [7:0]....")
Ñ 71 Ñ PIN NAME I/O DESCRIPTION MA [9:0] MD [63:0] ~WE ~RAS ~CAS ~CS0 ~DQM [7:0] DSF BA SDCK SDCKEN ~ROMEN O I/O O O O O O O O I/O I/O OExternal Memory Address Bus. The video memory row and column addresses are multiplexed on these lines. External Memory Data Bus External Memory Write Strobe External Memory SDRAM Row Address Select External SGRAM Column Address Select External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB memory External SGRAM I/O mask [7:0]....
Page 74
![Page 74
Ñ 72 Ñ
PIN NAME I/O DESCRIPTION
RED
GREEN
BLUE
IREF
CRTVSYNCC
CRTHSYNC/
CSYNC
O
O
O
I
O
OAnalog Red Current Output
Analog Green Current Output
Analog Blue Current Output
Current Reference Input
CRT Vertical Sync
CRT Horizontal Sync or Composite Sync depending on CCR65 [0]
0 = CRT Horizontal Sync
1 = Composite Sync
CRT Interface
Video Port Interface
P [15:0]
PCLK
VREF
HREF
BLANK/
TVCLKI/O
I/O
I/O
I/O
I/ORGB or YUV input/ RGB digital output
Pixel Clock
VSYNC input from PC Card or video decoder
HSYNC input...](http://img.usermanuals.tech/thumb/16/104070/w300_qt6000-service-manual-1517931421_d-73.png "Page 74
Ñ 72 Ñ
PIN NAME I/O DESCRIPTION
RED
GREEN
BLUE
IREF
CRTVSYNCC
CRTHSYNC/
CSYNC
O
O
O
I
O
OAnalog Red Current Output
Analog Green Current Output
Analog Blue Current Output
Current Reference Input
CRT Vertical Sync
CRT Horizontal Sync or Composite Sync depending on CCR65 [0]
0 = CRT Horizontal Sync
1 = Composite Sync
CRT Interface
Video Port Interface
P [15:0]
PCLK
VREF
HREF
BLANK/
TVCLKI/O
I/O
I/O
I/O
I/ORGB or YUV input/ RGB digital output
Pixel Clock
VSYNC input from PC Card or video decoder
HSYNC input...")
Ñ 72 Ñ PIN NAME I/O DESCRIPTION RED GREEN BLUE IREF CRTVSYNCC CRTHSYNC/ CSYNC O O O I O OAnalog Red Current Output Analog Green Current Output Analog Blue Current Output Current Reference Input CRT Vertical Sync CRT Horizontal Sync or Composite Sync depending on CCR65 [0] 0 = CRT Horizontal Sync 1 = Composite Sync CRT Interface Video Port Interface P [15:0] PCLK VREF HREF BLANK/ TVCLKI/O I/O I/O I/O I/ORGB or YUV input/ RGB digital output Pixel Clock VSYNC input from PC Card or video decoder HSYNC input...
Page 75
Ñ 73 Ñ PIN NAME I/O DESCRIPTION HVDD MVDD FPVDD VPVDD CVDD AVDD RVDD CVSS AVSS1 AVSS2 RVSS VDD VSS Host Interface VDD on I/O Ring, 3.3V Display Memory Interface VDD on I/O Ring, 3.3V Flat Panel Interface VDD on I/O Ring, 3.3V VPVDD VPort Interface VDD on I/O Ring 3.3V Clock (PLL) Analog Power, 3.3V DAC Analog Power, 3.3V RAM Filtered Palette Power, 3.3V PLL Analog Ground DAC Analog Ground DAC Analog Ground RAM Filtered Palette Ground Digital 3.3V Core Power Supply Digital 3.3V Internal Memory Power...
Page 76
Ñ 74 Ñ 8-13. ADPCM SPEECH LSI (IC15: MSM9841) 8-13-1. Pin Assignment MOUT LOUTAOUTLAOUTR MIN EMP MID FUL/DREQR CH/DACKR D15 to D0 WR RD CS D/C BUSYFIFO MCU I/FADSD DASD SIOCK TEST0 TEST1 DREQLDACKLIOWIOR VCKXTXTRESET input side LPF Volume Controller ADPCM2/ADPCM/PCM/Non-linear PCM Synthesizer DMA I/F Timing Controller External DAC/ ADC I/F LIN ADCoutput side LPFDACDAC SG AV DD AGND DV DD DGND ADPCM2/ADPCM/PCM Analyzer output side LPF 8-13-2. Block Diagram D0 D1 D2 D3 NC D4 D5 D6 D7 NC D8 D9 D10...
Page 77
Ñ 75 Ñ 8-13-3. Pin Function PIN NAME I/O DESCRIPTION D15-D8 D7-D0 WR RD CS D/C BUSY EMP MID FUL/ DREQR CH/DACKR DREQL DACKL IOW IOR ADSD DASD SIOCK I/O I/O I I I I O O O O I O I I I I O OFor 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs to input or output data to and from an external memory. Otherwise, these pins are configured to be inputs only. For 16-bit interface, these pins are a bidirectional data bus to input or output data to and from an external...
Page 78
Ñ 76 Ñ PIN NAME I/O DESCRIPTION Oscillator connection pins. When external clock is used, input clock into XT pin and leave XT pin open. Outputs sampling frequency selected at recording or playback. VCK pin is used as a synchronizing signal when external ADC or DAC is used. When this pin is ÒLÓ level input, the LSI is initialized. Pins for testing. Set the pins to ÒLÓ. Analog circuit signal ground output pin. Inverting input pin for built-in OP amplifier. Noninverting input pin is connected to SG (Signal...
Page 79
Ñ 77 Ñ 8-14. ETHERNET CONTROLLER (IC28: LAN91C113) 8-14-1. Pin Assignment 8-14-2. Block Diagram
Page 80
![Page 80
Ñ 78 Ñ
8-15. PCMCIA CONTROLLER (IC36: R5C485)
8-15-1. Pin Assignment
8-15-2. Block Diagram
GBRST#AD[31:0]IDSEL GNT# REQ#
C/BE[3:0]#
DEVSEL# FRAME#
IRDY#
TRDY#
Interrupt
&
Audio RESET
&
Clock
Socket
Power
Control Socket
Status &
Control
16-bit
Registers CardBus
Registers PCI
Config.
Registers16-bit
Interface
Master CardBus
Interface
Master &
Target CardBus
Address
Decode
&
Mapping PCI
Address
Decode
&
Mapping PCI
Interface
STOP#
PERR#
SERR#
PCICLK
PCIRST#
CLKRUN#
INTA#
IRQ3-IRQ15
RI_OUT#/PME# HWSPND#M
P
X...](http://img.usermanuals.tech/thumb/16/104070/w300_qt6000-service-manual-1517931421_d-79.png "Page 80
Ñ 78 Ñ
8-15. PCMCIA CONTROLLER (IC36: R5C485)
8-15-1. Pin Assignment
8-15-2. Block Diagram
GBRST#AD[31:0]IDSEL GNT# REQ#
C/BE[3:0]#
DEVSEL# FRAME#
IRDY#
TRDY#
Interrupt
&
Audio RESET
&
Clock
Socket
Power
Control Socket
Status &
Control
16-bit
Registers CardBus
Registers PCI
Config.
Registers16-bit
Interface
Master CardBus
Interface
Master &
Target CardBus
Address
Decode
&
Mapping PCI
Address
Decode
&
Mapping PCI
Interface
STOP#
PERR#
SERR#
PCICLK
PCIRST#
CLKRUN#
INTA#
IRQ3-IRQ15
RI_OUT#/PME# HWSPND#M
P
X...")
Ñ 78 Ñ 8-15. PCMCIA CONTROLLER (IC36: R5C485) 8-15-1. Pin Assignment 8-15-2. Block Diagram GBRST#AD[31:0]IDSEL GNT# REQ# C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# Interrupt & Audio RESET & Clock Socket Power Control Socket Status & Control 16-bit Registers CardBus Registers PCI Config. Registers16-bit Interface Master CardBus Interface Master & Target CardBus Address Decode & Mapping PCI Address Decode & Mapping PCI Interface STOP# PERR# SERR# PCICLK PCIRST# CLKRUN# INTA# IRQ3-IRQ15 RI_OUT#/PME# HWSPND#M P X...