Casio Qt6000 Service Manual

— 49 —
[ 27 ] Sound playback test
[Function]
This test will check the sound playback of the internal or external speaker.
In case of one time check only, the test can be ended by the judgment (OK or NG) of the operator.
[Operation]
Operation :  a x n 0 9 7 ST
a: Number of volume levels
0 → Max volume
* The volume can be designated in 8 levels (0 to 7). The higher the number is, the
lower the volume is. Note that the number 8 and 9 automatically are changed to 7.
x : 0 → Plays back the sound which was...

— 50 —
[ 28 ] Sound recording test
[Function]
This test will check the sound recorded by the internal or external microphone.
The test records sound for three seconds, followed by the playback of the recorded data at the
maximum volume.
[Operation]
Operation : 9 8 ST
Press [OK] or [NG] key to end the test.
OK = 1
NG = 9
[LCD]
[ 29 ] Charging test
[Function]
This test will turn off the charging function.
[Operation]
Operation : 9 9 ST
[LCD]
CAHRGE OFF  99
END   99
CAHRGE OFF  99
END   99
MIKE   98
MIKE...

— 51 —
option
iButton Probe
+19V 12.1inch TFT LCD UNIT
Touch PanelCFL INVERTOR unit
Init
CUSTOMER DISP. SYSTEMOPTIONAL REMOTE +5V SupplyOPTIONAL Hand Held Scanner
iButton FROM
EtherNet 1
iButton LCDC
CF CARD
CF card I/FCardBusCPU
Power Supply for CFL
Wireless LAN CARD
SPEAKER
SW
CFL
CARDBUS card I/F         
COM1DSUB9pin
Battery
main pcb
+5V Supply
COM2
SIGNAL ONLY
Disp On/OffSDRAM
E820-1
MCR
I/O ctrl.
G/A Sound
BGA256pin
BGA90pin
EtherNet
MODEM or PC
COM4~6
DSUB9pin x3SPEAKER OutMIC in
Green
DL-****...

— 52 —
8-2. LSI BLOCK DIAGRAM
BUZZER
DRAWER DRIVE x 2
COMPULSORY SW x 2
LOAD x 2
CLOCK x 2
DATA x 2
SERIAL I/FISDN(MODEM)PORT
10M/100MBASE SH BUS
80Mhz
PCI BUS
33MhzBUFFER
(IC8, 13, 17)
SDRAM
256MB
(IC12)
FROM
128MB
(IC1)
SVGA
TFT PANEL
(12.1inch)
TOUCH
PANEL
DALLAS
KEY DISPLAY
ON/OFF
SW
DRAWER
PORT
X 2
SOFT
WARE
KEY LCDC IC
(IC45)
SERIAL I/F
3.3V    5VPCMCIA IC
(IC36)
PCI     CARD
CPUSH-4
SH-7751R
240MHz
(IC26)
I/O
CONTROLLER
78K4
12.5MHz
(IC44)PC CARD
SLOT CARD BUS
IEEE802.11b
IEEE802.11g BUFFER
(IC4,...

— 53 —
8-3. RESET CIRCUIT
The reset circuit is as follows.
8-4. POWER SUPPLY CIRCUIT 1
VP (DC 19V) For the drawer circuit
VOP (DC 5.2V) For the COM2, 3 power and display ON/OFF LED
VCC (DC 5V) For the logic circuit power
The power supply circuit is as follows. 

— 54 —
8-5. POWER SUPPLY CIRCUIT 2
VBAT (DC 3.3V) For the battery
V1.5 (DC 1.5V) For the CPU core
V1.8 (DC 1.8V) For the PCMCIA core
The power supply circuit is as follows.
8-6. DRAWER I/F CIRCUIT
The drawer open circuit is as follows. 

— 55 —
8-7. CPU (IC26: SH7751)
8-7-1. Pin Assignment
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256 XTAL2
EXTAL2
VDD-RTC
VSS-RTC
CA
NMI//MD6/
TXD
MD2/RXD2
RXD
TCLK
MD8/
SCK
MD1/TXD2
MD0/SCK2
MD7/
AUDSYNC
AUDCK
AUDATA0
AUDATA1
AUDATA2
AUDATA3
Reserved
MD3/MD4/
MD5
DACK0
DACK1
DRAK0
DRAK1
STATUS0...

— 56 —
8-7-2. Block Diagram
Lower 32-bit data
64-bit data (store)
CPG
INTC
SCI
(SCIF)
RTC
TMU
External (SH) bus
interface
DMAC
32-bit data29-bit address
32-bit data Address
32-bit data
32-bit data
Upper 32-bit data 32-bit address (instructions)
32-bit data (instructions)
32-bit address (data)
Peripheral address bus
26-bit 
SH bus
address 32-bit
PCI
address/
data32-bit 
SH bus
data
Peripheral data bus
UBC
32-bit data (store) 32-bit data (load)
CPU
I cacheO cacheITLB UTLBCache and
TLB
controller
FPU
BSC:...

— 57 —
8-7-3. Pin Function
NO. PIN NAME I/O DESCRIPTION
1 TMS I Mode (H-UDI)
2 TCK I Clock (H-UDI)
3 VDDQ Power IO VDD
4 VSSQ Power IO GND
5 TDI I Data in (H-UDI)
6 CSO O Chip select 0
7 CS1 O Chip select 1
8 CS4 O Chip select 4
9 CS5 O Chip select 5
10 CS6 O Chip select 6
11 BS O Bus start
12 WE0/REG O D7–D0 select signal
13 WE1 O D15-D8 select signal
14 D0 I/O Data
15 VDDQ Power IO VDD
16 VSSQ Power IO GND
17 VDD Power Internal VDD
18 VSS Power Internal GND
19 D1
20 D2
21 D3
22 D4
23 D5
I/O Data
24 D6...

— 58 —
NO. PIN NAME I/O DESCRIPTION
55 VDDQ Power IO VDD
56 VSSQ Power IO GND
57 A4
58 A5
59 A6
60 A7
61 A8
O Address
62 A9
63 A10
64 A11
65 A12
66 A13
67 VDDQ Power IO VDD
68 VSSQ Power IO GND
69 A14
70 A15
O Address
71 A16
72 A17
73 CAS2/DQM2 O D23–D16 select signal
74 CAS3/DQM3 O D31–D24 select signal
75 D16
76 D17
I/O Data
77 D18
78 D19
79 VDDQ Power IO VDD
80 VSSQ Power IO GND
81 VDD Power Internal VDD
82 VSS Power Internal GND
83 D20
84 D21
85 D22
86 D23
87 D24
I/O Data
88 D25
89 D26
90 D27
91 D28...