Casio Qt 6100 Service Manual
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Page 61
— 59 — 8-9. SDRAM (IC12: HY5V52ALFP-H-C) DQ26 1 A B C D E F G H J K L M N P R 2 3 4 5 6 7 8 9 DQ28 VSSQ VSSQ VDDQ VSSA4 A7 CL K DQ2 4 VDDQ DQ2 7 DQ2 9 DQ3 1 DQM3 A5 A8 CKE VSS VSSQ DQ2 5 DQ3 0 NC A3 A6 NC A9 VDD VDDQ DQ2 2 DQ1 7 NC A2 A1 0 NC BA0 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 /CS DQ2 1 DQ1 9 VDDQ VDDQ VSSQ VDD A1 A1 1 /RAS (Top view) DQM1 NCNC /CAS/WEDQM0 VDDQ DQ8VSS VDDDQ7VSSQ VSSQ DQ10 DQ9 DQ6DQ5VDDQ VSSQ DQ12DQ14 DQ1DQ3VDDQ DQ11 VDDQ VSSQ VDDQVSSQ DQ4 DQ13DQ15 VSS VDDDQ0DQ2 90-ball FBGA
Page 62
— 60 — 8-10. DISPLAY CONTROLLER (IC45: SM712) 8-10-1. Pin Assignment MD3MD4MD5MD7MD31MD17MD28MD20MD25MD22AD0AD4AD7AD9AD12AD14PAR MD44 MD45 ~DQM4FPFPENCKINAVDDAVSS2 MD0MD11MD9MD8MD30MD18MD27MD21MD24AD1AD5~BE0AD10AD 13~BE1 MD1MD13MD10MD6~DQ M2MD16MD29MD19MD26MD23AD3AD6AD8AD11AD15AD17 ~DQM1MD14VDDVSSMV DDN/CMVDDVSSVSSAD2HVDDVSSHV DDVDDVSSHVDDAD19AD20 MD46 MD34 MD47LPDECR TH SYNCRVDDIR EF BLUE P15 MD42 MD41 MD33~DQ M5FPSC LKCVDDRVSS RED USR1TEST0 MD38 MD39 MD43MVDDN/CFDA22N/CFPVDDN/CN/CFPVDDN/CCV...
Page 63
![Page 63
— 61 —
PIN NAME I/O DESCRIPTION
AD [31:0]
C/
~BE [3:0]
PAR
~FRAME
~TRDY
~IRDY
~STOP
~DEVSEL
IDSEL
CLK
~RST
~REQ
~GNT
~INTA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
I
OPCI multiplexed Address and Data Bus. A bus transaction consists of an address cycle followed by one or
more data cycles.
PCI Bus Command and Byte Enables. These signals carry the bus command during the address cycle and
byte enable during data cycles.
Parity. LynxEM+ asserts this signal to verify even parity across AD [31:0] and C/~BE...](http://img.usermanuals.tech/thumb/16/86909/w300_d_1502191232-qt-6100-service-manual_d-62.png "Page 63
— 61 —
PIN NAME I/O DESCRIPTION
AD [31:0]
C/
~BE [3:0]
PAR
~FRAME
~TRDY
~IRDY
~STOP
~DEVSEL
IDSEL
CLK
~RST
~REQ
~GNT
~INTA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
I
OPCI multiplexed Address and Data Bus. A bus transaction consists of an address cycle followed by one or
more data cycles.
PCI Bus Command and Byte Enables. These signals carry the bus command during the address cycle and
byte enable during data cycles.
Parity. LynxEM+ asserts this signal to verify even parity across AD [31:0] and C/~BE...")
— 61 — PIN NAME I/O DESCRIPTION AD [31:0] C/ ~BE [3:0] PAR ~FRAME ~TRDY ~IRDY ~STOP ~DEVSEL IDSEL CLK ~RST ~REQ ~GNT ~INTA I/O I/O I/O I/O I/O I/O I/O I/O I I I O I OPCI multiplexed Address and Data Bus. A bus transaction consists of an address cycle followed by one or more data cycles. PCI Bus Command and Byte Enables. These signals carry the bus command during the address cycle and byte enable during data cycles. Parity. LynxEM+ asserts this signal to verify even parity across AD [31:0] and C/~BE...
Page 64
![Page 64
— 62 —
PIN NAME I/O DESCRIPTION
MA [9:0]
MD [63:0]
~WE
~RAS
~CAS
~CS0
~DQM[7:0]
DSF
BA
SDCK
SDCKEN
~ROMEN
O
I/O
O
O
O
O
O
O
O
I/O
I/O
O
External Memory Address Bus. The video memory row and column addresses are multiplexed on these lines.
External Memory Data Bus
External Memory Write Strobe
External Memory SDRAM Row Address Select
External SGRAM Column Address Select
External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB memory
External SGRAM I/O mask...](http://img.usermanuals.tech/thumb/16/86909/w300_d_1502191232-qt-6100-service-manual_d-63.png "Page 64
— 62 —
PIN NAME I/O DESCRIPTION
MA [9:0]
MD [63:0]
~WE
~RAS
~CAS
~CS0
~DQM[7:0]
DSF
BA
SDCK
SDCKEN
~ROMEN
O
I/O
O
O
O
O
O
O
O
I/O
I/O
O
External Memory Address Bus. The video memory row and column addresses are multiplexed on these lines.
External Memory Data Bus
External Memory Write Strobe
External Memory SDRAM Row Address Select
External SGRAM Column Address Select
External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB memory
External SGRAM I/O mask...")
— 62 — PIN NAME I/O DESCRIPTION MA [9:0] MD [63:0] ~WE ~RAS ~CAS ~CS0 ~DQM[7:0] DSF BA SDCK SDCKEN ~ROMEN O I/O O O O O O O O I/O I/O O External Memory Address Bus. The video memory row and column addresses are multiplexed on these lines. External Memory Data Bus External Memory Write Strobe External Memory SDRAM Row Address Select External SGRAM Column Address Select External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB memory External SGRAM I/O mask...
Page 65
![Page 65
— 63 —
PIN NAME I/O DESCRIPTION
RED
GREEN
BLUE
IREF
CRTVSYN-CC
CRTH-
O
O
O
I
O
O
Analog Red Current Output
Analog Green Current Output
Analog Blue Current Output
Current Reference Input
CRT Vertical Sync
CRT Horizontal Sync or Composite Sync depending on CCR65 [0]0 = CRT Horizontal Sync1 = Composite Sync
CRT Interface
Video Port Interface
P [15:0]
PCLK
VREF
HREF
BLANK/TVCLK
I/O
I/O
I/O
I/O
I/O
RGB or YUV input/ RGB digital output
Pixel Clock
VSYNC input from PC Card or video decoder
HSYNC input from...](http://img.usermanuals.tech/thumb/16/86909/w300_d_1502191232-qt-6100-service-manual_d-64.png "Page 65
— 63 —
PIN NAME I/O DESCRIPTION
RED
GREEN
BLUE
IREF
CRTVSYN-CC
CRTH-
O
O
O
I
O
O
Analog Red Current Output
Analog Green Current Output
Analog Blue Current Output
Current Reference Input
CRT Vertical Sync
CRT Horizontal Sync or Composite Sync depending on CCR65 [0]0 = CRT Horizontal Sync1 = Composite Sync
CRT Interface
Video Port Interface
P [15:0]
PCLK
VREF
HREF
BLANK/TVCLK
I/O
I/O
I/O
I/O
I/O
RGB or YUV input/ RGB digital output
Pixel Clock
VSYNC input from PC Card or video decoder
HSYNC input from...")
— 63 — PIN NAME I/O DESCRIPTION RED GREEN BLUE IREF CRTVSYN-CC CRTH- O O O I O O Analog Red Current Output Analog Green Current Output Analog Blue Current Output Current Reference Input CRT Vertical Sync CRT Horizontal Sync or Composite Sync depending on CCR65 [0]0 = CRT Horizontal Sync1 = Composite Sync CRT Interface Video Port Interface P [15:0] PCLK VREF HREF BLANK/TVCLK I/O I/O I/O I/O I/O RGB or YUV input/ RGB digital output Pixel Clock VSYNC input from PC Card or video decoder HSYNC input from...
Page 66
— 64 — PIN NAME I/O DESCRIPTION HVDD MVDD FPVDD VPVDD CVDD AVDD RVDD CVSS AVSS1 AVSS2 RVSS VDD VSS Host Interface VDD on I/O Ring, 3.3V Display Memory Interface VDD on I/O Ring, 3.3V Flat Panel Interface VDD on I/O Ring, 3.3V VPVDD VPort Interface VDD on I/O Ring 3.3V Clock (PLL) Analog Power, 3.3V DAC Analog Power, 3.3V RAM Filtered Palette Power, 3.3V PLL Analog Ground DAC Analog Ground DAC Analog Ground RAM Filtered Palette Ground Digital 3.3V Core Power SupplyDigital 3.3V Internal Memory Power...
Page 67
— 65 — 8-11. ETHERNET CONTROLLER (IC28: LAN91C113) 8-11-1. Pin Assignment 8-11-2. Block Diagram
Page 68
— 66 — Perform proper operation. Return the mode to its original setting. Input correct check number or assign the proper clerk. Reallocate memory. Close cash drawer. Replace journal paper. Replace receipt paper. Check the internal R/J printer. Switch to another mode and then back to the REF/REG– mode again. Input a check number. Input a table number. Enter the number of customers. Input a seat number. Perform stock maintenance. Perform stock maintenance. Re-enter the PLU code. Finalize the...
Page 69
— 67 — ActionMeaningPrompt message E051 CHK/TBL No. is occu- pied. E052 CHK/TBL No. is Busy. E053 CHK/TBL No. is not opened. E054 Out of CHK/TBL No. Range. E056 Store range full. E057 No item exists in detail. E058 Enter post entry item. E059 Press Eat-in or Take-out key. ********** E060 Printer offline. ********** E061 Printer error ********** E061 Printer error. YES:Retry to print. NO :Backup to R/J printer. ESC:Discard data. ********** E062 Printer paper end. ********** E062...
Page 70
— 68 — ActionMeaningPrompt message ********** E073 Your receipt/order may not be issued. YES:Retry to print. NO :Backup to R/J printer. ESC:Discard data. E075 Negative Balance, can- not be finalized. E080 Electronic Journal Full Please clear E-Journal. E082 ***** Illegal Data ***** E083 Cannot create E-Journal. Check Flash memory. ********** E105 Check/TBL tracking Master down. Please call Manager!! YES:Retry for connection. NO :Remove it from system. ********** E106 Check/TBL...