Asus S62 Service Guide

							
                                              BIOS SPECIFICATION            
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Table 5-3. Super I/O GPIO Definition 
PIN# GPI
O 
I/O Type Name Activat
ed 
Level
Description 
23 40 I NC NC N/A 
24 41 I NC NC N/A 
25 42 I NC NC N/A 
27 43 I NC NC N/A 
28 44 I NC NC N/A 
29 45 I NC NC N/A 
30 46 I NC NC N/A 
31 47 I NC NC N/A 
32 10 I NC NC N/A 
33 11 I N/A NC N/A 
34 12 O SIOSMI# Low N/A 
35 13  I NC NC N/A 
36 14 I NC NC N/A 
40 23 I NC NC N/A 
* : NC -> Not Connected, SI -> Selection ID. 
  
						

							
                                              BIOS SPECIFICATION            
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6. Devices 
 
6.0 CPU   
 
  The CPU supported by S62 series system is Intel mobile Yonah dual core processor. 
  The supported frequency is from 1.66GHz to 2.16GHz. 
 
6.1 NORTH BRIDGE (CALISTOGA) 
 
6.1.1 DRB Registers (dram row boundary registers) 
  The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM 
rows with granularity of 128MB. The offset of these registers are 100h~103h. The following is the 
mapping of the registers.  
DRB0(row 0) : 100h 
DRB1(row 1) : 101h 
DRB2(row 2) : 102h 
DRB3(row 3) : 103h 
 
DRB0 = Total memory in row 0 (in 128MB increments) 
DRB1 = Total memory in row 0 + row 1 (in 128MB increments) 
DRB2 = Total memory in row 0 + row 1+ row 2 (in 128MB increments) 
DBR3 = Total memory in row 0 + row 1 + row 2 + row 3 (in 128MB increments) 
 
6.2 SOUTH BRIDGE (ICH7-M) 
 
6.2.1 Hub Interface To PCI Bridge 
  6.2.1.1 Features
 
  The device allows software to “hide” PCI devices(0~5) in terms of configuration space. 
Specifically, when PCI devices(0~5) are hidden, the configuration space is not accessible 
because the PCI IDSEL pin does not assert. The ICH7-M supports the hiding of 7 external 
devices, which matches the number of PCI request/grant pairs, and the ability to hide the 
integrated LAN device by masking out the configuration space decode of LAN controller. 
 
6.2.2 LPC Interface Bridge 
  6.2.2.1 Specific I/O Base Address (PMBASE, GPIOBASE, TCOBASE)
 
 
Two specific I/O Base Addresses are defined in this device – PMBase, GPIOBase . PMBase 
is defined in register 0x40~0x43, also called ACPIBase. The registers offset based on 
PMBase(ACPIBase) are ACPI2.0 compliance. GPIOBase is defined in register 0x48~0x4B. 
OS/Utilities can read/write the related I/O registers based on it to control GPIO function, level 
and interrupt type. Following is the registers setting programmed by BIOS.  
 PMBase Address :  0 800h  
  GPIOBase Address : 0 480h 
  
6.2.2.2 Interrupt
 
 
      This section contains some interrupts configuration and relative PCI registers. 
  6.2.2.2.1 SCI Interrupt
 
  SCI IRQ routing is generally set to  IRQ9. (Power On Default). The relative register is 
PCI register 0x44. IRQ Selections are described below. 
 
Bit2:0 :  000 ->    IRQ9  
						

							
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  001 -> IRQ10 
  010 -> IRQ11 
  011 -> Reserved 
  100 -> IRQ20(Only available if APIC enabled) 
  101 -> IRQ21(Only available if APIC enabled) 
    110 ->  IRQ22(Only available if APIC enabled) 
    111 ->  IRQ23(Only available if APIC enabled) 
 
  6.2.2.2.2 PIRQ[A,C,D,E,F,G,H] Routing Control
 
 
        PIRQA Routing Control Register 0x60 
        PIRQB Routing Control Register 0x61 
    PIRQC Routing Co ntrol Register 0x62 
    PIRQD Routing Co ntrol Register 0x63 
        PIRQE Routing Control Register 0x68 
        PIRQF Routing Control Register 0x69 
        PIRQG Routing Control Register 0x6A 
    PIRQH Routing Co ntrol Register 0x6B 
 
        The description of bit fields are described below. 
     Bit7 :  IRQEN  Interrupt Routing Enable  0 -> The corresponding PIRQ is routed to one of the ISA-compatible 
interrupts specified in bits[3:0] 
1 -> The PIRQ is not routed to the 8259. 
     Bit6~4 : Reserved 
     Bit3~0 : 0000 = Reserved,  1000 = Reserved 
       0001 = Reserved,  1001 = IRQ9 
       0010 = Reserved,  1010 = IRQ10 
       0011 = IRQ3,   1011 = IRQ11 
       0100 = IRQ4,   1100 = IRQ12 
       0101 = IRQ5,   1101 = Reserved 
       0110 = IRQ6,   1110 = IRQ14 
       0111 = IRQ7,   1111 = IRQ15 
 
        Currently BIOS setting is described below (Legacy Mode), 
  Table 6-1 IRQ Configuration Table 
PIN IRQ PIN IRQ 
A 11  E Disabled
B  5 F Disabled
C  6 G Disabled
D  4 H 3 
 
 
6.2.2.3 DMA Configuration
 
  The ICH7-M supports two types of DMA: LPC and PC/PCI. DMA via LPC is similar to ISA 
DMA. LPC DMA and PC/PCI DMA us e the ICH7-M’s DMA Controller. 
 
S62 series uses LPC DMA I/F for Parallel Port because LPC LN47N217 Super I/O is used to 
support those functions. 
      Table 6-3 DMA Resource Allocation 
Channel Allocation ChannelAllocation 
0 Reserved 4 Cascade 
1  Reserved 5 Reserved 
2  Reserved 6 Reserved 
3  ECP 7 Reserved  
						

							
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6.2.3 IDE Controller 
 
6.2.3.1 Function and Feature
 
 
The ICH7-M IDE controller features two sets of interface signals(Primary and Secondary) that 
can be independently enabled, tri-stated or driven low. 
  The ICH7-M IDE controller supports both legacy mode and native mode IDE interface. In 
native mode, the IDE controller is a fully PCI compliant software interface and does not use 
any legacy I/O or interrupt resources. 
     The IDE interface of the ICH7-M can support several types of data transfers: 
     PIO(Programmed I/O)  : CPU is in control of the data transfer. 
     DMA : DMA protocol that resembles the DMA on the ISA bus, although it does not use the 
8237 in the ICH7-M. This protocol offloads the CPU from moving data. This allows higher 
transfer rate of up to 16MB/s. 
     Ultra DMA/33  : DMA protocol that redefines signals on the IDE cable to allow both host and 
target throttling of data and transfer rates of up to 33MB/s. 
    
Ultra DMA/66  : DMA protocol that redefines signals on the IDE cable to allow both host and 
target throttling of data and transfer rates of up to 66 MB/s. 
     Ultra DMA/100 : DMA protocol that redefines signals on the IDE cable to allow both host and 
target throttling of data and transfer rates of up to 100 MB/s. 
 
6.2.4 Audio 
 
S62 series uses the internal High Definition Audio Host Controller of ICH7-M. 
 
 
6.2.5 USB 2.0 (EHCI) 
  6.2.5.1 Overview
 
  The ICH7-M contains an Enhanced Host Controller Interface(EHCI) compliant host controller 
which supports up to 8 USB 2.0 specification compliant root ports. USB 2.0 allows data 
transfer rate up to 480Mbps using the same pins as the 8 USB 1.1 ports. The ICH7-M 
contains port-routing logic that determines whether a USB port is controlled by one of the 
UHCI controllers or by the EHCI controller. USB2.0 based Debug Port is also implemented in 
the ICH7-M. 
  6.2.5.2 – Device Connects operation mode
 
 
      1. Configure Flag = 0 and an USB 1.1-Only Device is connected.  -  In this case, the USB 1.1 Controller is the owner of the port both before and after the connection occurred. The EHC never sees the connection occurred. The UHCI driver 
handles the connection and initialization process. 
2. Configure Flag = 0 and an USB 2.0-Capable Device is connected.  -  In this case, the USB 1.1 Controller is the owner of the port both before and after the 
connection occurred. The EHC never sees the connection occurred. The UHCI driver 
handles the connection and initialization process. Since the USB 1.1 Controller does not 
perform the high-speed chirp handshake, the device operates in compatible. 
      3. Configure Flag = 1 and an USB 1.1-only Device is connected.  -  In this case, the USB 2.0 controller is the owner of the port before the connection occurred. The EHCI driver handles the connection and performs the port reset. After the 
reset process completes, the EHC hardware has cleared(not set) the Port Enable bit in 
the EHC’s PORTSC register. The EHCI driver then writes a 1 to the Port Owner bit in the  
						

							
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same register, causing the USB 1.1 controller to see a connect event and the EHC to 
see an ‘electrical’ disconnect event. The UHCI driver and hardware handle the 
connection and initialization process from that point on. The EHCI driver and hardware 
handle the perceived disconnect. 
      4. Configure Flag = 1 and an USB 2.0-capable Device is connected  -  In this case, the USB 2.0 Controller is the owner of the port before, and remains the 
owner after, the connection occurred. The EHCI driver handles the connection and 
performs the port reset. After the reset process completes, the EHC hardware has set 
the Port Enable bit in the EHC’s PORTSC register. The port is functional at this point. 
The USB 1.1 Controller continues to see an unconnected port. 
 
6.2.5.3 – Device Disconnects operation mode
 
  1. Configure Flag = 0 and the device is disconnected -  In this case, the USB 1.1 Controller is the owner of the port both before and after the  disconnection occurred. The  EHC never sees a device attached. The UHCI driver 
handles disconnection process. 
      2. Configure Flag = 1 and a USB 1.1-capable Device is disconnected.  -  In this case, the USB 1.1 Controller is the owner of the port before the disconnection occurred. The disconnection is reported by the USB 1.1 Controller and serviced by the 
associated UHCI driver. The port-routing logic  in the EHC cluster forces the port owner 
bit to 0, indicating that the EHC owns the unconnected port. 
      3. Configure Flag = 1 and an USB 2.0-capable Device is disconnected.  -  In this case, the USB 2.0 Controller is the owner of the port before, and remains the owner after, the disconnection occurs. The EHCI hardware and driver handle the 
disconnection process. The USB 1.1 Controller never sees a device attached. 
 
6.3 – SMBUS CONTROLLER 
 
6.3.1 – Devices on SMBUS 
 
On S62 series platform, totally there are 3 devices connected to ICH7-M SMBUS. They are 
Clock Generator ICS954310, SODIMM0 and SODIMM1. The slave addresses used by each 
device are listed in Table 6-5. 
  Table 6-5 SMBus Devices Slave Address 
SMBus Device Slave Address 
Clock Generator – ICS954310  D2h 
SODIMM0 – SA2,SA1,SA0 (0,0,0)  A0h 
SODIMM1 – SA2,SA1,SA0 (0,0,1) A2h 
  
						

							
                                              BIOS SPECIFICATION            
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7. CMOS Setup Utility 
 
 S62 series system BIOS allows users to change some system hardware/function settings during 
POST (power on self test) stage, users may hit F2 key to enter SETUP mode in POST, the setup feature 
is categorized into 7 menus described as below: 
 
7.1 MAIN MENU 
 
7.1.1 Main menu: 
Main menu describes system overall information with some user changeable setting, it contains 
below items: 
 
  AMI BIOS: 1.  Version: [xxxx.xxx] -> Current system BIOS version 
2.  VGA BIOS Version: [xxxx.xxxxxx.xxx] -> Current VGA BIOS version 
3.  EC BIOS Version: [xxxxxxxxxx] -> Current EC BIOS version 
Processor  
1. 
Ty p e :  Current CPU model name 
2. Speed:  Current CPU speed 
System Memory  
1. 
Size:  The installed memory size 
 
System Time: [HH/MM/SS] -> Current time 
System Date: [X MM/DD/YYYY] -> Current date 
带格式的: 项目符号和编号
带格式的: 项目符号和编号
带格式的: 项目符号和编号 
						

							
                                              BIOS SPECIFICATION            
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7.2 ADVANCED MENU
: 
 
In advanced menu, users can configure I/O device resource such as I/O base, interrupt vector or 
DMA(Direct Memory Access) channel, some auxiliary settings may be changed as well. Detailed I/O device 
settings are described below: 
 
 
 
Core Multi-Processing :[Enable] -> enable/disable dual core function  
Execute Disable Bit :[Enable] -> enable/disable “Execute Disable” function  
IDE configuration:  See 7.2.1 
Super I/O configuration:  See 7.2.2 
Internal pointing device :[Enable] -> enable/disable TouchPad function 
Internal Numeric Pad Lock [Enable] -> enable/disable “Number Lock” function 
  
						

							
                                              BIOS SPECIFICATION            
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7.2.1 IDE Configuration: 
  7.2.1.1 Primary Master/Slave IDE
 
 
  At system boot, the Intel Ultra ATA Storage Driver configures each ATA/ATAPI device to transfer 
data at particular transfer modes. These transfer modes are defined by ATA standards, and are either 
Programmed I/O (PIO) or Direct Memory Access (DMA or UltraDMA) type transfers.    The Intel Ultra 
ATA Storage Driver usually configures devices for their fastest capable transfer modes; however, there 
may be times when a different (perhaps slower) transfer mode is appropriate for a particular device or 
system configuration.   
For hard disks and CD-ROM drives, BIOS can detect them automatically. Users may enter the 
selected(highlighted) item to get more detailed information. The “Type” field can be set by users to force 
BIOS to apply different setting on the devices when it detects them. There are four types provided by 
BIOS for users. Detailed description for each type is described below   
[Not Installed] : Disabled current device  
[Auto] : To use BIOS default setting 
[CD/DVD] : Apply CD/DVD setting on the device 
[ARMD] : Apply ARMD setting on the device 
 
  
						

							
                                              BIOS SPECIFICATION            
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7.2.2 SuperIO Configuration: 
 
  Users can enable/disable Parallel port function and set Parallel Port mode in this page. The Parallel 
Port modes supported by this system are listed below. 
 
1. SPP/Bi-Directional 
2. EPP/SPP 
3. ECP 
4. ECP/EPP 
  
						

							
                                              BIOS SPECIFICATION            
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7.3 SECURITY MENU: 
 
 BIOS supports two levels of password for security protection: 
Supervisor password
: 
Users may set, change or erase system password, the password data is saved in non-volatile 
device (CMOS), system password check is done during POST(Power On Self Test). The BIOS will 
prompt a dialog message to ask user for password check when:  The system has password stored, and “Password on boot” setting in BIOS SETUP is enabled. 
If password verification fails for 3 times, the system BIOS will halt the machine to inhibit users from 
operating.   
User Password
 
          If your setting of BIOS have been modified by other, You can setting the function [Enable], 
                  and key in your password and confirm, Don’t modify BIOS setting if no password.   
  Hard disk password
: 
Users may set, change or erase hard disk password, the password data is stored in the drive itself, 
the BIOS prompts a dialog message for hard disk password verification whenever it finds the hard disk 
locked in POST.  If hard disk password verification fails for 3 times, the system BIOS will halt the machine to inhibit 
users from operating.