Asus S62 Service Guide

							
                                              BIOS SPECIFICATION            
6-7 
4. BIOS Features 
 
4.1 SYSTEM SECURITY 
 The functions of all passwords are listed in following table. 
  Table 4-1 Password Function 
Password Function 
UserSupervisorHard Disk
Access all setup items    V   
Access only part of setup items  V     
Enter system    V   
Unlock a hard disk      V 
Disable “lock” of a hard disk      V 
 Here are some other rules should be followed: 
 
If supervisor password is enabled, BIOS allows supervisor setting the authority level of the user 
password.  The authority levels of user password are listed below. 
  [No Access]  : User can not access setup menu. 
[View Only]/[Limited]  : User can view setup menu but can not change it. 
[Full Access]  : User can fully access setup menu. 
 
 
4.2 SYSTEM MEMORY 
  The system BIOS automatically detects the amount of memory in the system and configure the DRAM 
timing based on the SPD data of DIMM module and the CMOS settings during the POST 
(Power-On-Self-Test) process. The memory detection only supports DDR2 (Double Data Rate 2) 
SDRAM. 
 
The DRAM clock is routed as follows: 
DIMM 1 uses SCK0/SCK0#, SCK1/SCK1#, SCK2/SCK2#, CS0/CS1, CKE0/CKE1. 
DIMM 2 uses SCK3/SCK3#, SCK4/SCK4#, SCK5/SCK5#, CS2/CS3, CKE2/CKE3. 
 
4.3 LCD BRIGHTNESS CONTROL 
  During POST, the LCD brightness will be set by  BIOS based on the LEVEL INDEX saved in a 
designated extended CMOS byte. If the CMOS’ checksum is incorrect or the CMOS is loaded with setup 
default setting, the LEVEL INDEX will be set to 0Fh in the designated CMOS byte for LCD brightness 
level. Whenever the function hot key Fn+F5 or Fn+F6 is pressed, the brightness level setting should be 
updated to the designated CMOS byte as well as setting the new brightness level. 
 
In S62 series, there are 16 levels for brightness control. The setting values of these 16 levels are 
different between AC-powering and DC-powering modes. Table 4.3 shows the brightness level for each 
stage used by BIOS. 
 
Table 4.3 LCD BRIGHTNESS LEVEL TABLE 
  LCD BRIGHTNESS LEVEL 
LEVEL  INDEX  00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 
AC  15h 24h 33h 42h 51h 60h 6Fh 7Fh 8Fh 9Fh AFh BFh CFh DFh EFh FFh 
DC 0Fh 1Eh 2Dh 3Ch 4Bh 5Ah 69h 78h 87h 96h A5h B4h C3h D2h E1h F0h 
 
 
4.4 SUPER I/O 
  
						

							
                                              BIOS SPECIFICATION            
6-8 
The configuration index/data I/O ports are 2Eh/2Fh. And only Parallel Port function is enabled by BIOS. 
The Parallel Port Mode can be adjusted in BIOS SETUP MENU during POST. Table 4.4 shows all 
modes supported by BIOS. 
Table 4.4 Parallel Port Mode supported by BIOS 
 Parallel Port Mode 
1 SPP/Bi-Directional 
2 EPP/SPP 
3 ECP 
4 ECP/EPP 
 
 
 
4.5 RESOURCE ALLOCATION 
  The system resources are allocated as follows at POST. 
  Table 4-2 System Resource Allocation   
Device Connect Type Resources    
  I/O IRQ DMA Memory 
DMA Controller Static 00~0F, 81~8F, 
C0~DF  - DMA4 - 
Interrupt Controller 
Static 20~21, A0~A1 -  - - 
System Timer Static 40~43  IRQ0  - - 
RTC Static 70~71   IRQ8  - - 
ISA Bus Static -  -  - - 
System Speaker Static 61  -  - - 
System Board Static -  -  - E0000~FFFFF 
FED14000~FE
D19FFF 
PnP Mother Board Static 80  -  - - 
Keyboard Controller Static  60, 62, 64, 66  IRQ1  -  - 
Math Coprocessor Static F0~FF  IRQ13 - - 
Touch Pad Static   IRQ12   
IDE Controller Static 1F0~1F7, 3F6 IRQ14 - - 
USB Host Controller 1 Dynamic E880~E89F  IRQ23  -  - 
USB Host Controller 2 Dynamic E800~E81F  IRQ19  -  - 
USB Host Controller 3 Dynamic E480~E49F  IRQ18  -  - 
USB Host Controller 4 Dynamic E400~E41F  IRQ16  -  - 
USB 2.0 Host Controller Dynamic   IRQ23  -  FEB3BC00~ 
FEB3BFFF 
High Definition Audio 
Controller Dynamic   IRQ16  -   FEB3C000~ 
FEB3FFFF 
SMBus Static 400~041F IRQ5    
Video Controller Static 3B0~3BB, 
3C0~3DF 
D000-D0FF  IRQ16 - D0000000~ 
D7FFFFFF 
FEAF0000~ 
FEAFFFFF 
000A0000~ 
000BFFFF 
CardBus Controller  Dynamic 3E0~3E1 
FE00~FEFF 
FD00~FDFF  IRQ17 - FFEFF000~ 
FFEFFFFF 
FFEFE000~ 
FFEFFFFF 
F9F00000~ 
FDEFFFFF 
DF000~DFFFF 
1394 Controller  Dynamic   IRQ18    FE8FF800~ 
FE8FFFFF  
						

							
                                              BIOS SPECIFICATION            
6-9 
LAN Controller Dynamic D800~D8FF  IRQ16    FE8FEC00~ 
FE8FECFF 
Wireless (802.11abg) Static   IRQ17  FDFFF000~ 
FDFFFFFF 
Ricoh MS Dynamic   IRQ19    FE8FF000~ 
FE8FF0FF 
Ricoh SD Dynamic   IRQ19    FE8FF400~ 
FE8FF4FF 
 Note: The resources of dynamic devices will be changed if users change the settings. The IRQ 9 is 
reserved for SCI of ACPI O.S. 
 
 
4.6 POWER MANAGEMENT 
  In addition to C1, C2/C2E, C3 and C4/C4E states at system full on state, the S62 series platform must 
also support suspend states described in next two sections. 
 
 
4.6.1 ACPI-Enabled Environment 
  Table 4-5 Power Management in ACPI mode 
Power State  Entry Event Source  Wake Up Event Source  
S3 z Standby Timer Time out 
z   Select “Standby” in O.S. 
z  LID switch 
z  Power button  z
  PME (onboard LAN, CardBus card) 
z   High Definition Audio (modem) 
z   USB (USB devices) 
z  RTC Alarm 
z  Internal keystroke 
z  Power button 
S4  z Standby Timer time out 
z   Select “Hibernate” in O.S. 
z  LID switch 
z  Power button  z
  PME (onboard LAN, AC Only) 
z  RTC Alarm 
z  Power button 
Soft Off  z  Select “Shut Down” in O.S. 
z  LID switch 
z  Power button  z
 RTC Alarm  
z  Power button 
z   PME (onboard LAN, AC Only) 
Note : LID won’t trigger a wake up. 
 
4.6.2 ACPI 2.0 
 
  S62 BIOS is ACPI 2.0 compliance. It supports Windows XP Native Processor Performance Control.  In Windows XP, the processor performance control policy is linked to the Power Scheme setting in   
the standard control panel power options applet. No additional UI is employed to set the policy.   
Windows XP defines four control policies for processor performance control: 
   
Constant  Always runs at lowest performance state 
Adaptive  Performance state chosen based on CPU demand 
Degrade  Starts at lowest performance state, then uses linear performance reduction (stop 
clock throttling) as battery discharges 
None   Always runs at highest performance state 
 
 
The following table shows the relationship between the Power Scheme selected and the control 
policy used. 
 
Table 4-6 Power Scheme Table  
						

							
                                              BIOS SPECIFICATION            
6-10 
Power Scheme AC Power DC Power 
Home/office Desk None Adaptive 
Portable/Laptop Adaptive Adaptive 
Presentation Adaptive Degrade 
Always On None None 
Minimal Power Management Adaptive Adaptive 
Max Battery Adaptive Degrade 
 
Three control methods that are implemented to support Windows XP Native Processor   
Performance Control. 
_PCT     Processor performance control object. 
_PSS     The number of supported processor performance states. 
_PPC     Number of performance states currently supported by the platform. 
 
4.6.3 Intel Geyserville iii & Enhanced intel speedstep 
  Geyserville III Technology allows the CPU performance and power consumption levels to be altered while 
the computer is functioning. It alters the performance of the CPU by changing the bus to core frequency 
ratio and CPU voltage. This allows the processor to run at different core frequencies and voltages 
depending upon the system power source(AC or battery in a mobile computer), CPU thermal state, or OS 
policy. Note that the external bus frequency(processor system bus) is not altered; only the internal core 
frequency is changed. In order to run at different speeds, the voltage is altered in step with the bus ratio. 
This works in accordance with voltage reduction technology that allows a given processor to run at higher 
frequency when a higher voltage is applied. The side result is that power is increased in a roughly 
cube-law fashion as the performance is altered in this manner. 
  A software model utilizing Geyserville III is currently referred to as Enhanced Intel SpeedStep Technology. 
This technology is a software mechanism that involves the fundamental mechanics of Intel SpeedStep 
Technology and includes demand-based CPU performance. Demand-based CPU performance uses the 
OS’s knowledge of CPU demand to match the performance of the CPU to the workload of the system. As 
an example, if the highest performance state provided by the CPU is 1600MHz at 18W and the lowest 
performance state provided by the CPU is 800MHz at 6W, with performance states available at each 
100MHz step in between, and the performance required by the system is effectively 1200MHz, a 
Geyserville III technology system can provide the required 1200MHz of performance without waste any 
additional power. 
 
4.6.4 Battery management 
  S62 series supports Lithium-Ion battery pack and a battery calibration menu items in “Power Menu 
Group” for users to calibrate a battery. 
 
4.7 THERMAL AND FAN CONTROL 
 
The settings of cooling policies are based on the CPU temperature read back from the “Intel Digital 
Thermal Sensor” which is embedded in CPU and a external thermal sensor ADT7461. All parameters 
defined in BIOS are showed in Table 4-7.  Table 4-7 FAN Control Mode 
FAN Control Mode EC Linear 
FAN  STEP Numb er   N/A 
 
 
Table 4-8 Parameters for FAN control 
Definition Parameter Base Temperature Thermal Monitor Label 
EC CPU Shutdown 
temperature Threshold 110 CPU EC S/D 
OS Critical Shutdown 
Threshold (_CRT) 105 CPU OS S/D 
OS Passive Cooling 
Threshild (_PSV) 
95 CPU OS PSV  
						

							
                                              BIOS SPECIFICATION            
6-11 
THRM Throttle On 
Threshold 
95 CPU THRM_ON 
THRM Throttle Off 
Threshold 90 CPU THRM_OFF 
Fan Failure Temp Point  65  CPU  FANERR 
Fan Stop Threshold  50  CPU  FSP 
STEP Trip Point 1  55  CPU  TS1 
STEP Trip Point 2  60  CPU  TS2 
STEP Trip Point 3  65  CPU  TS3 
STEP Trip Point 4  70  CPU  TS4 
STEP Trip Point 5  75  CPU  TS5 
STEP Trip Point 6  80  CPU  TS6 
STEP Trip Point 7  85  CPU  TS7 
STEP Trip Point 8  90  CPU  TS8 
Fan Full Run Threshold  95  CPU  FFP 
STEP Trip Pointer 1 
Hysteresis Offset 
3 CPU HYS1 
STEP Trip Pointer 2 
Hysteresis Offset 3 CPU HYS2 
STEP Trip Pointer 3 
Hysteresis Offset 3 CPU HYS3 
STEP Trip Pointer 4 
Hysteresis Offset 
3 CPU HYS4 
STEP Trip Pointer 5 
Hysteresis Offset 3 CPU HYS5 
STEP Trip Pointer 6 
Hysteresis Offset 3 CPU HYS6 
STEP Trip Pointer 7 
Hysteresis Offset 3 CPU HYS7 
STEP Trip Pointer 8 
Hysteresis Offset 3 CPU HYS8 
STEP Trip Pointer 1 Duty 73  CPU  DA1 
STEP Trip Pointer 2 Duty 95  CPU  DA2 
STEP Trip Pointer 3 Duty 117  CPU  DA3 
STEP Trip Pointer 4 Duty 139  CPU  DA4 
STEP Trip Pointer 5 Duty 161  CPU  DA5 
STEP Trip Pointer 6 Duty 183  CPU  DA6 
STEP Trip Pointer 7 Duty 205  CPU  DA7 
STEP Trip Pointer 8 Duty 227  CPU  DA8 
Rising Limit Range 1  6  CPU  Addscl1 
Rising Limit Range 2  12  CPU  Addscl2 
Rising Limit Range 3  22  CPU  Addscl3 
Rising Limit Range 4  24  CPU  Addscl4 
Rising Limit Value 1  1  CPU  AddDA1 
Rising Limit Value 2  2  CPU  AddDA1 
Rising Limit Value 3  4  CPU  AddDA1 
Rising Limit Value 4  6  CPU  AddDA1 
Falling Limit Range 1  6  CPU  Decscl1 
Falling Limit Range 2  12  CPU  Decscl2 
Falling Limit Range 3  22  CPU  Decscl3 
Falling Limit Range 4  24  CPU  Decscl4 
Falling Limit Value 1  1  CPU  DecDA1 
Falling Limit Value 2  2  CPU  DecDA2 
Falling Limit Value 3  4  CPU  DecDA3 
Falling Limit Value 4  6  CPU  DecDA4 
  
						

							
                                              BIOS SPECIFICATION            
6-12 
 
4.8 NUMERIC PAD CONTROL 
 
There is a control switch in setup menu item for enabling or disabling numeric pad lock of an 
internal keyboard. 
 
4.9 TOUCH PAD CONTROL 
  In ACPI environment, BIOS will notify ATK0100 to enable/disable Touch Pad when the Touch Pad 
Enable/Disable instant key is pressed. 
 
4.10 HOTKEY USAGE DURING POST 
 
The hot keys used during POST are: 
 Hotkey Description 
1  TAB  Switch from “LOGO” screen to “message” screen, i.e. from “silent” mode  to “verbose” mode 
2  ESC  Pop up “BOOT SELECTION MENU” 
3  F1  Load optimum CMOS setting and continue booting process if CMOS checksum is incorrect 
4  F2  Enter setup menu 
  
						

							
                                              BIOS SPECIFICATION            
6-13 
5. GPIO Pin Assignment 
 
The following tables are the definition of GPIO pins. Some of GPIO pins need to be initialized by system BIOS 
and some of them need the driver to support. Please check the Description column for reference. 
 Table 5-1. ICH7-M GPIO Definition 
GPIO Ty p e  Name Usage PowerDescription 
0 I GPIO00/BM_BUSY# BM_BUSY# M Native Function 
1 I GPIO01/REQ5# REQ5# M Native Function 
2 I GPIO02/PIRQE# PIRQE# M Native Function 
3 I GPIO03/PIRQF# PIRQF# M Native Function 
4 I GPIO04/PIRQG# PIRQG# M Native Function 
5 I GPIO05/PIRQH# PIRQH# M Native Function 
6 I/O GPIO06  N/A  M   
7   I GPIO07 RF_OFF_SW#M N/A 
8 I GPIO08 EXTSMI# 
 
R From KBC, it is to notify system an 
external SMI occurred. 
9  I GPIO09  SATA_DET#0  R  SATA indicator 
10 I/O GPIO10  N/A  R   
11 I GPIO11/SMBALERT# SMBALERT# R Native Function 
12 I GPIO12 KBDSCI R From KBC, runtime and wake up event 
will be sent to system through this pin. 
13  I  GPIO13  SIO_SMI#  R  Super I/O SMI event 
14 I/O  GPIO14  PWRLED_1Hz R  1Hz On/Off cycle for Power LED 
15 I/O GPIO15  N/A  R   
16 O GPIO16/GNT6# GNT6# M Native Function 
17 O GPIO17/GNT5# GNT5# M Native Function 
18 O GPIO18/STP_PCI# STP_PCI# M This signal is an output to the external 
clock generator for it to turn off the PCI 
clock. Used to support PCI CLKRUN# 
protocol. 
19 I GPIO19/SATA1GP SATA1GP M N/A 
20 O GPIO20/STP_CPU# STP_CPU# M Output to the external clock generator 
for it to turn off the CPU clock. Used to 
support the C3 state. 
21 I GPIO21/SATA0GP SATA0GP M Native Function 
22 I GPIO22/REQ4# REQ4# M Native Function 
23 I/O GPIO23/LDRQ1# LDRQ1# M Native Function 
24  O  GPIO24  802_LED_EN# R  Enable Wireless LED 
25 O  GPIO25  CB_SD#  R  Disable CardBus function. 
26 I/O GPIO26    R   
27 O GPIO27/EL_STATE0 BT_LED_EN# R Enable BlueTooth LED 
28 I/O GPIO28/EL_STATE1    R   
29 I GPIO29/OC#5 OC#5 R N/A 
30 I GPIO30/OC#6 OC#6 R N/A 
31 I GPIO31/OC#7 OC#7 R N/A 
32 O GPIO32/CLKRUN# PM_CLKRUN#M Used to support PCI clock run protocol. 
Connects to PCI devices that need to 
request clock re-start, or prevention of 
clock stopping. 
33  O GPIO33/AZ_DOCK_EN#  BT_ON  M  Turn On/Off BlueTooth 
34 O GPIO34/AZ_DOCK_RST# WLAN_ON#  Turn On/Off Wireless LAN 
35 O GPIO35/SATACLKREQ# SATACLKREQ#M Native Function 
36 I GPIO36/SATA2GP SATA2GP M Native Function 
37  I GPIO37/SATA3GP  SATA3GP  M  Native Function 
38 I GPIO38  PCB_ID0  M  1st PCB ID pin 
39 I GPIO39  PCB_ID1  M  2nd PCB ID pin 
40 N/A GPIO40 N/A N/A N/A  
						

							
                                              BIOS SPECIFICATION            
6-14 
41 N/A GPIO41 N/A N/A  N/A 
42 N/A GPIO42 N/A N/A N/A 
43 N/A GPIO43 N/A N/A N/A 
44 N/A GPIO44 N/A N/A N/A 
45 N/A GPIO45 N/A N/A N/A 
46 N/A GPIO46 N/A N/A N/A 
47 N/A GPIO47 N/A N/A N/A 
48 O GPIO48/GNT4# GNT4# M Native Function 
49 O CPUPWRGD H_PWRGD M Processor I/F power well 
1. Power field: M -> main power will, R-> resume power well 
2. pins in light gray: used as Native Function pins 
3. pins in gray: no function 
  
						

							
                                              BIOS SPECIFICATION            
6-15 
 
Table 5-2. KBC GPIO Definition 
Port I/O 
Ty p e  
Input Pin 
Pull-up/down 
Name Output Pin 
Default Value
Description 
A.0 O    BRIGHT_PWM  Low  Used to adjust LCD backlight 
A.1   NC   
A.2 O    BAT1_CNT1#  High  BAT1_CNT1# signal to battery 
A.3   NC   
A.4 O    CHG_LED_UP#  High  When battery is charging, charging LED will 
be turned on by this pin 
A.5 O    PWR_LED_UP#  High  When system is powered on, power LED will 
be turned on by this pin 
A.6 O    BATSEL_3S#  Low  BATSEL_3S# signal to battery charging 
circuit 
A.7 O    LCD_BACKOFF#  Low  For LCD back light control 
B.0 O    NUM_LED  Low  Number Lock Indicator 
B.1 O    CAP_LED  Low  CAP Lock Indicator 
B.2 O    SCRL_LED  Low  Scroll Lock Indicator 
B.3  A    SMCLK_BAT    SMBUS clock pin (to battery) 
B.4 A    SMDATA_BAT    SMBUS data pin (to battery) 
B.5 O    A20GATE  Low  A20 is gated by this pin from KBC 
B.6 O    RCIN#  Low  System reset signal from KBC 
B.7 O    THRO_CPU  Low  This pin is used for CPU throttling. To set it 
high to enable CPU throttling. To set it low to 
disable CPU throttling. 
C.0   NC   
C.1 A    SMB1_CLK    SMBUS1 clock pin (to thermal sensor) 
C.2 A    SMB1_DAT    SMBUS1 data pin (to thermal sensor) 
C.3 O    EMAIL_LED#  High  Email incoming Indicator 
C.4  A    ACIN_OC#    For AC adapter in/out detection 
C.5 O    OP_SD#  Low  EC MUTE on/off switch pin 
C.6  A    BAT_IN_OC#    For battery in/out detection 
C.7   NC   
D.0  I    PM_SUSB#    PM_SUSB signal from ICH7-M 
D.1 I    PM_SUSC#    PM_SUSC signal from ICH7-M 
D.2 A    PLT_RST#    Platform reset signal from ICH7-M 
D.3 O    KB_SCI#  HIGH  SCI pin to notify system at runtime or wake 
up events from KBC 
D.4   NC   
D.5   NC   
D.6 A   FAN0_TACH   FAN0 tachometer 
D.7   NC   
E.0  I  Pull-Up  EMAIL#    For Email instant key 
E.1 I  Pull-Up  INTERNET#    For Internet instant key 
E.2 I  Pull-Up  MARATHON#    For Marathon instant key 
E.3 I  Pull-Up  DISTP#    For Padlock instant key 
E.4 A    PWRSW#_EC    For Power Button 
E.5   NC   
E.6  I    LID_EC#    For LID Event 
E.7   NC   
F. 0  O    EXT_PS2_CLK  Low  External PS2 clock pin 
F. 1  O    EXT_PS2_DAT  Low  External PS2 data pin 
F. 2    NC   
F. 3    NC   
F. 4   A    TPAD_CLK    Touch Pad clock pin 
F. 5  A    TPAD_DAT    Touch Pad data pin 
F. 6   I  Pull-Up  PWRLMT#    For Power Limit function 
F. 7    NC    
						

							
                                              BIOS SPECIFICATION            
6-16 
G. 0  A  FA16  To FLASH I/F 
G. 1  A  FA17  To FLASH I/F 
G. 2  A  FA18  To FLASH I/F 
G. 3    NC   
G. 4  O    THRM_CPU#  Low  THRM_CPU# signal from external thermal 
sensor 
G. 5    NC   
G. 6  I    PMTHERM#  Low  PMTHERM# signal to ICH7-M 
G. 7    NC   
H.0 O    VSUS_ON  Low  VSUS_ON signal to power circuit 
H.1  I    VSUS_GD#    VSUS_GD# signal from power circuit 
H.2 I    IMVPOK#    IMVPOK# signal from power circuit 
H.3 O  PM_PWRBTN# High PM_PWR BTN# signal to ICH7-M 
H.4 O    SUSC_EC#  Low  SUSC_EC# signal to ICH7-M 
H.5 O    SUSB_EC#  Low  SUSB_EC# signal to ICH7-M 
H.6 O   CPU_VRON Low CPU_VRON  signal to power circuit 
H.7 O    PM_RSMRST#  Low  At boot, KBCRSM needs to be set low for 
normal operation 
I.0 O    ICH_PWROK  Low  ICH_PWROK signal to ICH7-M 
I.1 O    VSUS_ON  High  VSUS_ON signal to power circuit 
I.2 O    BAT1_CNT2#  Low  BAT1_CNT1# signal to battery 
I.3 O    CHG_EN#  High  For Battery Charge function 
I.4 O    PRECHG  Low  For Batter PreCharge function 
I.5 O    BAT_LL  Low  When the pin is set as low, it represents that 
battery is in very low capacity. 
I.6 O    BAT_LEARN  Low  This pin is used for battery learning (refresh). 
To set it low for battery charging. To set it 
high for battery discharging. 
1. Name field: NC -> not connected