Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-129  
15.5.5.13 SIFCCON1 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01E4, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved (should be 0)=0=
SYS_WDATA=[23:0]=RW=Controls the LCD i80 System Interface Write Data.=0=
=
15.5.5.14 SIFCCON2 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01E8, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24]...

 
 
0 = Non-invert 
1 = Invert 
RSVD [15:9] –=Reserved=0=
CRCMXSEL=[8:4]=RW=Specifies the CRC Data Mux. Selection.=
Select n th=(0 to 23) Video data (VD) for CRC.=0=
RSVD=[3]=–=Reserved=0=
CRCCLKEN=[2]=RW=
CRCCLK Enable control=
0 = Disable=
1 = Enable=
0=
CRCSTART_F [1] RW 
CRC start control  
0 = Disable CRC logic at next frame 
1 = Enable CRC logic at next frame 
0 
CRCEN [0] RW 
Enables the CRC check 
0 = Disables CRC check 
1 = Enables CRC check 
0 
 
15.5.5.17 I80IFCONn (n = 0 to 11) 
 Base...

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-1  
16 Analog to Digital Converter (ADC) 
This chapter describes the functions and usage of ADC  
 
16.1 Overview 
The 10-bit or 12-bit CMOS Analog to Digital Converter (ADC) comprises of 8-channel analog inputs. It converts 
the analog input signal into 10-bit or 12-bit binary digital codes at a maximum conversion rate of 1MSPS with 
5MHz A/D converter clock. A/D converter operates with on-chip sample-and-hold function. ADC...

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-2  
16.3 ADC Interface Operation 
16.3.1 Block Diagram ADC 
Figure 16-1 is the functional block diagram of A/D converter.  
 
    Figure 16-1   ADC Functional Block Diagram 
 ADC input 
control
Interrupt 
generation
Waiting for interrupt
VDDA_ADC
8:1
MUX
A/D
Converter
ADC
interface
INT_ADC0
AIN0
AIN5
AIN4
AIN3
AIN2
AIN1
AIN6
AIN7  

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-3  
16.4 Function Descriptions 
16.4.1 A/D Conversion Time 
When the PCLK frequency is 66 MHz and the prescaler value is 65, total 12-bit conversion time is as follows. 
 A/D converter freq. = 66 MHz/(65 + 1) = 1 MHz 
 Conversion time = 1/(1 MHz/5 cycles) = 1/200 kHz = 5 s 
NOTE: This A/D converter was designed to operate at maximum 5 MHz clock, so the conversion rate can go up to 1MSPS. 
 
16.4.2 ADC conversion Mode  
The...

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-4  
16.5 ADC Input Clock Diagram 
 
    Figure 16-2   Input Clock Diagram for ADC PCLK1/NADCCLK
ADCCON[13:6]  

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-5  
16.6 I/O Descriptions 
Signal I/O Description Pad Type 
AIN[7] Input ADC Channel[7] Analog input Xadc0AIN_7 Analog 
AIN[6] Input ADC Channel[6] Analog input Xadc0AIN_6 Analog 
AIN[5] Input ADC Channel[5] Analog input Xadc0AIN_5 Analog 
AIN[4] Input ADC Channel[4] Analog input Xadc0AIN_4 Analog 
AIN[3] Input ADC Channel[3] Analog input Xadc0AIN_3 Analog 
AIN[2] Input ADC Channel[2] Analog input Xadc0AIN_2 Analog 
AIN[1]...

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-6  
16.7 Register Description 
16.7.1 Register Map Summary 
 Base Address = 0x12D1_0000 
Register Offset Description Reset Value 
ADCCON 0x0000 ADC control register 0x0000_3FC4 
RSVD 0x0004 Reserved 0x0000_0058 
ADCDLY 0x0008 ADC Start or interval delay register 0x0000_00FF 
ADCDATX 0x000C ADC conversion data  Undefined 
RSVD 0x0010 Reserved Undefined 
RSVD 0x0014 Reserved 0x0000_0000 
CLRINTADC 0x0018 Clear INT_ADC0...

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-7  
16.7.1.1 ADCCON 
 Base Address: 0x12D1_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_3FC4 
Name Bit Type Description Reset Value 
RES [16] RW 
ADC output resolution selection 
0 = 10-bit A/D conversion 
1 = 12-bit A/D conversion 
0 
ECFLG [15] RW 
End of conversion flag(Read only) 
0 = A/D conversion in process 
1 = End of A/D conversion 
0 
PRSCEN [14] RW 
A/D converter prescaler enable 
0 = Disable 
1 =...

Samsung Confidential  
Exynos 5250_UM 16 Analog to Digital Converter (ADC) 
 16-8  
16.7.1.2 ADCDLY 
 Base Address: 0x12D1_0000 
 Address = Base Address + 0x0008, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
DELAY [15:0] RW 
ADC conversion is delayed by counting this value. 
Counting clock is PCLK.  
 ADC conversion delay value. 
NOTE: Do not use zero value(0x0000) 
00ff 
 
 
16.7.1.3 ADCDATX 
 Base Address: 0x12D1_0000 
 Address = Base Address + 0x000C, Reset Value = Undefined...