NEC Mcu 5000a Multipoint Control Unit Equipment Manual

NECA 340-414-100 Revision 2.0Page 29
MCU 5000A Multipoint Control Unit General Description Manual
(2) Table 4-5 and Fig. 4-4 show RS-422 LIF Connector pin assignment.
Figure 4-4:   RS-422 LIF (CH1 to CH16) Connector Pin Assignment
Table 4-5: RS-422 LIF (CH1 to CH16) Signal Assignment
PIN NO. SIGNAL NAME I /O REMARKS PIN NO. SIGNAL NAME I /O REMARKS
1 SHIELD Cable shield 9 T (B)+ OUT Transmitting (B)
2 T (A)_ OUT Transmitting Data (A) 10 C (B)+ OUT Control (B)
3 C (A)_ OUT Control (A) 11 R (B)+ IN...

Page 30NECA 340-414-100 Revision 2.0
General Description Manual MCU 5000A Multipoint Control Unit
(3) Fig. 4-5 shows the Block diagram of RS-422 LIF unit.
Figure 4-5:   Block Diagram of RS-422 LIF Unit
MTSCLIF
LEVEL CONV
RATE CONV
LIF
LEVEL CONV
RATE CONV
LIF
LEVEL CONV
RATE CONV
LIF
LEVEL CONV
RATE CONV
IN    OUT
14      14
OUT   IN
  14    14
IN    OUT
14      14
OUT   IN
  14    14
IN    OUT
14      14
OUT   IN
  14    14
IN    OUT
14      14
OUT   IN
  14    14
DELAY
&
MUXH221
SYNC DET
H221
SYNC DET...

NECA 340-414-100 Revision 2.0Page 31
MCU 5000A Multipoint Control Unit General Description Manual
C:  H0-INF Unit General
4.10
The H0-INF unit receives 1.5 Mbps data signal from ISDN line.  After 
extracting the clock pulse in IPAT, bipolar to unipolar conversion is executed, and  
sends it to ACFA.  ACFA performs frame synchronization, internal data high-way 
bit rate conversion, and detection of transmission line failure for the data signal, 
and sends it to MTSC.  MTSC performs the line setting with...

Page 32NECA 340-414-100 Revision 2.0
General Description Manual MCU 5000A Multipoint Control Unit
4.14
Fig. 4-6 shows block diagram of H0-INF unit.
Figure 4-6:   Block Diagram of H0-INF Unit
PORT2
PORT1RELAY
RELAYIPAT#2
IPAT#1AC FA # 2
AC FA # 1MTSC#4
MTSC#3
MTSC#2
MTSC#1 ICU
DEBUG2
DEBUG1LED
LED DIP SW
DIP SWPIIFC
#2
PIIFC
#1CPU
G/A
ROM
RAM
HSCX
CPU
G/A
ROM
RAM
HSCX
DIP SW
LED
44
4
44
4
4
4
4
4
H221
MUX
LDRLDS
LB
CLOCK (4M, 8K)
+5V
CPU BUS
INT (TS24)
DCL (2M)
DCL (2M) (TS24) 232C
232C
DCL (2M) 

NECA 340-414-100 Revision 2.0Page 33
MCU 5000A Multipoint Control Unit General Description Manual
H0-INF Unit Interface
(1) Table 4-6 shows the electrical specification.  This interface conforms to 
ITU-TS G.703, I.431.
(2) Table 4-7 and  Fig. 4-7 shows H0-INF Connector Pin Assignment.
Figure 4-7:   H0-INF (CH1 to CH16) Connector Pin Assignment
Table 4-6: Electrical Specification
ITEM SPECIFICATION
Transmission Rate 1.544 Mbps ±50 ppm (Data rate: 64  to 1536 kbps, 64k step)
Line code AMI (B8ZS)
Frame...

Page 34NECA 340-414-100 Revision 2.0
General Description Manual MCU 5000A Multipoint Control Unit
D: EC H211 MUX 
UnitGeneral
4.15
In EC H211 MUX unit, the received data signal from terminal CODEC via LIF 
unit is synchronized with H.221 or multiframe.  This unit also demultiplexes the 
synchronized data signal to the audio coding data, video coding data, and MCU Control 
Data. This unit  also multiplexes the sum-processed audio coding signal in A CODEC 
and A SUM units, converted video coding signal in...

NECA 340-414-100 Revision 2.0Page 35
MCU 5000A Multipoint Control Unit General Description Manual
4.17
Fig. 4-8 shows block diagram of EC H221 MUX unit.
Figure 4-8:   Block Diagram of EC H221 MUX Unit
LD1 IN
LD2 IN
LD3 IN
LD4 IN
LD1 OUT
LD2 OUT
LD3 OUT
LD4 OUTDIST4-1
SEL
TO /F RO M
LIF
(LD S/R)MTSC
H221
SYNCHRONIZATION
DETECTOR
CPU
CPU INFDELAY
CONTDMUX
PG
MUX4-1
SEL DIST
LD1 OUT
LD2 OUT
LD3 OUT
LD4 OUT
LD1 IN
LD2 IN
LD3 IN
LD4 IN
V SW/LSD
A CODEC
(MD-R)
V SW/LSD
(LSD)
V SW/LSD
A CODEC
(MD-S)
FROM PG/S...

Page 36NECA 340-414-100 Revision 2.0
General Description Manual MCU 5000A Multipoint Control Unit
E:  V SW/LSD IF Unit General
4.18
The V SW/LSD IF unit switches the video signal between RD IN and SD 
OUT from EC H221 MUX unit.  This unit receives the low-speed data 
demultiplexed from service channel in EC H221 MUX unit, and the proceed low-
speed data is sent back to the EC H221 MUX unit.
Functions
(1) V SW
This unit sends the video signal of the transmitting teleconference 
terminal received from the...

NECA 340-414-100 Revision 2.0Page 37
MCU 5000A Multipoint Control Unit General Description Manual
4.19
Fig. 4-9 shows the block diagram of V SW/LSD IF unit.
Figure 4-9:  Block Diagram of V SW/LSD IF Unit (1of 2)
DBDIN
OUT
TSC48
4
4 MTSC
MTSC
DIN
OUT
TSC
DETECTING
ERROR
TDBMDR
MDS
8
4
4
8
8
8
8
8
8D HC151
Y
S
C
B
A
Y G2
C
B
A
Y G2
C
B
A TDH
TEST
VLB HC138 HC151
D W
S
C
B
A TSC 4MCK -
2MCK -
8
4
4MDS
DQ HC273
TDS PN
PAT T E R N
CHECKER
BURST
CLK
BURST
CLK
PN
PAT T E R N
CHECKERTSC
TEST:  TESTING CONTROL...

Page 38NECA 340-414-100 Revision 2.0
General Description Manual MCU 5000A Multipoint Control Unit
Figure 4-9:  Block Diagram of V SW/LSD IF Unit (2 of 2)
R x D1
T x D1
T x CK1
R x D2
T x D2
T x CK2H
S
C
X
R x D1
T x D1
T x CK1
R x D2
T x D2
T x CK2H
S
C
X
R x D1
T x D1
T x CK1
R x D2
T x D2
T x CK2H
S
C
X
R x D1
T x D1
T x CK1
R x D2
T x D2
T x CK2H
S
C
X
D71054 DIST
SEL
LSD R IN
LSD S OUT
V11 CLK
2M CLK
4M CLK
CN3LSD R0
LSD S0
LSD CK0
CPU BUS