Motorola Xtl5000 Detailled 6881096c74 B Manual

							6881096C74-BMay 25, 2005
Theory of Operation: Receiver Back-End3-25
3.5.4.1  Intermediate Frequency (IF) Filter
The XTL 5000 radio uses two leadless, surface-mount, two-pole, third-overtone, quartz crystal filters 
(B6350, B6351) separated by a 20 dB gain IF amplifier. The filter is centered at 73.35 MHz. This 
narrow-bandpass filter gives the radio its adjacent-channel and alternate-channel rejection 
performance. Components L6350, L6351, L6352, L6353, C6351, C6352, C6353, C6355, C6356, 
and C6357 are used as impedance-matching networks. Components L6355, R6354, R6352, R6353, 
C6354, and R6350 are used for biasing and stabilizing the transistor Q6350. Component C6358 
bypasses the DC supply. L6355 is an RF choke.
3.5.4.2  ABACUS III IC (U6000)
The receiver back-end is designed around the ABACUS III (AD9874 IF digitizing subsystem) IC and 
its associated circuitry. The AD9874 (Figure 3-20) is a general-purpose, IF subsystem that digitizes a 
low-level, 10–300 MHz IF input with a bandwidth up to 270 kHz. The signal chain of the AD9874 
consists of a variable gain, low-noise amplifier, a mixer; a bandpass, sigma-delta, A/D converter; and 
a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit 
provides the AD9874 with 12 dB of continuous gain adjustment. The high dynamic range and 
inherent anti-aliasing provided by the bandpass, sigma-delta converter allow the AD9874 to cope 
with blocking signals 80 dB stronger than the desired signal. Auxiliary blocks include clock and LO 
synthesizers, as well as an SPI port. Input signal RXIF is the 73.35 MHz IF from the IF filter in the 
receiver front-end.
Components C6000, C6001, and L6000 match the input impedance from 50 ohms (IF Filter 
terminating impedance) to the ABACUS III IC input IFIN. Formatted SSI (synchronous serial 
interface) data is output to the Patriot microcontroller IC for DSP processing on ports FS, DOUTA, 
and CLKOUT. Control logic is sent to the ABACUS III IC from the Patriot microcontroller via the SPI 
lines (PC, PD, PE).
Figure 3-20.  ABACUS III (AD9874) IC Functional Block Diagram from Data Sheet (700–800 MHz)
IFIN
FREF-16dB
LNA
LO
Synth.Sample Clock
Synthesizer
CLK VCO and
Loop Filter LO VCOand
Loop FilterVoltage
Reference DAC AGC
ADCDecimation
FilterFormatting/SSI
Control Logic f
CLK = 13-26MHz
SPIDOUTB DOUTA
FS
CLKOUT
MXON MXOP
IF2P
IF2N
GCP
GCN LOP IOUTL
LON
IOUTC
CLKP
CLKN
VREFP
VCM
VREFN
PC
PD
PE
SYNCB
MAEPF-27817-O
AD9874 
						

							May 25, 20056881096C74-B
3-26Theory of Operation: Transmitter
3.5.4.2.1  Second Local Oscillator (LO)
The ABACUS III IC local oscillator (LO) synthesizer controls the second LO. Signal FREF is the 
16.8 MHz reference from the frequency generation unit (FGU). The second LO frequency is 
75.6 MHz by default, or 71.1 MHz in special cases as necessary to avoid radio self-quieters. The 
second LO signal mixes with IFIN to produce a 2.25 MHz final IF. The external VCO consists of 
transistor Q6000, together with its bias and instability network and tank elements. Darlington 
transistor Q6001 along with C6024 and C6025 form an active DC filter. The 2nd order loop filter is 
comprised of C6056, C6057, and R6019.
3.5.4.2.2  Sampling Clock Oscillator
The ABACUS III IC sampling clock synthesizer, at Fclk=18 MHz (IF2=Fclk/8, where Fclk is the clock 
rate), utilizes a negative-resistance core that is internal to the ABACUS III IC which, when used in 
conjunction with an external LC tank (made up of L6003 and C6031) and a varactor (D6030), serves 
as the VCO.
3.6 Transmitter
This section of the theory of operation provides a detailed circuit description of the transmitter, which 
includes the RF power amplifier (RFPA), output network (ON), and power control.
When reading the theory of operation, refer to the appropriate schematic and component location 
diagrams located in “Chapter 7. Schematics, Component Location Diagrams, and Parts Lists”. This 
detailed theory of operation will help isolate the problem to a particular component. However, first 
use the ASTRO Digital XTL 5000 VHF/UHF Range 1/UHF Range 2/700–800 MHz Mobile Radio 
Basic Service Manual to troubleshoot the problem to a particular section.
3.6.1 VHF (136-174 MHz) Band
3.6.1.1  50-Watt Transmitter
The following text discusses the 50-W transmitter.
3.6.1.1.1  RF Power Amplifier (RFPA)
The RFPA consists of three gain stages, which are shown in Figure 3-21.
Figure 3-21.  50-Watt RF Power Amplifier (RFPA) Gain Stages (VHF)



	









 
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							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-27
First Stage
The RFPA first stage provides gain that is determined by the control voltage, RFPA_CNTRL. This 
control voltage is generated in the power control section and is a function of the final-stage output 
power, temperature, and current, as well as the control and A+ voltage levels. See “3.6.1.4. Power 
Control (for 50W and 100W Transmitter)” on page 3-30 for a detailed explanation of the power 
control section.
The 2 mW TX_INJ signal is routed to the U3550 first-stage device (Pin 16, RFIN) via C3500 to an 
integrated, wide-band input match. U3550 is a two-stage LDMOS device with a bandpass interstage 
match consisting of C3503, L3502, C3504, R3501 and C3505 routed between VD1 (pin 14) and G2 
(pin 11). L3501 and L3503 provide the K9.1V drain bias voltage for the first and second stages to 
VD1 (pin 14) and RFOUT1/2 (pins 6 and 7), respectively. The RFPA_CNTRL gate bias is provided to 
both stages internally via VCNTRL (pin 1). Both U3550 stages are operated Class A.
Driver Stage
C3521, L3520, C3520, and a transmission line form a low-pass, interstage match that transfers 
power to the Q3530 LDMOS transistor. R3520-3 provide device stability, and R3524 and C3522 
supply the VGBIAS2 gate bias. L3530-1, R3530-1, C3530, C3531, C3536 and C3537 form the A+ 
drain bias circuit. Q3530 is operated Class AB.
Final Stage
C3532-4, and transmission lines form a bandpass. R3532-8 provide stability for Q3550. R3540 and 
C3535 supply the VGBIAS1 gate bias to Q3550. L3549-51, C3548-51, and R3551 form the A+ drain 
bias circuit.
C3552-9 and transmission lines form a low-pass. Q3550 operate Class AB.
R3550, R3560, C3563, and U3561 comprise the final-stage, current-sense circuit that generates the 
VCURRENT voltage proportional to the final stage current. R3560 sets the circuit gain. U3560 
generates the VTEMP voltage, which is proportional to the final-stage temperature. 
						

							May 25, 20056881096C74-B
3-28Theory of Operation: Transmitter
3.6.1.2  100-Watt Transmitter
The following text discusses the 100-W transmitter.
3.6.1.2.1  RF Power Amplifier (RFPA)
The RFPA consists of three gain stages, which are shown in Figure 3-22.
Figure 3-22.  100-Watt RF Power Amplifier (RFPA) Gain Stages (VHF)
First Stage
The RFPA first stage provides gain that is determined by the control voltage, RFPA_CNTRL. This 
control voltage is generated in the power control section and is a function of the final-stage output 
power, temperature, and current, as well as the control and A+ voltage levels. See “3.6.1.4. Power 
Control (for 50W and 100W Transmitter)” on page 3-30 for a detailed explanation of the power 
control section.
The 2 mW TX_INJ signal is routed to the U3500 first-stage device (Pin 16, RFIN) via C3500 to an 
integrated, wide-band input match. U3550 is a two-stage LDMOS device with a bandpass interstage 
match consisting of C3502 and L3501 routed between VD1 (pin 14) and G2 (pin 11). L3501 and 
L3500 provide the K9.1V drain bias voltage for the first and second stages to VD1 (pin 14) and 
RFOUT1/2 (pins 6 and 7), respectively. The RFPA_CNTRL gate bias is provided to both stages 
internally via VCNTRL (pin 1). Both U3500 stages are operated Class A.
Driver Stage
C3521, L3520, C3520, and a transmission line form a low-pass, interstage match that transfers 
power to the Q3520 LDMOS transistor. R3520-5 provide device stability, and R3526 and C3522 
supply the VGBIAS2 gate bias. L3521, R3528, C3525, C3524, C3536, L3522 and R3527 form the 
A+ drain bias circuit. Q3520 is operated Class AB.
50W
RFPA_out
100W
50W Q3540
Q3541 Q352010W
5W
A+
A+ A+
Vg_bias
Vg_bias Vg_bias 100mW
RFPA_cntrl Tx_inj
2mW
Key9.1V
U3500
30C65
5W 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-29
Dual Final Stage
C3540-1, C3543-4 and transmission lines form a bandpass. R3541-8 provide stability for Q3540. 
R3550-7 provide stability for Q3541. R3540 and R3568 supply the VGBIAS1 gate bias to Q3540. 
R3569 and R3558 supply the VGBIAS2 gate bias to Q3541. L3540-4 and C3560-1 form the A+ drain 
bias circuit. C3548-55 and transmission lines form a low-pass. Q3540-1 operate Class AB.
R3560-1, C3561, and U3561 comprise the final-stage, current-sense circuit that generates the 
VCURRENT voltage proportional to the final stage current. R3564 sets the circuit gain. U3560 
generates the VTEMP voltage, which is proportional to the final-stage temperature.
3.6.1.3  Output Network (ON) - (for 50W and 100W Transmitter)
The ON consists of the antenna switch, harmonic filter, and power detector (see Figure 3-23).
Figure 3-23.  Output Network Components (VHF)
Antenna Switch
The antenna switch functions in two modes, which are determined by the presence of K9.1V. The 
K9.1V switch bias is applied via L3700, L3731-2, and C3702. When K9.1V is present, the switch is in 
TX mode. D3701-2 and D3704 are forward biased forming a low-loss path from the RFPA final stage 
to the harmonic filter and a 60 dB isolation path between the RFPA final stage and the RX front-end. 
Isolation is achieved via a quarter-wave transmission line between D3701 and D3702. D3701-4 
serves as an ESD protection circuit against ESD discharge on the antenna connector.
When K9.1V is absent, the switch is in RX mode. D3701 and D3702 are reverse biased forming a 
low-loss path from the harmonic filter to the RX front-end and a 60 dB isolation path from the 
harmonic filter to the RFPA final stage. Isolation is achieved via the D3701 off resistance.
Harmonic Filter
L3720-7, C3720-3, form the twelve-element, low-pass harmonic filter. The filter attenuates 
harmonics generated by the RFPA when the antenna switch is in TX mode and provides extra 
selectivity when the antenna switch is in RX mode.
Power Detector
The power detector consists of two asymmetric, coupled transmission lines and detection circuitry 
that detects forward and reverse power. C3730-1, D3730, L3730, R3730-3, and R3735-6 form the 
forward-power detector (VFORWARD), which is used for power leveling. C3732-3, D3731, L3731, 
R3737-9, and R3733-4 form the reverse-power detector (VREVERSE). L3737 provides an 
electrostatic discharge path to protect the RFPA final stage device.

	


 

 
		
		




	





		
	

 
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							May 25, 20056881096C74-B
3-30Theory of Operation: Transmitter
3.6.1.4  Power Control (for 50W and 100W Transmitter)
The power control section is comprised of a control loop to level forward power and protection 
mechanisms to reduce power to a safe level for the given environmental conditions 
(see Figure 3-24).
Figure 3-24.  Power Control Components (VHF)
Power Control Loop
VFORWARD from the ON is buffered via the non-inverting, variable-gain stage U0956-2 whose gain 
is set by EPOT U0952. The proper gain is determined during power-detection calibration tuning. 
Buffered VFORWARD (U0956-2, Pin 7) is added to PWR_SET via R0971, R0972, and R0947 and 
then compared to a reference determined by R0974 and R0975. PWR_SET is supplied by the 
digital-to-analog converter (DAC) U0959, Pin 2. Comparator stage U0956-3 increases or decreases 
RFPA_CNTRL so that the voltage at U0956-3, Pin 9 in the same at the reference voltage at U0956-
3, Pin 10. When the PWR_SET voltage is decreased, U0956-3 increases RFPA_CNTRL to increase 
VFORWARD which is proportional to forward power thus increasing the power level. When the 
PWR_SET voltage is increased, U0956-3 decreases RFPA_CNTRL to decrease VFORWARD, thus 
decreasing the power level. The microprocessor initiates the loop through U0958-1 and Q0954. 
Loop timing is set via software together with R0977, and C0973.
EEPOT
U0952
Q0954RFPA_CNTRL
(TO RFPA) U0957-4
U0957-4 U0956-3
Q0955 TEMP_2
(U0959, PIN 10)VTEMP
(FROM RFPA)PA_EN
CURR_LIM_SET
(U0959, PIN1)
VCURRENT
(FROM RFPA) 9.3V
9.3V
9.3V9.3V 9.3V9.3V
9.3V
VFORWARD
(FROM ON)PWR_SET
(U0959, PIN 2)D0950
D0951
1.5V
D0952
U0957-1 U0956-2
U0957-2 TEMP_1
(U0959, PIN 9)
+- +-+-
+- +- +-
+
-
MAEPF-27889-O 
						

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-31
Protection Mechanisms
Final-stage temperature is sensed in the RFPA resulting in VTEMP, which is proportional to 
temperature. VTEMP is compared against a reference voltage TEMP_1 (U0959, pin 9) via U0957-1. 
When VTEMP exceeds TEMP_1, the U0957-1, pin 1, voltage increases and forward biases one of 
the D0951 diodes, which cuts back power. Power continues to cut back with rising temperature until 
the voltage level at the junction of R0978 and R0983 is high enough to forward bias D0952, thus 
clamping the cut back so that the radio meets its duty cycle specification while providing protection 
against high-temperature conditions. The clamping level is set via TEMP_2 (U0959, pin 10) and 
U0957-2. U0957-3 is used to sense if a high A+ battery voltage condition exists and, if it does, the 
Q0955 gate is biased on, which increases the clamp voltage allowing for additional power cutback 
for a high A+, high temperature condition.
Final-stage current is also monitored via VCURRENT, which is proportional to current. VCURRENT 
is compared against a reference CURR_LIM_SET (U0959, pin 1) which is tuned after power 
characterization. If VCURRENT exceeds CURR_LIM_SET, then U0957-4, pin 14, voltage rises and 
forward biases one of the D0951 diodes, which limits power.
Finally, control voltage is limited by U0956-4 and D0950. RFPA_CNTRL can rise to the control 
voltage limit set by R0942-4.
3.6.2 UHF Range 1 (380-470 MHz) Band
3.6.2.1  40-Watt Transmitter
The following text discusses the 40-W transmitter.
3.6.2.1.1  RF Power Amplifier (RFPA)
The RFPA consists of three gain stages, which are shown in Figure 3-25.
Figure 3-25.  40-Watt RF Power Amplifier (RFPA) Gain Stages (UHF Range 1)
FIRST
STAGE
0.5mW
U5501
C65250mW
Q5502
15183.5W
Q5503
157051W
To Antenna
Switch
RFPA_CNTRLK9.1V
TRANSMIT
BUFFER
TX_INJ
From
FGU2mW
Q5501
C65
K9.1V
VGBIAS3A+
DRV_9.3V
VGBIAS1 VGBIAS2
FINAL
STAGE
RFPA_OUT DRIVER
STAGE 
						

							May 25, 20056881096C74-B
3-32Theory of Operation: Transmitter
First Stage
The RFPA first stage provides gain that is determined by the control voltage, RFPA_CNTRL. This 
control voltage is generated in the power control section and is a function of the final-stage output 
power, temperature, and current, as well as the control and A+ voltage levels. See “3.6.2.4. Power 
Control (for 40W and 100W Transmitter)” on page 3-35 for a detailed explanation of the power 
control section.
The 0.5 mW TX_INJ signal is routed to the U5501 first stage device (Pin 16, RFIN) via C5508 to an 
integrated, wide-band input match. U5501 is a two-stage LDMOS device with a bandpass interstage 
match consisting of L5503, C5507, and C5509 routed between VD1 (pin 14) and G2 (pin 11). L5502 
and L5505 provide the K9.1V drain bias voltage for the first and second stages to VD1 (pin 14) and 
RFOUT1/2 (pins 6 and 7), respectively. The RFPA_CNTRL gate bias is provided to both stages 
internally via VCNTRL (pin 1). Both U5501 stages are operated Class A and the second-stage output 
power is approximately 250 mW.
Driver Stage
C5566, C5516, C5518 and a transmission line form a low-pass, interstage match that transfers 
power to the Q5502 LDMOS transistor. R5511-R5515 provide device stability, and R5527, C5556, 
C5525 and R5516 supply the VGBIAS3 gate bias. L5508, C5527, R5517, E5501 and C5526 form 
the 9.3 V drain bias circuit. The 9.3 V drain voltage is supplied from regulator U5570 via R5574. The 
9.3 V supply to the driver is only present during transmit and is disabled during receive via the K9.1V 
signal and Q5570. Q5502 is operated Class AB and its output power is approximately 3.5 W. 
Final Stage
C5559, C5560, C5535, C5538, and transmission lines form a low pass, splitter match that transfers 
power to the LDMOS final-stage transistor Q5503. Q5503 contains two transistors in a single 
package, each with its own gate and drain lead. R5530, R5533, R5534 and R5536 provide stability 
for Q5503. R5525, C5557, C5539 and R5520 supply the VGBIAS1 gate bias to Q5503-7. R5526, 
C5558, C5540 and R5521 supply the VGBIAS2 gate bias to Q5503-6. L5510, C5549, R5523, E5502 
and C5550 form the A+ drain bias circuit to Q5503-2 and Q5503-3. C5542-43, C5545-46, C5547-48, 
C5551-53 and transmission lines form a low -pass combiner match that transfers approximately 51 
W to the antenna switch. R5535 provides stability for Q5503. Q5503 operates Class AB. 
R5522 and U5503 comprise the final-stage, current-sense circuit that generates the VCURRENT 
voltage proportional to the final stage current. R5519 sets the circuit gain. U5502 generates the 
VTEMP voltage, which is proportional to the final-stage temperature.  
						

							6881096C74-BMay 25, 2005
Theory of Operation: Transmitter3-33
3.6.2.2  100-Watt Transmitter
The following text discusses the 100-W transmitter.
3.6.2.2.1  RF Power Amplifier (RFPA)
The RFPA consists of three gain stages, which are shown in Figure 3-26.
Figure 3-26.  100-Watt RF Power Amplifier (RFPA) Gain Stages (UHF Range 1)
First Stage
The RFPA first stage provides gain that is determined by the control voltage, RFPA_CNTRL. This 
control voltage is generated in the power control section and is a function of the final-stage output 
power, temperature, and current, as well as the control and A+ voltage levels. See “3.6.2.4. Power 
Control (for 40W and 100W Transmitter)” on page 3-35 for a detailed explanation of the power 
control section.
The 2.5 mW TX_INJ signal is routed to the U5500 first stage device (Pin 16, RFIN) via C5524 to an 
integrated, wide-band input match. U5500 is a two-stage LDMOS device with a bandpass interstage 
match consisting of L5511, L5510, C5511 routed between VD1 (pin 14) and G2 (pin 11). L5510 and 
R5510 provide the K9.1V drain bias voltage for the first and second stages to VD1 (pin 14) and 
RFOUT1/2 (pins 6 and 7), respectively. The RFPA_CNTRL gate bias is provided to both stages 
internally via VCNTRL (pin 1). Both U5501 stages are operated Class A and the second-stage output 
power is approximately 300 mW.
Driver Stage
C5525, L5514, C5516, C5518, C5519, C5523 and a transmission line form a low-pass, interstage 
match that transfers power to the Q5502 LDMOS transistor. R5520-R5525 provide device stability, 
and R5526, C5520 and C5529 supply the VGBIAS3 gate bias. L5520, C5521, R5527, L5521, R5528 
and C5522 form the A+ drain bias circuit. Q5520 is operated Class AB and its output power is 
approximately 8 W. 
50W
RFPA_out
100W
50W Q5540
Q5541 Q55208W
4W
A+
A+ A+
Vg_bias
Vg_bias Vg_bias 300mW
RFPA_cntrl Tx_inj
2.5mW
Key9.1V
U5500
30C65
4W 
						

							May 25, 20056881096C74-B
3-34Theory of Operation: Transmitter
Dual Final Stage
C5530, C5531, C5532, C5533, C5536, C5537-41 and transmission lines form a low pass, splitter 
match that transfers power to the LDMOS dual final-stage transistors Q5541 and Q5540. Q5540 and 
Q5541 contain two transistors in a single package, each with its own gate and drain lead. R5542-5, 
R5548-51 provide stability for Q5540. R5552-5, R5557-60 provide stability for Q5541. R5546, C5602 
and C5542 supply the VGBIAS1 gate bias to Q5540. R5581, C5550 and C5603 supply the VGBIAS2 
gate bias to Q5541. L5543, L5544, R5574, C5567 and C5568 form the A+ drain bias circuit to Q5540 
and Q5541. C5551-56, C5559-66, C5584, C5587, C5589 and transmission lines form a low -pass 
combiner match that transfers approximately 100 W to the antenna switch. R5562 provides stability 
for Q5540. R5573 provides stability for Q5541. Both Q5540 and Q5541 operate Class AB. 
R5575 and U5561 comprise the final-stage, current-sense circuit that generates the VCURRENT 
voltage proportional to the final stage current. R5578 sets the circuit gain. U5560 generates the 
VTEMP voltage, which is proportional to the final-stage temperature. 
3.6.2.3  Output Network (ON) - (for 40W and 100W Transmitter)
The ON consists of the antenna switch, harmonic filter, and power detector (see Figure 3-27).
Figure 3-27.  Output Network Components (UHF Range 1)
Antenna Switch
The antenna switch functions in two modes determined by the presence of K9.1V. The K9.1V switch 
bias is applied via L5701and C5702. When K9.1V is present, the switch is in TX mode. D5701, 
D5702 and D5703 are forward biased forming a low-loss path from the RFPA final stage to the 
harmonic filter and a 20 dB isolation path between the RFPA final stage and the RX front-end. 
Isolation is achieved via a quarter-wave transmission lines between D5701 - D5702 and between 
D5702 - D5703. C5709-10 resonates out the D5702-3 on inductance improving the isolation. When 
K9.1V is absent, the switch is in RX mode. D5701, D5702 and D5703 are reverse biased forming a 
low-loss path from the harmonic filter to the RX front-end and a 20 dB isolation path from the 
harmonic filter to the RFPA final stage. Isolation is achieved via the D5701 off resistance. L5702 
resonates out the D5701 off capacitance improving the isolation.
Harmonic Filter
The harmonic filter is a 7-element, equal-L Zolotarev quasi-lowpass filter consisting of C5712 and 
C5713, C5719 thru C5721 and L5706 thru L5708. L5712, C5711 and L5713, C5714 form two shunt 
zeros for extra attenuation at the second harmonic. C5708 acts as a DC block between the filter and 
the antenna switch. The filter provides approximately 60 dB of harmonic rejection. The harmonic 
filter together with the antenna switch provides approximately 0.7 dB insertion loss between the 
transmitter power amplifier and the antenna.
RFPA_OUTANTENNA
SWITCHH-FILTERPOWER
DETECTOR
RF
CONNECTOR
From
RFPA51W
K9.1VVREVERSE
VFORWARDJ570144W
RX_IN