Motorola Radius Cm200 Cm300 Pm400 Detailed 6881098c00 A Manual

							Technical Specifications1-3
*Availability subject to the laws and regulations of individual countries.
Transmitter
Specification UHF2
Power Output1-25W
Conducted/Radiated 
Emissions:-36 dBm < 1 GHz 
-30 dBm > 1 GHz
Audio Response: (from 6 dB/
oct. Pre-Emphasis, 300 to 
3000Hz)
TIA603 and CEPT
Tx Audio Distortion < 3%
Modulation Limiting:±2.5 kHz @ 12.5 kHz
±4.0 kHz @ 20 kHz
±5.0 kHz @ 25 kHz
FM Hum and Noise: -35 [email protected] kHz
-40 dB@25 kHz
Receiver
Specification UHF2
Sensitivity (12 dB SINAD):0.35 μV @ 12.5 kHz
0.3 μV @ 25 kHz
Intermodulation: 60 [email protected] kHz 
70 dB@25 kHz 
Adjacent Channel Selectivity:60 dB @ 12.5 kHz 
70 dB @ 25 kHz 
Spurious Response 70 dB 
Rated Audio Power4 W (typ.) Internal
7.5 W @ 5 % External
Audio Distortion < 5 %
Hum and Noise:-35 dB @ 12.5 kHz
-40 dB @ 25 kHz
Audio Response TIA603 and CEPT
Conducted Spurious Emission 
per FCC Part 15:-57 dBm 1 Ghz
Specifications subject to change without notice. All electrical specifications and methods 
refer to EIA/TIA 603 standards.  
						

							1-4 MODEL CHART AND TECHNICAL SPECIFICATIONS
Notes 
						

							Chapter 2
THEORY OF OPERATION
1.0 Introduction
This Chapter provides a detailed theory of operation for the UHF circuits in the radio. Details of the 
theory of operation and trouble shooting for the the associated Controller circuits are included in this 
Section of the manual.
2.0 UHF (438-470 MHz) Receiver
2.1 Receiver Front-End
The received signal is applied to the radio’s antenna input connector and routed through the 
harmonic filter and antenna switch. The insertion loss of the harmonic filter/antenna switch is less 
than 1 dB. The signal is routed to the first filter (4-pole), which has an insertion loss of 2 dB typically. 
The output of the filter is matched to the base of the LNA (Q303) that provides a 16 dB gain and a 
noise figure of better than 2 dB. Current source Q301 is used to maintain the collector current of 
Q303. Diode CR301 protects Q303 by clamping excessive input signals. Q303 output is applied to 
the second filter (3-pole) which has an insertion loss of 1.5 dB. In Distance mode, Q304 turns on and 
causes D305 to conduct, thus bypassing C322 and R337. In Local mode, the signal is routed 
through C322 and R337, thus inserting 7 dB attenuation. Since the attenuator is located after the RF 
amplifier, the receiver sensitivity is reduced only by 6 dB, while the overall third order input intercept 
is raised. 
The first mixer is a passive, double-balanced type, consisting of T300, T301 and U302. This mixer 
provides all of the necessary rejection of the half-IF spurious response. Low-side injection at 
+15 dBm is delivered to the first mixer. The mixer output is then connected to a duplex network 
which matches its output to the XTAL filter input (FL300) at the IF frequency of 44.85 MHz. The 
duplex network terminates into a 50 ohm resistor (R340) at all other frequencies.
Figure 2-1 UHF Receiver Block Diagram
Mixer
Xtal Filter
Controller Front Filter Antenna
First LO
2nd LO Xtal Osc
 IF AmpSecond Filter4- Pole
25 kHzFilter12.5 kHzFilter
Phase Shift 
Element IFIC LNA
25 kHzFilter
12.5 kHzFilter 
						

							2-2THEORY OF OPERATION
2.2 Receiver Back End
The IF signal from the crystal filter enters the IF amplifier which provides 20 dB of gain and feeds 
the IF IC at pin 1. The first IF signal at 44.85 MHz mixes with the second local oscillator (LO) at 
44.395 MHz to produce the second IF at 455 kHz. The second LO uses the external crystal Y301. 
The second IF signal is amplified and filtered by two external ceramic filters (FL303/FL302 for 
12.5 kHz channel spacing and FL304/FL301 for 25 kHz channel spacing). The IF IC demodulates 
the signal by means of a quadrature detector and feeds the detected audio (via pin 7) to the audio 
processing circuits. At IF IC pin 5, an RSSI signal is available with a dynamic range of 70 dB.
3.0 UHF Transmitter Power Amplifier (438-470 MHz)
The radio’s 25W PA is a three-stage amplifier used to amplify the output from the VCOBIC to the 
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U101) is 
adjustable and controlled by pin 7 of U103-2 via U103-3. It is followed by an LDMOS stage Q105 
and LDMOS final stage Q100.
Figure 2-2 UHF Transmitter Block Diagram
Devices U101, Q105 and Q100 are surface mounted. A metal clip ensures good thermal contact 
between both the driver and final stage, and the chassis.
3.1 First Power Controller Stage
The first stage (U101) is a 20 dB gain integrated circuit containing two LDMOS FET amplifier 
stages. It amplifies the RF signal from the VCO (TX_INJ). The output power of stage U101 is 
controlled by a DC voltage applied to pin 1 from the op-amp U103-3, pin 8. The control voltage 
simultaneously varies the bias of two FET stages within U101. This biasing point determines the 
overall gain of U101 and therefore its output drive level to Q105, which in turn controls the output 
Loop
Pin Diode 
Antenna 
Switch
RF JackAntenna
Harmonic 
Filter
CouplerPA - F i n a lStage
From VCO
ControlledSta ge
Bias 
Temperature
Sense SPI BUSASFIC_CMP
PA
PWR
SET
PA
Driver
Controller
U103-2Forward  
						

							UHF Transmitter Power Amplifier (438-470 MHz) 2-3
power of the PA.Op-amp U103-3 monitors the drain current of U101 via resistor R122 and adjusts 
the bias voltage of U101.
In receive mode, the DC voltage from RX_EN line turns on Q101, which in turn switches off the 
biasing voltage to U101.
3.2 Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of 12 dB. This device requires a 
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit 
mode by the drain current control op-amp U102-1, and fed to the gate of Q105 via the resistive 
network R175, R147.
Op-amp U102-1 monitors the drain current of Q105 via resistors R126-8 and adjusts the bias 
voltage of Q105.
In receive mode the DC voltage from RX_EN line turns on Q102, which in turn switches off the 
biasing voltage to Q105.
3.3 Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12 dB. This device also requires a 
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS 
is set in transmit mode by the ASFIC and fed to the gate of Q100 via the resistive network R134, 
R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be 
tuned using the Tuner. Care must be taken not to damage the device by exceeding the maximum 
allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage 
input, B+, via L117 and L115.
A matching network consisting of C1004-5, C1008, C1021: and two striplines, transforms the 
impedance to 50 ohms and feeds the directional coupler.
3.4 Directional Coupler
The directional Coupler is a microstrip printed circuit, which couples a small amount of the forward 
power of the RF power from Q100.The coupled signal is rectified to an output power which is 
proportional to the DC voltage rectified by diode D105; and the resulting DC voltage is routed to the 
power control section to ensure that the forward power out of the radio is held to a constant value.
3.5 Antenna Switch
The antenna switch utilizes the existing dc feed (B+) to the last stage device (Q100). The basic 
operation is to have both PIN diodes (D103, D104) turned on during key-up by forward biasing 
them. This is achieved by pulling down the voltage at the cathode end of D104 to around 12.4 V (0.7 
V drop across each diode). The current through the diodes needs to be set around 100 mA to fully 
open the transmit path through resistor R108. Q106 is a current source controlled by Q103 which is 
turned on in Tx mode by TX_EN. VR102 ensures that the voltage at resistor R107 never exceeds 
5.6 V. 
						

							2-4THEORY OF OPERATION
3.6 Harmonic Filter
Inductors L111 and L113 along with capacitors C1011, C1023, C1020 and C1016 form a low-pass 
filter to attenuate harmonic energy coming from the transmitter. Resistor R150 along with L126 
drains any electrostatic charges that might otherwise build up on the antenna. The harmonic filter 
also prevents high level RF signals above the receiver passband from reaching the receiver circuits 
to improve spurious response rejection.
3.7 Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler 
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by 
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error 
output current is then routed to an integrator, and converted into the control voltage. This voltage 
controls the bias of the pre-driver (U101 and driver (Q105) stages. The output power level is set by 
way of a DAC, PWR_SET, in the audio processing IC (U504) which acts at the forward power 
control loop reference.
The sampled reflected power is rectified by diode D107,The resulting DC voltage is amplified by an 
operational amplifier U100 and routed to the summing junction. This detector protects the final stage 
Q100 from reflected power by increasing the error current. The temperature sensor protects the 
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the 
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103 
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage 
below 5.6 V and eliminates the DC current from the 9.3 regulator U501. 
Two local loops for the Pre Driver (U101) and for the Driver (Q105) are used in order to stabilize the 
current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by 
applying ground to the Pre Driver U101 and for the Driver Q105 control.
4.0 UHF (438-470 MHz) Frequency Synthesis
The synthesizer consists of a reference oscillator (Y201), low voltage Fractional-N (LVFRAC-N) 
synthesizer (U200), and a voltage controlled oscillator (VCO) (U201).
4.1 Reference Oscillator
The reference oscillator is a crystal (Y201) controlled Colpitts oscillator and has a frequency of 
16.8 MHz. The oscillator transistor and start-up circuit are located in the LVFRAC-N (U200) while 
the oscillator feedback capacitors, crystal, and tuning varactors are external. An analog-to-digital (A/
D) converter internal to the LVFRAC-N (U200) and controlled by the microprocessor via SPI sets the 
voltage at the warp output of U200 pin 25. This sets the frequency of the oscillator. Consequently, 
the output of the crystal Y201 is applied to U200 pin 23.
The method of temperature compensation is to apply an inverse Bechmann voltage curve, which 
matches the crystal’s Bechmann curve to a varactor that constantly shifts the oscillator back on 
frequency. The crystal vendor characterizes the crystal over a specified temperature range and 
codes this information into a bar code that is printed on the crystal package. In production, this 
crystal code is read via a 2-dimensional bar code reader and the parameters are saved. 
						

							UHF (438-470 MHz) Frequency Synthesis2-5
This oscillator is temperature compensated to an accuracy of +/-2.5 PPM from -30 to 60 degrees C. 
The temperature compensation scheme is implemented by an algorithm that uses five crystal 
parameters (four characterize the inverse Bechmann voltage curve and one for frequency accuracy 
of the reference oscillator at 25 degrees C). This algorithm is implemented by the LVFRAC-N (U200) 
at the power up of the radio.
TCXO Y200, along with its corresponding circuitry R204, R205, R210, and C2053, are not placed as 
the temperature compensated crystal proved to be reliable.
4.2 Fractional-N Synthesizer
The LVFRAC-N U200 consists of a pre-scaler, programmable loop divider, control divider logic, 
phase detector, charge pump, A/D converter for low frequency digital modulation, balanced 
attenuator used to balance the high and low frequency analog modulation, 13 V positive voltage 
multiplier, serial interface for control, and a super filter for the regulated 5 volts.
Figure 2-3 UHF Synthesizer Block Diagram
A voltage of 5 V applied to the super filter input (U200, pin 30) supplies an output voltage of 4.5 Vdc 
(VSF) at U200, pin 28. This supplies 4.5 V to the VCO Buffer IC U201.
To generate a high voltage to supply the phase detector (charge pump) output stage at pin VCP 
(U200, pin 47) while using a low voltage 3.3 Vdc supply, a 13 V positive voltage multiplier is used 
(D200, D201, and capacitors C2024, 2025, 2026, 2055, 2027, 2001).
Output lock (U200, pin 4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. A 16.8 MHz reference frequency is provided at U200, pin 
19.
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)
+5 V (U503 PIN 1)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
        1540FILTERED 5VSTEERING LOCK (U403 PIN 56)
PRESCALER INFREF (U504 PIN 34)
39 BIAS2
41
 48 5, 20, 34, 36
+5 V (U503 PIN 1)
AUX1 VDD, DC5VMODOUT
U200 
LOW VOLTAGEFRACTIONAL-N
SYNTHESIZER
AUX21 (NU)
BWSELECTVCO Bias
TRB
To IF
SectionTX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
LOOP
FILTER 
						

							2-6THEORY OF OPERATION
4.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U201), the TX and 
RX tank circuits, the external RX buffer stages, and the modulation circuitry.
Figure 2-4 UHF VCO Block Diagram
The VCOBIC together with the LVFRAC-N (U200) generate the required frequencies in both 
transmit and receive modes. The TRB line (U201, pin 19) determines which VCO and buffer is 
enabled (high being TX output at pin 10, low being RX output at pin 8). A sample of the signal from 
the enabled output is routed from U201, pin 12 (PRESC_OUT), via a low pass filter to U200, pin 32 
(PREIN). 
A steering line voltage between 3.0 V and 10.0 V at varactor D204 tunes the TX VCO through the 
frequency range of 438-470 MHz, and at D203 tunes the RX VCO through the frequency range of 
393.15-425.15 MHz.
The external RX amplifier is used to increase the output from U201, pin 9 from 3-4 dBm to the 
required 15 dBm for proper mixer operation. In TX mode, the modulation signal from the LVFRAC-N 
(U200, pin 41) is applied to the VCO by way of the modulation circuit D205, R212, R211, C2073.
 
Presc
RX
TXBuffersQ200
Low Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U200 Pin28)
VCC Buffers
TX RF Injection U200 Pin 32 AUX3 (U200 Pin 2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U201
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6RX
TX
(U200 Pin 28)Rx-SW
Tx-SW
Vcc-Logic
(U200 Pin 28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION 
						

							UHF (438-470 MHz) Frequency Synthesis2-7
4.4 Synthesizer Operation
The synthesizer consists of a low voltage FRAC-N IC (LVFRAC-N), reference oscillator, charge 
pump circuits, loop filter circuit, and DC supply. The output signal (PRESC_OUT) of the VCOBIC 
(U201, pin 12) is fed to the PREIN, pin 32 of U200 via a low pass filter which attenuates harmonics 
and provides a correct input level to the LVFRAC-N in order to close the synthesizer loop.
The pre-scaler in the synthesizer (U200) is a dual modulus pre-scaler with selectable divider ratios. 
The divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs 
via the SPI. The output of the pre-scaler is applied to the loop divider. The output of the loop divider 
is connected to the phase detector, which compares the loop divider’s output signal with the 
reference signal. The reference signal is generated by dividing down the signal of the reference 
oscillator (Y201).
The output signal of the phase detector is a pulsed dc signal that is routed to the charge pump. The 
charge pump outputs a current from U200, pin 43 (IOUT). The loop filter (consisting of R224, R217, 
R234, C2074, C2075, C2077, C2078, C2079, C2080, C2028, and L205) transforms this current into 
a voltage that is applied the varactor diodes D203 and D204 for RX and TX respectively. The output 
frequency is determined by this control voltage. The current can be set to a value fixed in the 
LVFRAC-N or to a value determined by the currents flowing into BIAS 1 (U200, pin 40) or BIAS 2 
(U200, pin 39). The currents are set by the value of R200 or R206 respectively. The selection of the 
three different bias sources is done by software programming. 
To modulate the synthesizer loop, a two-spot modulation method is utilized via the MODIN (U200, 
pin 10) input of the LVFRAC-N. The audio signal is applied to both the A/D converter (low frequency 
path) and the balance attenuator (high frequency path). The A/D converter converts the low 
frequency analog modulating signal into a digital code which is applied to the loop divider, thereby 
causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s deviation 
sensitivity to high frequency modulating signals. The output of the balance attenuator is presented 
at the MODOUT port of the LVFRAC-N (U200,pin 41) and connected to the VCO modulation 
varactor D205. 
						

							2-8THEORY OF OPERATION
5.0 Controller Theory of Operation
This section provides a detailed theory of operation for the radio and its components. The main 
radio is a single-board design, consisting of the transmitter, receiver, and controller circuits. A 
control head is connected by an extension cable. The control head contains LED indicators, a 
microphone connector, buttons, and speaker. 
In addition to the power cable and antenna cable, an accessory cable can be attached to a 
connector on the rear of the radio. The accessory cable enables you to connect accessories to the 
radio, such as an external speaker, emergency switch, foot-operated PTT, and ignition sensing, etc.
Figure 2-5 Controller Block Diagram 
5.1 Radio Power Distribution
Voltage distribution is provided by five separate devices:
• U514 P-cH FET - Batt + (Ext_SWB+)
• U501 LM2941T - 9.3 V
• U503 LP2951CM - 5 V
• U508 MC 33269DTRK - 3.3 V
• U510 LP2986ILDX - 3.3 V Digital
External
Microphone
Internal
Microphone
External
Speaker
Internal
Speaker
SCI to
Control Head Audio
 PA Audio/Signaling
   Architecture To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer
Disc Audio
To RF SectionSPI
    Digital
ArchitectureµP Clock
   3.3 V
RegulatorRAM
EEPROM
FLASHHC11FL0 ASFIC_CMP
Accessory &  
Connector
Handset
.