Motorola Radius Cm200 Cm300 Pm400 Detailed 6881098c00 A Manual

							Controller Theory of Operation2-11
While the radio is switched on, the µP monitors the voltage at the emergency input on the accessory 
connector via U403-pin 62. Three different conditions are distinguished: no emergency kit is 
connected, emergency kit connected (unpressed), and emergency press.
If no emergency switch is connected or the connection to the emergency switch is broken, the 
resistive divider R5030 / R5049 will set the voltage to about 3.14 volts (indicates no emergency kit 
found via EMERGENCY_SENSE line). If an emergency switch is connected, a resistor to ground 
within the emergency switch will reduce the voltage on EMERGENCY _SENSE line, and indicate to 
the µP that the emergency switch is operational. An engaged emergency switch pulls line 
EMERGENCY _SENSE line to ground level. Diode VR503 limits the voltage to protect the µP input. 
While EMERGENCY _ACCES_CONN is low, the µP starts execution, reads that the emergency 
input is active through the voltage level of µP pin 64, and sets the DC POWER ON output of the 
ASFIC CMP pin 13 to a logic high. This high will keep Q505 in saturation for soft turn off. 
5.4 Microprocessor Clock Synthesiser
The clock source for the µP system is generated by the ASFIC CMP (U504). Upon power-up the 
synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF section to the 
ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a reference 
input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry, has a 
programmable synthesizer which can generate a synthesized signal ranging from 1200 Hz to 
32.769 MHz in 1200 Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864 MHz CMOS square 
wave UP CLK (on U504 pin 28) and this is routed to the µP (U403 pin 90). After the µP starts 
operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually 
7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various 
times depending on the software features that are executing. In addition, the clock frequency of the 
synthesizer is changed in small amounts if there is a possibility of harmonics of the clock source 
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C5025, C5024 and R5033 to set the switching time and jitter 
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch 
back to its default 3.6864 MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz 
reference clock it (and the voltage regulators) should be checked first when debugging the system. 
						

							2-12THEORY OF OPERATION
5.5 Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT 
DATA (MOSI) (U403-pin100), SPI RECEIVE DATA (MISO) (U403-pin 99), SPI CLK (U0403-pin1) 
and chip select lines going to the various IC’s, connected on the SPI PORT (BUS). This BUS is a 
synchronous bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA 
or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT 
DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA 
is used to send serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a 
device to a µP. 
There are two IC’s on the SPI BUS, ASFIC CMP (U504 pin 22)), and EEPROM (U400). In the RF 
sections there is one IC on the SPI BUS, the FRAC-N Synthesizer. The chip select line CSX from 
U403 pin 2 is shared by the ASFIC CMP and FRAC-N Synthesizer. Each of these IC’s check the 
SPI data and when the sent address information matches the IC’s address, the following data is 
processed. 
When the µP needs to program any of these Is it brings the chip select line CSX to a logic “0” and 
then sends the proper data and clock signals. The amount of data sent to the various IC’s are 
different; e.g., the ASFIC CMP can receive up to 19 bytes (152 bits). After the data has been sent 
the chip select line is returned to logic “1”.
5.6 SBEP Serial Interface
The SBEP serial interface allows the radio to communicate with the Customer Programming 
Software (CPS), or the Universal Tuner via the Radio Interface Box (RIB) or the cable with internal 
RIB. This interface connects to the SCI pin via control head connector (J2-pin 17) and to the 
accessory connector P1-6 and comprises BUS+. The line is bi-directional, meaning that either the 
radio or the RIB can drive the line. The µP sends serial data and it reads serial data via pin 97. 
Whenever the µP detects activity on the BUS+ line, it starts communication. 
5.7 General Purpose Input/Output
The controller provides six general purpose lines (PROG I/O) available on the accessory connector 
P1 to interface to external options. Lines PROG IN 3 and 6 are inputs, PROG OUT 4 is an output 
and PROG IN OUT 8, 12 and 14 are bi-directional. The software and the hardware configuration of 
the radio model define the function of each port.
• PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this 
port via pin 72 and Q412.
• PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is 
controlled by the µP (U403 pin 55)
• PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73 
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.
• DIG IN OUT 8,12,14 are bi-directional and use the same circuit configuration. Each port uses 
an output Q416, Q404, Q405 controlled by µP pins 52, 53, 54. The input ports are read 
through µP pins 74, 76, 77; using Q409, Q410, Q411 
						

							Controller Theory of Operation2-13
5.8 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In 
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation 
the µP uses only its internal memory. In normal operation of the radio the µP is operating in 
expanded mode as described below.
During normal operation, the µP (U403) is operating in expanded mode and has access to 3 
external memory devices; U400 (EEPROM), U402 (SRAM), U404 (Flash). Also, within the µP there 
are 3 Kilobytes of internal RAM, as well as logic to select external memory devices.
The external EEPROM (U400) space contains the information in the radio which is customer 
specific, referred to as the codeplug. This information consists of items such as: 1) what band the 
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information. 
The external SRAM (U402) as well as the µP’s own internal RAM space are used for temporary 
calculations required by the software during execution. All of the data stored in both of these 
locations is lost when the radio powers off. 
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data 
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U403-38) to chip select U404-pin 
30 (FLASH), CSGP2 (U403-pin 41) to chip select U404-pin 20 (SRAM) and PG7_R_W (U403-pin 4) 
to select whether to read or to write. The external EEPROM (U400-pin1). 
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic 
levels. Specifically, the logic high levels should be between 3.1 and 3.3 V, and the logic low levels 
should be between 0 and 0.2 V. No other intermediate levels should be observed, and the rise and 
fall times should be 
						

							2-14THEORY OF OPERATION
5.9 Static Random Access Memory (SRAM)
The SRAM (U402) contains temporary radio calculations or parameters that can change very 
frequently, and which are generated and stored by the software during its normal operation. The 
information is lost when the radio is turned off. 
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS 
signal U402 (which comes from U403-CSGP2) going low. U402 is commonly referred to as the 
external RAM as opposed to the internal RAM which is the 3 Kilobytes of RAM which is part of the 
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the 
calculated values which are accessed most often.
Capacitor C402 and C411 serves to filter out any AC noise which may ride on +3.3 V at U402
6.0 Control Board Audio and Signalling Circuits
6.1 Audio Signalling Filter IC and Compander (ASFIC CMP)
The ASFIC CMP (U504) used in the controller has the following four functions:
1.RX/TX audio shaping, i.e. filtering, amplification, attenuation
2.RX/TX signaling, PL/DPL/HST/MDC
3.Squelch detection
4.µP clock signal generation 
The ASFIC CMP is programmable through the SPI BUS (U504 pins-20/21/22), normally receiving 
19 bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or 
signaling signals through the appropriate filtering, gain and attenuator blocks. The ASFIC CMP also 
has 6 General Control Bits GCB0-5 which are CMOS level outputs and used for the following:
• GCBO - BW Select
• GCBI - switches the audio PA On/Off
• GCB2 - DC Power On switches the voltage regulator (and the radio) on and off
• GCB3 - Control on MUX U509 pin 9 to select between Low Cost Mic path to STD Mic Path
• GCB4 - Control on MUX U509 pin 11 to select between Flat RX path to filtered RX path on the 
accessory connector.
• GCB5 - Control on MUX U509 pin 10 to select between Flat TX path mute and Flat TX path 
						

							Transmit Audio Circuits2-15
7.0 Transmit Audio Circuits
Figure 2-7 Transmit Audio Paths
7.1 Microphone Input Path
The radio supports 2 distinct microphone paths known as internal (from control head J2-15) and 
external mic (from accessory connector P1-2) and an auxiliary path (FLAT TX AUDIO, from 
accessory connector P1-5). The microphones used for the radio require a DC biasing voltage 
provided by a resistive network.
The two microphone audio input paths enter the ASFIC CMP at U504-pin 48 (external mic) and 
U504-pin 46 (internal mic). The microphone is plugged into the radio control head and connected to 
the audio DC via J2-pin 15. The signal is then routed via C5045 to MUX U509 that select between 
two paths with different gain to support Low Cost Mic (Mic with out amplifier in it) and Standard Mic.
7.1.1 Low Cost Microphone
Hook Pin is shorted to Pin 1 (9.3 V) inside the Low Cost Mic, This routes 9.3 V to R429, and creates 
2.6 V on MIC_SENSE (u.P U403-67) by Voltage Divider R429/R430. U403 senses this voltage and 
sends command to ASFIC_CMP U504 to get GCB3 = ‘0’. The audio signal is routed from C5045 via 
U509-5 (Z0), R5072, U507, R5026, C5091, R5014 via C5046 to U504- 46 int. mic (C5046 100 nF 
creates a159 Hz pole with U504- 46 int mic impedance of 16Kohm).
MIC 
IN
MOD IN
TO
RF
SECTION
(SYNTHESIZER)
36 44
40
P1
ACCESSORY
CONNECTOR
J2
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
FLAT TX
AUDIO42
548
46 15
2
24kOhms
FILTERS AND
PREEMPHASIS
HS SUMMER
SPLATTER
FILTER
LS SUMMERLIMITER
ATTENUATORVCO 
ATN TX RTN TX SND
MIC
INT
AUX 
TX
ASFIC_CMP 
U504
U509
MIC
EXT
FLAT TX
AUDIO MUTEGCB3
MUX
35
U509
MUX
GCB5
38 
						

							2-16THEORY OF OPERATION
7.1.2 Standard Microphone
Hook Pin is shorted to the hook mic inside the standard Mic, If the mic is out off hook, 3.3 V is routed 
to R429 via R458, D401, and it create 0.7 V on MIC_SENSE (u.P U403-67) by Voltage Divider 
R429/R430. U403 senses this voltage and sends command to ASFIC_CMP U504 to get GCB3 =‘1’. 
The audio signal is routed from C5045 via U509-3 (Z1), R5072, U507, R5026, C5091, R5014 via 
C5046 to U504- 46 int mic (C5046 100nF create a159 Hz pole with U504- 46 int mic impedance of 
16Kohm). 9.3 Vdc is routed via R5077, R5075 to J2-15, It create 4.65 V with Mic Impedance. C5010 
supplies AC Ground to create AC impedance of 510 Ohms via R5075. and Filter 9.3 Vdc mic bias 
supply.
Note: The audio signal at U504-pin 46 should be approximately 12 mV for 1.5 kHz or 3 kHz of 
deviation with 12.5 kHz or 25 kHz channel spacing.
The external microphone signal enters the radio on accessory connector P1 pin 2 and is routed via 
line EXT MIC to R5054. R5078 and R5076 provide the 9.3 Vdc bias. Resistive divider R5054/ 
R5070 divide the input signal by 5.5 and provide input protection for the CMOS amplifier input. 
R5076 and C5009 provide a 510 ohm AC path to ground that sets the input impedance for the 
microphone and determines the gain based on the emitter resistor in the microphone’s amplifier 
circuit.
C5047 serves as a DC blocking capacitor. The audio signal at U504-pin 48 should be approximately 
14 mV for 1.5 kHz or 3 kHz of deviation with 12.5 kHz or 25 kHz channel spacing.
The FLAT TX AUDIO signal from accessory connector P1-pin 5 is fed to the ASFIC CMP (U504 pin 
42 through U509 pin 2 to U509 pin 15 via U506 OP-AMP circuit and C5057.
The ASFIC has an internal AGC that can control the gain in the mic audio path. The AGC can be 
disabled / enabled by the µP. Another feature that can be enabled or disabled in the ASFIC is the 
VOX. This circuit, along with Capacitor C5023 at U504-pin 7, provides a DC voltage that can allow 
the µP to detect microphone audio. The ASFIC can also be programmed to route the microphone 
audio to the speaker for public address operation.
7.2 PTT Sensing and TX Audio Processing
Internal microphone PTT is sensed by µP U403 pin 71. Radio transmits when this pin is “0” and 
selects inside the ASFIC_ CMP U504 internal Mic path. When the internal Mic PTT is “0” then 
external Mic PTT is grounded via D402. External Mic PTT is sensed by U403 pin 72 via Q412 
circuits. The radio transmits when this pin is “0” and selects inside the ASFIC _CMP U504 External 
Mic path.
Inside the ASFIC CMP, the mic audio is filtered to eliminate frequency components outside the 300-
3000 Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to 
prevent the transmitter from over deviating. The limited mic audio is then routed through a summer, 
which is used to add in signaling data, and then to a splatter filter to eliminate high frequency 
spectral components that could be generated by the limiter. The audio is then routed to an 
attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The 
TX audio emerges from the ASFIC CMP at U504-pin 40 MOD IN, at which point it is routed to the 
RF section. 
						

							Transmit Signalling Circuits2-17
8.0 Transmit Signalling Circuits
Figure 2-8 Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:
• Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or 
signaling,
• DTMF data for telephone communication in trunked and conventional systems, and
• Audible signaling including MDC and high-speed trunking.
Note: All three types are supported by the hardware while the radio software determines which 
signaling type is available.
8.1 Sub-Audio Data (PL/DPL)
Sub-audible data implies signaling whose bandwidth is below 300 Hz. PL and DPL waveforms are 
used for conventional operation and connect tones for trunked voice channel operation. The 
trunking connect tone is simply a PL tone at a higher deviation level than PL in a conventional 
system. Although it is referred to as “sub-audible data”, the actual frequency spectrum of these 
waveforms may be as high as 250 Hz, which is audible to the human ear. However, the radio 
receiver filters out any audio below 300 Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U504 (ASFIC CMP) at any one time. The 
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper low-
speed data deviation and select the PL or DPL filters. The µP then generates a square wave which 
strobes the ASFIC PL / DPL encode input LSIO U504-pin 18 at twelve times the desired data rate. 
For example, for a PL frequency of 103 Hz, the frequency of the square wave would be 1236 Hz.
This drives a tone generator inside U504 which generates a staircase approximation to a PL sine 
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice 
or data. The resulting summed waveform then appears on U504-pin 40 (MOD IN), where it is sent to 
the RF board as previously described for transmit audio. A trunking connect tone would be 
generated in the same manner as a PL tone.
19
18
40
MOD INTO RF
SECTION
(SYNTHESIZER)
8044
HIGH SPEED
CLOCK IN
(HSIO)
LOW SPEED 
CLOCK IN
(LSIO)
ASFIC_CMP U504
MICRO
CONTROLLER
U403
HS
SUMMER
5-3-2 STATE 
ENCODER
DTMF 
ENCODERSPLATTER
FILTER
PL
ENCODERLS
SUMMER
ATTENUATOR
8582
SPI
BUS 
						

							2-18THEORY OF OPERATION
8.2 High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signaling Words 
(ISWs) used in a trunking system for high speed communication between the central controller and 
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U504) to the proper filter and 
gain settings. It then begins strobing U504-pin 19 (HSIO) with a pulse when the data is supposed to 
change states. U504’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the post-
limiter summer block and then the splatter filter. From that point it is routed through the modulation 
attenuator and then out of the ASFIC CMP to the RF board. MDC is generated in much the same 
way as trunking ISW. However, in some cases these signals may also pass through a data pre-
emphasis block in the ASFIC CMP. Also these signaling schemes are based on sending a 
combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during high speed data 
signaling.
8.3 Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type 
of tones which are heard when using a “Touch Tone” telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941 Hz) and three in the 
high group (1209, 1336, 1477 Hz). The high-group tone is generated by the µP (U403-46) strobing 
U504-19 at six times the tone frequency for tones less than 1440 Hz or twice the frequency for 
tones greater than 1440 Hz. The low group tone is generated by the ASFIC CMP, controlled by the 
µP via SPI bus. Inside U504 the low-group and high-group tones are summed (with the amplitude of 
the high group tone being approximately 2 dB greater than that of the low group tone) and then pre-
emphasized before being routed to the summer and splatter filter. The DTMF waveform then follows 
the same path as was described for high-speed data. 
						

							Receive Audio Circuits2-19
9.0 Receive Audio Circuits
Figure 2-9 Receive Audio Paths
9.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal 
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U504-pin 2). All of 
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of 
view, DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs 
based on the result. They are CH ACT (U504-16) and SQ DET (U504-17).
The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then 
sent to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to 
produce SQ DET (U504-17) from CH ACT. The state of CH ACT and SQ DET is high (logic “1”) 
when carrier is detected, otherwise low (logic “0”).
CH ACT is routed to the µP pin 84 while SQ DET is routed to the µP pin 83.
SQ DET is used to determine all audio mute / unmute decisions except for Conventional Scan. In 
this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.
FLT RX AUDIO
P111
16
1EXTERNAL
SPEAKER
INTERNAL
SPEAKER ACCESSORY
CONNECTOR
CONTROL HEAD
CONNECTOR
HANDSET
AUDIO 1820 19
J2 INT
SPKR-
SPKR +
SPKR -1
9
2
U509
41 10
INT
SPKR+
4
6
DISC
ASFIC_CMP
U504
AUDIO 
PA
U502
VOLUME
ATTEN.
FILTER AND
DEEMPHASIS
17
MICRO 
CONTROLLER
U40380 FROM
RF
SECTION
(IF IC)
LIMITER, RECTIFIER
FILTER, COMPARATOR
SQ DETSQUELCH
CIRCUIT
16
PL  FILTER 
LIMITER
CH ACT
AUX RX43
18
LS IO
U IOAUDIO
8384
39URX OUT
DISC
AUDIO37
85
GCB4
MUTE
GCB1 14
U505 
						

							2-20THEORY OF OPERATION
9.2 Audio Processing and Digital Volume Control
The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is.DC 
coupled to ASFIC CMP via the DISC input U504-pin 2. The signal is then applied to both the audio 
and the PL/DPL paths
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth 
being received, an LPF filter to remove any frequency components above 3000 Hz, and a HPF to 
strip off any sub-audible data below 300 Hz. Next, the recovered audio passes through a de-
emphasis filter (if it is enabled to compensate for Pre-emphasis which is used to reduce the effects 
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level 
is set depending on the value of the volume control. Finally the filtered audio signal passes through 
an output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at AUDIO output 
(U504 pin 41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum / 
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signaling is summed with voice information on transmit, it must be separated 
from the voice information before processing. Any sub-audible signaling enters the ASFIC CMP 
from the IF IC at DISC U504-2. Once inside, it goes through the PL/DPL path. The signal first 
passes through one of the two low-pass filters, either the PL low-pass filter or the DPL/LST low-pass 
filter. Either signal is then filtered and goes through a limiter and exits the ASFIC CMP at LSIO 
(U504-pin 18). At this point, the signal will appear as a square wave version of the sub-audible 
signal which the radio received. The µP U403 pin 80 will decode the signal directly to determine if it 
is the tone / code which is currently active on that mode.
9.3 Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U504-pin 41 is routed through DC blocking 
capacitor C5049 to the audio PA (U502 pin 1 and 9). 
The audio power amplifier has one inverted and one non-inverted output that produces the 
differential audio output SPK+/SPK- (U502 pins 4 and 6)
The audio PA is enabled via the ASFIC CMP (U504-GCB1). When the base of Q501 is low, the 
transistor is off and U502-pin 8 is high, using pull up resistor R5041, and the audio PA is ON. The 
voltage at U502-pin 8 must be above 8.5 Vdc to properly enable the device. 
If the voltage is between 3.3 and 6.4 V, the device will be active but has its input (U502-pins 1/9) off. 
This is a mute condition which is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with B+ 
(U502- pin 7). B+ of 11 V yields a DC offset of 5 V, and B+ of 17 V yields a DC offset of 8.5 V. If 
either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ and 
SPK- are routed to the accessory connector (P1-pin 1 and 16) and to the control head (connector 
J2-pins 19 and 20).