Motorola Gm1200e Detailled 68p64115b15 Manual

							Transmitter Power Amplifier (PA) 5-25W
Introduction/Theory of Operation3.1-21
9.4 Antenna Switch
The antenna switch is switched synchronously with the K9V1 voltage and feeds either the antenna 
signal coming through the harmonic filter to the receiver or the transmitter signal coming from the PA 
to the antenna via the harmonic filter.
In transmit mode, this K9V1 voltage is high and biases Q5520 and along with the RF signal from 
Q5510 allows a collector current to be drawn. The collector current of Q5520 drawn from A+ flows 
via L5542, L5541, directional coupler, D5551, L5551, D5631, L5631, R5616, R5617 and L5611 and 
switches the PIN diodes D5551 and D5631 to the low impedance state. D5551 leads the RF signal 
from the directional coupler to the harmonic filter. The low impedance of D5631 is transformed to a 
high impedance at the input of the harmonic filter by the resonant circuit formed by L5551, C5633 
and the input capacitance of the harmonic filter.
In receive mode the low K9V1 and no RF signal present from Q5510 turn off the collector current of 
Q5520. With no current drawn by Q5520 and resistor R5615 pulling the voltage at PIN diode D5631 
to A+ both PIN diodes are switched to the high impedance state. The antenna signal, coming 
through the harmonic filter, is channelled to the receiver via L5551, C5634 and line PA RX. 
A high impedance resonant circuit formed by D5551 in off state and L5554, C5559 prevents an 
influence of the receive signal by the PA stages. The high impedance of D5631 in off state doesn´t 
influence the receiver signal. 
9.5 Harmonic Filter 
The transmitter signal from the antenna switch is channelled through the harmonic filter to the 
antenna connector J5501.The harmonic filter is formed by inductors L5552, L5553, and capacitors 
C5557, C5552 through C5555. This network forms a low-pass filter to attenuate harmonic energy of 
the transmitter to specifications level. R5550 is used for electro - static protection.
9.6 Power Control 
The power control loop regulates transmitter power with an automatic level control (ALC) loop and 
provides protection features against excessive control voltage and high operating temperatures.
MOS FET device bias, power and control voltage limit are adjusted under microprocessor control 
using a Digital to Analogue (D/A) converter (U0731). The microprocessor writes the data into the D/
A converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC 
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise 
time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control 
voltage.
The microprocessor controls K9V1 ENABLE (U0101-3) to switch on the first and the second PA 
stage via transistors Q0741, Q0742 and signal K9V1. The antenna switch is turned on by the 
collector current of the second PA stage. PA DISABLE, also microprocessor controlled (U0101-34), 
sets BIAS VLTG (U0731-4) and VLTG LIMIT SET (U0731-13) via Q0731, D0731 in receive mode to 
low to switch off the bias of the MOS FET device Q5530 and to switch off the power control voltage 
(PWR CNTL).
Through an Analogue to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA 
control voltage (PWR CNTL) during the tuning process. 
						

							Transmitter Power Amplifier (PA) 5-25W
3.1-22Introduction/Theory of Operation
The ALC loop regulates power by adjusting the PA control line PWR CNTL to keep the forward 
power voltage PWR DETECT at a constant level.
Opamp U0701-2 and resistors R0701 to R0703 and R0731 subtract the negative PWR DETECT 
voltage from the PA PWR SET D/A output U0731 pin 2. The result is connected to opamp inverting 
input U0701-4 pin 9 which is compared with a 4.6 volt reference VAG present at noninverting input 
U0701-4 pin 10 and controls the output power of the PA via pin 8 and control line PWR CNTL. The 
4.6 volt reference VAG is set by a resistive divider circuit (R0251, R0252) which is connected to 
ground and 9.3 volts and buffered by opamp U0251-1.
During normal transmitter operation the voltages at the opamp inputs U0701-4 pins 9 and 10 should 
be equal to 4.6 volts and the PA control voltage output at pin 8 should be between 4 and 7 volts. If 
power falls below the desired setting, PWR DETECT becomes less negative, causing the output at 
U0701-2 pin 7 to decrease and the opamp output U0701-4 pin 8 to increase.
A comparator formed by U0701-4 increases the PA control voltage PA CNTL until PWR DETECT is 
at the desired level. The power set D/A output voltage PWR SET (U0731-2) at U0701-2 pin 5 adjusts 
power in steps by adjusting the required value of PWR DETECT. As PA PWR SET (U0731-2) 
decreases, transmitter power must increase to make PWR DETECT more negative and keep the 
inverting input U0701-4 pin 9 at 4.6 volts.
Loop frequency response is controlled by opamp feedback components R0712 and C0711. Opamp 
U0701-3 compares the power control voltage PWR CNTL divided by resistors R0717 to R0719 with 
the voltage limit setting VLTG LIMIT SET from the D/A converter (U0731-13) and keeps the control 
voltage constant via Q0711 if the control voltage, reduced by the resistive divider (R0717 to R0719), 
approaches the voltage of VLTG LIMIT SET (U0731-13).
Rise and fall time of the output power during transmitter keying and dekeying is controlled by the 
comparator formed by opamp U0701-3.
During normal transmitter operation the voltage at U701-3 pin 13 is higher than the voltage at pin 12 
causing the output at pin 14 being low and switching off transistor Q0711. Diode D0732 reduces the 
bias voltage BIAS VLTG for low control voltage levels.
The temperature of the PA area is monitored by opamp U0701-1 using thermistor R5641 (located in 
the PA section). If the temperature increases, the resistance of the thermistor decreases, decreasing 
the voltage PA TEMP. The inverting amplifier formed by U0701-1 amplifies the PA TEMP voltage and 
if the voltage at opamp pin 1 approaches 4.6 V plus the voltage (ON) across D0721, U701-1 
simulates an increased power which in turn decreases the power control voltage until the voltage at 
U0701-4 pin 9 is 4.6V again. Resistor R0724, R0722, R0723 set the factor of the decrease in output 
power per temperature increase while R0721 through R0723 set the threshold were the temperature 
starts reducing the output power. During normal transmitter operation the output voltage of opamp 
U701-1 pin 1 is below 4.6V. Diode D5601 located in the PA section acts as protection against 
transients and wrong polarity of the supply voltage.  
						

							Frequency Synthesis
Introduction/Theory of Operation3.1-23
10.0 Frequency Synthesis
The complete synthesizer subsystem consists of the Reference Oscillator (Y5701 or U5702), the 
Fractional-N synthesizer (U5701), the Voltage Controlled Oscillator (Q5741), the RX and TX buffer 
stages (Q5751, Q5771, Q5781) and the feedback amplifier (Q5791).
10.1 Reference Oscillator
The Reference Oscillator (Y5702) contains a temperature compensated crystal oscillator with a 
frequency of 16.8 MHz. An Analogue to Digital (A/D) converter internal to U5701 (FRAC-N) and 
controlled by the microprocessor via serial interface (SRL) sets the voltage at the warp output of 
U5701 pin 16 to set the frequency of the oscillator. The output of the oscillator (pin 2 of Y5702) is 
applied to pin 14 (XTAL1) of U5701 via a RC series combination.
Some models use the Reference Oscillator U5702 instead of Y5702. The Reference Oscillator 
(U5702) contains a temperature compensated crystal oscillator with a frequency of 16.8 MHz. This 
oscillator is tuned by a temperature referenced 5 bit Analogue to Digital (A/D) converter. The output 
of the oscillator (pin 10 of U5702) is applied to pin 14 (XTAL1) of U5701 via a RC series 
combination. The serial interface (SRL) for control is connected to the mP via the data line SPI DATA 
(U5702-25), clock line SPI CLK (U5702-22), and chip enable line PEND CE (U5702-24). 
In applications were less frequency stability is required the oscillator inside U5701 is used along with 
an external crystal Y5701, the varactor diode D5702, C5708, C5710 and R5704. The crystal may 
not be replaced in case of failure. Instead of the crystal, the reference oscillator Y5702 must be 
soldered in along with C5706, C5707, R5703. Components Y5701, C5708, C5710, R5704, D5702 
must be removed and the value of C5709 must be changed. Afterwards the radio must be retuned.
10.2 Fractional-N Synthesizer (U5701)
The FRAC-N synthesizer IC (U5701) consists of a pre-scaler, a programmable loop divider, control 
divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital 
modulation, a balance attenuator to balance the high frequency analogue modulation and low 
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and 
finally a super filter for the regulated 9.3 volts.
A voltage of 9.3V applied to the super filter input (U5701 pin 19) supplies an output voltage of 8.6 
VDC at pin 18. It supplies the VCO (Q5741), VCO modulation bias circuit (via R5714) and the 
synthesizer charge pump resistor network (R5723, R5724, R5726). The synthesizer supply voltage 
is provided by the 5V regulator U5801.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U5701-32), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry 
(D5701-1-3, C5716, C5717). This voltage multiplier is basically a diode capacitor network driven by 
two (1.05MHz) 180 degrees out of phase signals (U5701-9 and -10).
Output LOCK (U5701-2) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U5701 divides the 16.8 MHz reference frequency down 
to 2.1 MHz and provides it at pin 11. This signal is used as clock signal by the controller.
The serial interface (SRL) is connected to the microprocessor via the data line SPI DATA (U5701-5), 
clock line SPI CLK (U5701-6), and chip enable line FRACN CE (U5701-7). 
						

							Frequency Synthesis
3.1-24Introduction/Theory of Operation
10.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) is formed by the colpitts oscillator FET Q5741. Q5741 
draws a drain current of 12 mA from the FRAC-N IC super filter output. The oscillator frequency is 
half of the desired frequency and mainly determined by L5743, C5742, C5743, C5745 - C5748 and 
varactor diodes D5741 / D5742. Diode D5743 controls the amplitude of the oscillator.
A balanced frequency doubler T5751, D5751 converts the oscillator fundamental to the desired UHF 
frequency. With a steering voltage from 2.5V to 10.5V at the varactor diodes the full RX and TX 
frequency range from 357.9 MHz to 470 MHz is covered.
After the doubler a 3-pole bandpass filter rejects unwanted harmonics at the first and third oscillator 
fundamental frequency and matches the output to the Common VCO Buffer Q5751. Q5751 draws a 
collector current of 13 mA from the stabilized 5V (U5801) and drives the Pre-scaler Buffer Q5791, 
the PA Buffer Q5781 (Pout = 13dBm) and Mixer Buffer Q5771 (Pout = 10dBm). Q5791 draws a 
collector current of 8 mA from the stabilized 5V and Q5771, Q5781 both draw 17mA form the 9V3 
source. The buffer stages Q5771, Q5781 and the feedback amplifier Q5791 provide the necessary 
gain and isolation for the synthesizer loop.
Q5731 is controlled by output AUX3 of U5701 (pin 1) and enables the RX or TX buffer. In RX mode 
AUX3 is nearly at ground level, in TX mode about 5V DC. In TX mode with R5732 pulled to ground 
level by Q5731 the modulation signal coming from the FRAC-N synthesizer IC (U5701 pin28) 
modulates the VCO via varactor diode D5731 while in RX mode the modulation circuit is disabled by 
pulling R5732 to a higher level through R5772.
10.4 Synthesizer Operation
The complete synthesizer subsystem works as follows. The output signal of the VCO (Q5741) is 
frequency doubled by doubler D5751 and, buffered by Common VCO Buffer Q5751. To close the 
synthesizer loop, the collector of Q5791 is connected to the PREIN port of synthesizer U5701 (pin 
20). The buffer output (Q5751) also provides signals for the Mixer Buffer Q5771 and the PA Buffer 
(Q5781).
The pre-scaler in the synthesizer (U5701) is basically a dual modulus pre-scaler with selectable 
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn 
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output 
of the loop divider is connected to the phase detector, which compares the loop divider’s output 
signal with the reference signal.The reference signal is generated by dividing down the signal of the 
reference oscillator (Y5702 or Y5701).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump. 
The charge pump outputs a current at pin 29 (I OUT of U5701). The loop filter (which consists of 
R5715-R5717, C5723-C5725, C5727, R5741, C5741) transforms this current into a voltage that is 
applied to the varactor diodes D5741, D5742 and alters the output frequency of the VCO (Q5741). 
The current can be set to a value fixed in the FRAC-N IC or to a value determined by the currents 
flowing into CPBIAS 1 (U5701-27) or CPBIAS 2 (U5701-26). The currents are set by the value of 
R5724 or R5726 respectively. The selection of the three different bias sources is done by software 
programming. 
						

							Receiver Front-End
Introduction/Theory of Operation3.1-25
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the 
magnitude of the loop current is increased by enabling the IADAPT line (U5701-31) for a certain 
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high 
transient of the FRACN CE line. When the synthesizer is within the lock range the current is 
determined only by the resistors connected to CPBIAS 1, CPBIAS 2, or the internal current source. 
A settled synthesizer loop is indicated by a high level of signal LOCK DET (U5701-2). 
LOCK DET adds up with signal SQ DET, weighted by resistors R0113, R0114, and is routed to one 
of the mP´s ADCs input U0101-43. From the voltage weighted by the resistors the mP determines 
whether SQ DET, LOCK DET or both are active.
In order to modulate the PLL the two spot modulation method is utilized. Via pin 8 (MODIN) on 
U5701 the audio signal is applied to both the A/D converter (low freq path) as well as the balance 
attenuator (high freq path). The A/D converter converts the low frequency analogue modulating 
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The 
balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency modulating 
signals. The output of the balance attenuator is present at the MODOUT port (U5701-28) and 
connected to the VCO modulation diode D5731 via L5731, C5732.
VHF (136-174MHz) SPECIFIC CIRCUIT DESCRIPTION
11.0 Receiver Front-End
The receiver is able to cover the VHF range from 136 to 174 MHz. It consists of four major blocks: 
front-end, mixer, first IF section and IF IC. Antenna signal pre-selection is performed by two varactor 
tuned bandpass filters. A double balanced schottky diode mixer converts the signal to the first IF at 
45.1 MHz.
Two crystal filters in the first IF section and two ceramic filters in the second IF section provide the 
required selectivity. The second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The 
processing of the demodulated audio signal is performed by an audio processing IC located in the 
controller section.
11.1 Front-End Band-Pass Filter and Pre-Amplifier
A two pole pre-selector filter tuned by the dual varactor diode D3301 pre-selects the incoming signal 
(PA RX) from the antenna switch to reduce spurious effects to following stages. The tuning voltage 
(FE CNTL VLTG) ranging from 2 volts to 8 volts is controlled by a Digital to Analogue (D/A) converter 
(U0731-11) in the controller section. A dual hot carrier diode (D3303) limits any inband signal to 
0dBm to prevent damage to the pre-amplifier.
The RF pre-amplifier is an SMD device (Q3301) with collector base feedback to stabilize gain, 
impedance, and intermodulation. The collector current of approximately 11-16 mA, drawn from the 
voltage 9V3 via L3302, is controlled by a current source composed of Q3302, R3302, R3300, and 
R3311 - R3313. In transmit mode the high K9V1 signal fed through diode D3300 switches off the 
current source and in turn the pre-amplifier. In receive mode K9V1 must be low to switch on the 
current source. A 3 dB pad (R3306 - R3308 and R3316 - R3318) stabilizes the output impedance 
and intermodulation performance. 
						

							Transmitter Power Amplifier (PA) 5-25W
3.1-26Introduction/Theory of Operation
A second two pole varactor tuned bandpass filter provides additional filtering to the amplified signal. 
The dual varactor diode D3304 is controlled by the same signal which controls the pre-selector filter.
If the radio is configured for a base station application, R3318 is not placed and TP3301 and TP3302 
are shorted.
11.2 Mixer and Intermediate Frequency (IF) Section
The signal coming from the front-end is converted to the first IF (45.1 MHz) using a double balanced 
schottky diode mixer (D3331). Its ports are matched for incoming VHF signal conversion to the 
45.1MHz IF using high side injection. The injection signal (VCO MIXER) coming from the mixer 
buffer (Q3770) is filtered by the lowpass consisting of (L3333, L3334, C3331 - C3333) and has a 
level of approximately 10 dBm.
The mixer IF output signal (RX IF) from transformer T3301 pin 2 is fed to the first two pole crystal 
filter Y5201. The filter output in turn is matched to the following IF amplifier.
The IF amplifier Q5201 is actively biased by a collector base feedback (R5201, R5202) to a current 
drain of approximately 5 mA drawn from the voltage 5V STAB. Its output impedance is matched to 
the second two pole crystal filter Y5202. A dual hot carrier diode (D5201) limits the filter output 
voltage swing to reduce overdrive effects at RF input levels above -27 dBm.
11.3 IF IC (U5201)
The first IF signal from the crystal filters feeds the IF IC (U5201) at pin 6. Within the IF IC the 
45.1MHz first IF signal mixes with the second local oscillator (LO) at 44.645MHz to the second IF at 
455 kHz. The second LO uses the external crystal Y5211. The second IF signal is amplified and 
filtered by two external ceramic filters (FL5201, FL5202). Back in the IF IC the signal is demodulated 
in a phase-lock detector and fed from IF IC pin 28 to the audio processing circuit ASFIC U0201 
located in the controller section (line DET AUDIO).
The squelch circuit of the IF IC is not used. Instead the squelch circuit inside the audio processing 
IC ASFIC (U0201) determines the squelch performance and sets the squelch threshold. The 
detector output signal from IF IC (U5201) pin 28 (DET AUDIO) is fed to the ASFIC pin H7.
At IF IC pin 11 an RSSI signal is available with a dynamic range of 70 dB. The RSSI signal is 
interpreted by the microprocessor (U0101 pin 44) and in addition after buffering by op-amp U0202-3 
available at accessory connector J0400-15.
12.0 Transmitter Power Amplifier (PA) 5-25W
The radio’s 5-25 W PA is a three stage amplifier used to amplify the output from the exciter to the 
radio transmit level. It consists of the following stages in the line-up. The first (Q3511) is a bipolar 
stage that is controlled via the PA control line (line PWR CNTL). It is followed by a MOS FET stage 
(Q3521) and a final bipolar stage (Q3531). Devices Q3511 and Q3521 are surface mounted. Bipolar 
Transistor Q3531 is directly attached to the heat sink. 
						

							Transmitter Power Amplifier (PA) 5-25W
Introduction/Theory of Operation3.1-27
12.1 Power Controlled Stage
The first stage (Q3511) amplifies the RF signal from the VCO (line EXCITER PA) and controls the 
output power of the PA. The output power of the transistor Q3511 is proportional to its collector 
current which is adjusted by a voltage controlled current source consisting of Q3641, (Q3643-T3 
only) and Q3642. The current of the whole stage is drawn from the RX-TX Switch through coil 
L3652.
Transistor Q3643 (not in all models), controlled by the microprocessor via signal K9V1, switches the 
current source on in transmit mode and off in receive mode.
The collector current of Q3511, drawn via L3511/L3641, causes a voltage drop across the resistors 
R3645 and R3646. Transistor Q3641 adjusts the voltage drop across R3644 controlled through the 
PA control line (PWR CNTL). The current source Q3642 adjusts the collector current of Q3511 by 
modifying its base voltage via R3647 until the voltage drop across R3645 and R3646 plus V
BE 
(0.6V) equals the voltage drop across R3644. If the voltage of PWR CNTL is raised, the base 
voltage of Q3641 will also rise causing more current to flow to the collector of Q3641 and a higher 
voltage drop across R3644. This in turn results in more current driven into the base of Q3511 by 
Q3642 so that the current of Q3511 is increased. The collector current settles when the voltage over 
the series configuration of R3645 and R3646 plus V
BE of Q3642 equals the voltage over R3644. By 
controlling the output power of Q3511 and in turn the input power of the following stages the ALC 
loop is able to regulate the output power of the transmitter. 
In receive mode the PA control line (PWR CNTL) is at ground level and switches off the collector 
current of Q3641 which in turn switches off the current source transistor Q3642 and the RF 
transistor Q3511.
12.2 PA Stages
The following stage uses an enhancement mode N-Channel MOS FET device (Q3521) and requires 
a positive gate bias and a quiescent current flow for proper operation. The voltage of the line BIAS 
VLTG is set in transmit mode by a Digital to Analogue (D/A) converter (U0731-4) and fed to the gate 
of Q3521 via the resistive network R3613, R3614, R3615. The bias voltage is tuned in the factory. If 
the transistor is replaced, the bias voltage must be tuned with the Dealer Programming Software 
(DPS). Care must be taken, not to damage the device by exceeding the maximum allowed bias 
voltage. The collector current is drawn from the supply voltage A+ via L3622.
The final stage uses the bipolar device Q3531 and operates off the A+ supply voltage. For class C 
operation the base is DC grounded by two series inductors (L3521, L3522). A matching network 
consisting of C3530-C3534, L3532, L3533 and two striplines transforms the impedance to 50 Ohms 
and feeds the directional coupler.
12.3 Directional Coupler
The directional coupler is a microstrip printed circuit which couples a small amount of the forward 
power off the RF power from Q3531. The coupled signal is rectified to an output power proportional 
negative DC voltage by the diode D3657 and sent to the power control circuit in the controller 
section via the line PWR DETECT for output power control. The power control circuit holds this 
voltage constant, thus ensuring the forward power out of the radio to be held to a constant value. 
						

							Transmitter Power Amplifier (PA) 5-25W
3.1-28Introduction/Theory of Operation
12.4 Antenna Switch
The antenna switch is switched synchronously with the K9V1 voltage along with the voltage PWR 
CNTL signal and feeds either the antenna signal coming through the harmonic filter to the receiver 
or the transmitter signal coming from the PA to the antenna via the harmonic filter.
In transmit mode, this PWR CNTL is above 1 V and biases Q3511 through Q3641 and Q3642 to 
allow a collector current to be drawn. The collector current of Q3511 drawn from A+ flows via L3631, 
L3531, L3532, L3533, directional coupler, D3551, L3651, D3651, L3652, R3645, R3646, L3641, 
L3511 and switches the PIN diodes D3551 and D3651 to the low impedance state. D3551 leads the 
RF signal from the directional coupler to the harmonic filter. The low impedance of D3651 is 
transformed to a high impedance at the input of the harmonic filter by the resonant circuit formed by 
L3651,C3652 and the input capacitance of the harmonic filter.
Transistor Q3643, controlled by the microprocessor via Signal K9V1, is used to switch the collector 
current of Q3641 on in transmit mode and off in receive mode. In receive mode the low K9V1 and 
the low PWR CNTL turn off the collector current of Q3511  through Q3641  and Q3642. With no 
current drawn by Q3511  and resistor R3651 pulling the voltage at PIN diode D3651 to A+ both PIN 
diodes are switched to the high impedance state. The antenna signal, coming through the harmonic 
filter, is channelled to the receiver via L3651, C3651 and line PA RX. The high impedance of D3551/
D3651 in off state does not influence the receiver signal.
12.5 Harmonic Filter
The transmitter signal from the antenna switch is channelled through the harmonic filter to the 
antenna connector J3501.The harmonic filter is formed by inductors L3551, L3552, and capacitors 
C3551 through to C3554 This network forms a low-pass filter to attenuate harmonic energy of the 
transmitter to specifications level. R3551 is used for electro-static protection.
12.6 Power Control
The power control loop regulates transmitter power with an automatic level control (ALC) loop and 
provides protection features against excessive control voltage and high operating temperatures.
MOS FET device bias, power and control voltage limit are adjusted under microprocessor control 
using a Digital to Analogue (D/A) converter (U0731). The microprocessor writes the data into the D/
A converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC 
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise 
time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control 
voltage.
The microprocessor controls K9V1 ENABLE (U0101-3) to switch on the first PA stage via transistors 
Q0741, Q0742 and signal K9V1. The antenna switch is turned on by the collector current of the first 
PA stage. PA DISABLE, also microprocessor controlled (U0101-34), sets BIAS VLTG (U0731-4) and 
VLTG LIMIT SET (U0731-13) via Q0731, D0731 in receive mode to low to switch off the bias of the 
MOS FET device Q3521 and to switch off the power control voltage (PWR CNTL).
Through an Analogue to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA 
control voltage (PWR CNTL) during the tuning process. 
						

							Transmitter Power Amplifier (PA) 5-25W
Introduction/Theory of Operation3.1-29
The ALC loop regulates power by adjusting the PA control line PWR CNTL to keep the forward 
power voltage PWR DETECT at a constant level.
Opamp U0701-2 and resistors R0701 to R0703 and R0731 subtract the negative PWR DETECT 
voltage from the PA PWR SET D/A output U0731 pin 2. The result is connected to opamp inverting 
input U0701-4 pin 9 which is compared with a 4.6 volt reference VAG present at noninverting input 
U0701-4 pin 10 and controls the output power of the PA via pin 8 and control line PWR CNTL. The 
4.6 volt reference VAG is set by a resistive divider circuit (R0251, R0252) which is connected to 
ground and 9.3 volts and buffered by opamp U0251-1.
During normal transmitter operation the voltages at the opamp inputs U0701-4 pins 9 and 10 should 
be equal to 4.6 volts and the PA control voltage output at pin 8 should be between 4 and 7 volts. If 
power falls below the desired setting, PWR DETECT becomes less negative, causing the output at 
U0701-2 pin 7 to decrease and the opamp output U0701-4 pin 8 to increase.
A comparator formed by U0701-4 increases the PA control voltage PA CNTL until PWR DETECT is 
at the desired level. The power set D/A output voltage PWR SET (U0731-2) at U0701-2 pin 5 adjusts 
power in steps by adjusting the required value of PWR DETECT. As PWR SET (U0731-2) 
decreases, transmitter power must increase to make PWR DETECT becomes more negative and 
keep the inverting input U0701-4 pin 9 at 4.6 volts.
Loop frequency response is controlled by opamp feedback components R0712 and C0711. Opamp 
U0701-3 compares the power control voltage PWR CNTL divided by resistors R0717 to R0719 with 
the voltage limit setting VLTG LIMIT SET from the D/A converter (U0731-13) and keeps the control 
voltage constant via Q0711 if the control voltage, reduced by the resistive divider (R0717 to R0719), 
approaches the voltage of VLTG LIMIT SET (U0731-13).
Rise and fall time of the output power during transmitter keying and dekeying is controlled by the 
comparator formed by opamp U0701-3.
During normal transmitter operation the voltage at U701-3 pin 13 is higher than the voltage at pin 12 
causing the output at pin 14 being low and switching off transistor Q0711. Diode D0732 reduces the 
bias voltage BIAS VLTG for low control voltage levels.
The temperature of the PA area is monitored by opamp U0701-1 using thermistor R3611 (located in 
the PA section). If the temperature increases, the resistance of the thermistor decreases, decreasing 
the voltage PA TEMP. The inverting amplifier formed by U0701-1 amplifies the PA TEMP voltage and 
if the voltage at opamp pin 1 approaches 4.6 V plus the voltage (ON) across D0721, U701-1 
simulates an increased power which in turn decreases the power control voltage until the voltage at 
U0701-4 pin 9 is 4.6V again. Resistor R0724, R0722, R0723 set the factor of the decrease in output 
power per temperature increase while R0721 through R0723 set the threshold were the temperature 
starts reducing the output power. During normal transmitter operation the output voltage of opamp 
U701-1 pin 1 is below 4.6V. Diode D3601 located in the PA section acts as protection against 
transients and wrong polarity of the supply voltage.  
						

							Frequency Synthesis
3.1-30Introduction/Theory of Operation
13.0 Frequency Synthesis 
The complete synthesizer subsystem consists of the Reference Oscillator (Y3701 or Y3702), the 
Fractional-N synthesizer (U3701), the Voltage Controlled Oscillator (Q3741, Q3751), the RX and TX 
buffer stages (Q3760, Q3770, Q3780) and the feedback amplifier (Q3790).
13.1 Reference Oscillator
The Reference Oscillator (Y3702) contains a temperature compensated crystal oscillator with a 
frequency of 16.8 MHz. An Analogue to Digital (A/D) converter internal to U3701 and controlled by 
the microprocessor via serial interface (SRL) sets the voltage at the warp output of U3701 pin 16 to 
set the frequency of the oscillator. The output of the oscillator (pin 2 of Y3702) is applied to pin 14 
(XTAL1) of U3701 via a RC series combination.
In applications were less frequency stability is required the oscillator inside U3701 is used along with 
an external crystal Y3701, the varactor diode D3702, C3708, C3710 and R3704. The crystal may 
not be replaced in case of failure. Instead of the crystal, the reference oscillator Y3702 must be 
soldered in along with C3706, C3707, R3703. Components Y3701, C3708, C3710, R3704, D3702 
must be removed and the value of C3709 must be changed. Afterwords the radio must be retuned.
13.2 Fractional-N Synthesizer (U3701)
The FRAC-N synthesizer IC (U3701) consists of a pre-scaler, a programmable loop divider, control 
divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital 
modulation, a balance attenuator to balance the high frequency analogue modulation and low 
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and 
finally a super filter for the regulated 9.3 volts.
A voltage of 9.3V applied to the super filter input (U3701 pin 19) supplies an output voltage of 8.6 
VDC at pin 18. It supplies the VCO (Q3741 / Q3751), VCO modulation bias circuit (R3714) and the 
synthesizer charge pump resistor network (R3723, R3724). The synthesizer supply voltage is 
provided by the 5V regulator U3801.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U3701-32), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry 
(D3701-1-3, C3716, C3717). This voltage multiplier is basically a diode capacitor network driven by 
two (1.05 MHz) 180 degrees out of phase signals (U3701-9 and -10).
Output LOCK (U3701-2) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U3701 divides the 16.8 MHz reference frequency down 
to 2.1 MHz and provides it at pin 11. This signal is used as clock signal by the controller.
The serial interface (SRL) is connected to the microprocessor via the data line SPI DATA (U3701-5), 
clock line SPI CLK (U3701-6), and chip enable line FRACN CE (U3701-7).
13.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) uses 2 colpitts oscillators, FET Q3741 for transmit and FET 
Q3751 for receive. The appropriate oscillator is switched on or off by FRAC-N IC output AUX3 
(U3701-1) using transistors Q3742 and Q3752. In RX mode AUX3 is nearly at ground level and 
Q3742 enables a current flow from the source of FET Q3751 while Q3752 is switched off.