Motorola Gm1200e Detailled 68p64115b15 Manual

							 
Introduction
Introduction/Theory of Operation3.1-1
 
1.0 Introduction 
This section provides a detailed theory of operation for the radio and its components. The main radio 
is a single board design, consisting of the transmitter, receiver, and controller circuits. 
The main board is designed to accept one additional option board. This may provide functions such 
as secure voice/data or DTMF decoder. The control head is mounted directly on the front of the 
radio or connected via an extension cable in remote mount operation. The control head contains 
LED indicators, a microphone connector, buttons/keypad and a display. These provide the user with 
interface control over the various features of the radio. 
In addition to the power cable and antenna cable, an accessory cable can be attached to a 
connector on the rear of the radio. The accessory cable provides the necessary connections for 
items such as external speaker, emergency switch, foot operated PTT, ignition sensing, etc. 
2.0 Open Controller 
2.1 General 
The radio controller consists of 4 main subsections:  
n n 
Digital Control 
n n 
Audio Processing 
n n 
Power Control 
n n 
Voltage Regulation
The digital control section of the radio board is based upon an open architecture controller 
configuration. It consists of a microprocessor, support memory, support logic, signal MUX ICs, the 
On/Off circuit, and general purpose Input/Output circuitry. 
The controller uses the Motorola 68HC11K1 microprocessor (U0101). In addition to the 
microprocessor, the controller has 3 external memory devices. The 3 memory devices consist of a 
32kbyte SRAM (U0103), a 512kbyte FLASH EEPROM (U0102), and a 16kbyte EEPROM (U0104). 
Note: 
From this point on the 68HC11K1 microprocessor will be referred to as  
m  
P or K1  
m  
P.  
References to the control head will be to the Display/Keypad radio model (K6). 
2.2 Voltage Regulators 
Voltage regulation for the controller is provided by 3 separate devices; U0631 (LP2951CM) +5V, 
U0601 (LM2941T) +9.3V, and UNSW 5V (a combination of R0621 and VR0621). An additional 
regulator is located in the RF section.
Voltage regulation providing 5V for the digital circuitry is done by U0631. Input and output capacitors 
(C0631/C0632 and C0633-C0635) are used to reduce high frequency noise and provide proper 
operation during battery transients. This regulator provides a reset output (pin 5) that goes to 0 volts 
if the regulator output goes out of regulation. This is used to reset the controller to prevent improper 
operation. Diode D0631 prevents discharge of C0632 by negative spikes on the 9V3 voltage.
3.1 
						

							 
Open Controller
3.1-2Introduction/Theory of Operation
 
Regulator U0601 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry 
and power control circuitry. Input and output capacitors (C0601-C0603 and C0604/C0605) are used 
to reduce high frequency noise. R0602/R0603 set the output voltage of the regulator. If the voltage 
at pin 1 is greater than 1.3 volts the regulator output decreases and if the voltage is less than 1.3 
volts the regulator output increases. This regulator output is electronically enabled by a 0 volt signal 
on pin 2. Q0601 and associated circuitry (R0601/R0604/R0605) are used to disable the regulator 
when the radio is turned off. 
UNSW 5V is only used in a few areas which draw low current and require 5 V while the radio is off.
UNSW 5V CL is used to buffer the internal RAM. C0622 allows the battery voltage to be 
disconnected for a couple of seconds without losing RAM parameters. Diode D0621 prevents radio 
circuitry from discharging this capacitor.
The voltage 9V3 SUPP is only used in the VHF radio (T1) to supply the drain current for the RF MOS 
FET in the PA. The voltage SW B+ is monitored by the  
m  
P through the voltage divider R0641/R0642 
and line BATTERY VOLTAGE. Diode VR0641 limits the divided voltage to 5.1V to protect the  
m  
P.
Diode D5601 (UHF) / D3601 (VHF) / D2601 (MB) located on the PA section acts as protection 
against transients and wrong polarity of the supply voltage. 
2.3 Electronic On/Off 
The radio has circuitry which allows radio software and/or external triggers to turn the radio on or off 
without direct user action. For example, automatic turn on when ignition is sensed and off when 
ignition is off. 
Q0611 is used to provide SW B+ to the various radio circuits. Q0611 contains a pnp and an npn 
transistor and acts as an electronic on/off switch. The switch is on when the collector of the npn 
transistor (Q0611-1) is low. When the radio is off the pnp transistor is cutoff and the voltage at pin 1 
is at A+. This effectively prevents current flow through the pnp transistor from emitter (pin 3) to 
collector (pin 2). 
When the radio is turned on the voltage at the Q0611 pin 4 is high (about 4.4V) and the npn 
transistor switches on (saturation) and pulls down the voltage at the base of the pnp transistor. With 
Transistor Q0611 now “enabled” current flows through the device from pin 3 to pin 2. This path has a 
very low impedance (less than 1 ohm) from emitter to collector. This effectively provides the same 
voltage level at SWB+ as at A+.
The electronic on/off circuitry can be enabled by the microprocessor (through ASFIC port GCB2, 
line B+ CONTROL), the emergency switch (line EMERGENCY CONTROL), the mechanical On/Off 
button on the control head (line ON OFF CONTROL), or the ignition sense circuitry (line IGNITION 
CONTROL). If any of the 4 paths cause a low at Q0611 pin 1, the electronic ON is engaged. 
2.4 Emergency 
The emergency switch (J0400-9), when engaged, grounds the base of Q0441 and pulls the line 
EMERGENCY CONTROL to low via D0441. EMER IGN SENSE is pulled high by R0441. When the 
emergency switch is released the base of Q0441 is pulled high by R0442. This causes the collector 
of transistor Q0441 to go low (0.2V), thereby setting the EMER IGN SENSE line to low.  
						

							 
Open Controller
Introduction/Theory of Operation3.1-3
 
While EMERGENCY CONTROL is low, SW B+ is on, the microprocessor starts execution, reads 
that the emergency input is active through the voltage level of EMER IGN SENSE, and sets the B+ 
CONTROL output of the ASFIC pin B4 to a logic high. This high will keep Q0611 switched on. This 
operation allows a momentary press of the emergency switch to power up the radio. When the 
microprocessor has finished processing the emergency press, it sets the B+ CONTROL line to a 
logic 0. This turns off Q0611 and the radio turns off. Notice that the microprocessor is alerted to the 
emergency condition via line EMER IGN SENSE. If the radio was already on when emergency was 
triggered then B+ CONTROL would already be high. 
2.5 Mechanical On/Off 
This refers to the typical on/off button, located on the control head, and which turns the radio on and 
off. If the radio is turned off and the on/off button is pressed, line ON OFF CONTROL goes high and 
switches the radio on as long as the button is pressed. The microprocessor is alerted through line 
ANALOG 3 which is pulled to low by Q0925 (Display/Keypad Control Head) while the on/off button is 
pressed. If the software detects a low state it asserts B+ CONTROL via ASFIC pin B4 high which 
keeps Q0611, and in turn the radio switched on. 
If the on/off button is pressed and held while the radio is on, the software detects the line ANALOG 
3 changing to low and switches the radio off by setting B+ CONTROL to low. 
2.6 Ignition 
Ignition sense is used to prevent the radio from draining the vehicle’s battery because the engine is 
not running. 
When the IGNITION input (J0400-10) goes above 6 volts Q0611 is turned on via line IGNITION 
CONTROL. Q0611 turns on SW B+ and the microprocessor starts execution. A high IGNITION input 
reduces the voltage of line EMER IGN SENSE by turning on Q0450. The software reads the line 
EMER IGN SENSE, determines from the level (Emergency has a different level) that the IGNITION 
input is active and sets the B+ CONTROL output of the ASFIC pin B4 to high to latch on SW B+. 
When the IGNITION input goes below 6 volts, Q0450 switches off and R0449, R0450 pull line 
EMER IGN SENSE high. The software is alerted by line EMER IGN SENSE to switch off the radio 
by setting B+ CONTROL to low. The next time the IGNITION input goes above 6 volts the above 
process will be repeated.  
2.7 Hook RSS 
The HOOK RSS input is used to inform the  
m 
P when the Microphone’s hang-up switch is engaged. 
Dependent on the radio model the  
m 
P may take actions like turning the audio PA on or off. 
The signal is routed from J0101-3 and J0400-14 through transistor Q0101 to the K1 
m  
P U0101-23. 
The voltage range of HOOK RSS in normal operating mode is 0-5V.
To start SBEP communication this voltage must be above 6V. This condition generates a  
m  
P 
interrupt via VR0102, Q0105, Q0104, Q0106 and enables the BUS+ line for communication via 
Q0122, Q0121. 
						

							 
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3.1-4Introduction/Theory of Operation
 
2.8 Microprocessor Clock Synthesizer 
The clock source for the microprocessor system is generated by the ASFIC (U0201). Upon power-
up the synthesizer U5701 (UHF) / U3701 (VHF) / U2701 (MB) generates a 2.1 MHz waveform that is 
routed from the RF section (via C0202) to the ASFIC (on U0201-E1) For the main board controller 
the ASFIC uses 2.1MHz as a reference input clock signal for its internal synthesizer. The ASFIC, in 
addition to audio circuitry, has a programmable synthesizer which can generate a synthesized signal 
ranging from 1200Hz to 32.769MHz in 1200 Hz steps. 
When power is first applied, the ASFIC will generate its default 3.6864 MHz CMOS square wave  
m  
P 
CLK (on U0201-D1) and this is routed to the microprocessor (U0101-73). After the microprocessor 
starts operation, it reprograms the ASFIC clock synthesizer to a higher  
m  
P CLK frequency (usually 
7.9488 MHz) and continues operation. 
The ASFIC may be reprogrammed to change the clock synthesizer frequencies at various times 
depending on the software features that are executing. In addition, the clock frequency of the 
synthesizer is changed in small amounts if there is a possibility of harmonics of this clock source 
interfering with the desired radio receive frequency. 
The ASFIC synthesizer loop uses C0228, C0229 and R0222 to set the switching time and jitter of 
the clock output. If the synthesizer cannot generate the required clock frequency it will switch back to 
its default 3.6864MHz output. 
Because the ASFIC synthesizer and the  
m 
P system will not operate without the 2.1MHz reference 
clock, it (and the voltage regulators) should be checked first when debugging the system. 
2.9 Serial Peripheral Interface (SPI) 
The  
m 
P communicates to many of the ICs through its SPI port. This port consists of SPI TRANSMIT 
DATA (MOSI) (U0101-1), SPI RECEIVE DATA (MISO) (U0101-80), SPI CLK (U0101-2) and chip 
select lines going to the various ICs, connected on the SPI PORT (BUS). This BUS is a synchronous 
bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA or SPI 
RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT DATA or SPI 
RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA is used to send 
serial from a  
m 
P to a device, and SPI RECEIVE DATA is used to send data from a device to a  
m  
P. The 
only device from which data can be received via SPI RECEIVE DATA is the EEPROM (U0104 or 
U0107) and a control head with graphical display (Display/Keypad Radio Model K6).
On the controller there are three ICs on the SPI BUS, ASFIC (U0201-F2), EEPROM (U0104-1 or 
U0107-1) and D/A (U0731-6). In the RF sections there is one IC on the SPI BUS which is the 
FRAC-N Synthesizer. The SPI TRANSMIT DATA and CLK lines going to the RF section are filtered 
by L0131/L0132 to minimize noise. The chip select lines for the IC´s are decoded by the address 
decoder U0105. 
The SPI BUS is also used for the control head. U0106-2,3 buffer the SPI TRANSMIT DATA and CLK 
lines to the control head. U0106-1 switch off the CLK signal for the LCD display if it is not selected 
via LCD CE and Q0141.
When the  
m 
P needs to program any of these IC’s it brings the chip select line for that IC to a logic 0 
and then sends the proper data and clock signals. The amount of data sent to the various IC’s are 
different, for example the FRAC-N can receive up to 21 bytes (168 bits) while the DAC can receive 
up to 3 bytes (24 bits). After the data has been sent the chip select line is returned to a logic 1. 
						

							 
Open Controller
Introduction/Theory of Operation3.1-5
 
When the control head with graphical display wants to communicate to the  
m  
P it brings request line 
ANALOG 2 (J0101-11) to a logic “0“. The  
m 
P reads this line via one of the analogue to digital 
converters (U0101-48) and then starts communication by activating the control head select line 
(LED CHT CE) via U0105-9 and J0101-12, sending the clock signal via U0106-3 and J0101-5 and 
sending data via U0106-2 and J0101-6 or receiving data via J0101-10 and gate U0171. During data 
transfer gate U0171 is switched on by line LED CHT CE via transistor Q0171 and gate U0172-1. 
Gate U0172-1 is enabled by the  
m 
P via ASFIC output GCB4 (U0201-A2).
The Option board interfaces are different in that the  
m 
P can also read data back from devices 
connected.The timing and operation of this interface is specific to the option connected, but 
generally follows the pattern:  
1. 
an option board device generates an interrupt via J0103-8, Q0124, Q0125 and  
m  
P pin 61 
(IRQ). The  
m 
P determines the interrupt source by reading a high at the collector of Q0124 via  
m 
P pin 7 and R0129. 
2. 
the main board asserts a chip select for that option board device via U0105-10, J0102-5, 
3. 
the main board  
m 
P generates the CLK (J0102-6), 
4. 
the main board  
m 
P writes serial data via J0102-4 and reads serial data via J0102-2 and, 
5. 
when data transfer is complete the main board terminates the chip select and CLK activity. 
2.10 SPEB Serial Interface 
The SBEP serial interface allows the radio to communicate with the Dealer Programming Software 
(DPS) via the Radio Interface Box (RIB). This interface connects to the Microphone connector 
(J0903/J0803) via Control Head connector (J0101-15) or to the accessory connector J0400-6 and 
comprises BUS+ (J0101-15). The line is bi-directional, meaning that either the radio or the DPS can 
drive the line. 
When the RIB (Radio Interface Box) is connected to the radio, a voltage on the HOOK RSS line 
above 6 volts switches on Q0105. The low state at collector of Q0105 switches Q0104 off and in 
turn, Q0106 on. A high to low transition at the collector of Q0106 generates an interrupt via  
m  
P pin 
61. The  
m 
P determines the interrupt source by reading a high at the collector of Q0104 via  
m  
P pin 6 
and R0125. The switched on Q0105 also switches off Q0122 enabling the  
m 
P to read BUS+ via pin 
78 and to write BUS+ via pin 79 and transistors Q0123, Q0121. While the radio is sending serial 
data at pin 79 via Q0123 and Q0121 it receives an “echo” of the same data at pin 78.
When the voltage on the HOOK RSS line is below 6 volts (RIB is not connected), the high collector 
of Q0105 turns on Q0122. The low collector of Q0122 prevents the  
m 
P from writing data to BUS+ via 
Q0123. In this mode line BUS+ is used for signal SCI RX of the Serial Communication Interface 
(SCI). The  
m 
P reads the SCI via signal SCI RX (pin 78) and writes via signal SCI TX (pin 79). Both 
signals are available on the accessory connector J0400 (SCI DATA OUT, SCI DATA IN). 
						

							 
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3.1-6Introduction/Theory of Operation
 
2.11 General Purpose Input/Output 
The Controller provides one general purpose line (GP I/O) available on the accessory connector 
J0400-12 to interface to external options. The software and the hardware configuration of the radio 
model defines the function of the port. The port uses an output transistor (Q0432) controlled by  
m 
P 
via ASFIC port GCB3 (pin B3).
An external alarm output, available on J0400 pin 4 is generated by the  
m 
P via ASFIC port GCB1 (pin 
A3) and transistor Q0411. Input EXTERNAL PTT on J0400 pin 3 is read by the  
m 
P via line REAR 
PTT and  
m 
P pin 8.
Pin 13 of the accessory connector J0400 provides a voltage at battery level while the radio is 
switched on. The output is capable to drive a dc current up to 20mA. When the radio is switched on, 
the voltage 9V3 turns on transistor Q0482. Transistor Q0482 switches on Q0481 and enables a 
current flow from emitter to collector of Q0481. This path has a very low impedance and effectively 
provides the same voltage level at SW FLT A+ as at FLT A+. If the radio is switched off the voltage 
9V3 is at ground level which switches off Q0482 and in turn cuts off the current from emitter to 
collector of Q0481.  
2.12 Normal Microprocessor Operation 
For this radio, the  
m 
P is configured to operate in one of two modes, expanded and bootstrap. In 
expanded mode the  
m 
P uses external memory devices to operate, whereas in bootstrap operation 
the  
m 
P uses only its internal memory. In normal operation of the radio the  
m 
P is operating in 
expanded mode as described below. 
In expanded mode on this radio, the  
m 
P (U0101) has access to three external memory devices; 
U0102 (FLASH EEPROM), U0103 (SRAM), U0104 or U0107 (optional EEPROM). Also, within the  
m 
P there are 768 bytes of internal RAM and 640 bytes of internal EEPROM, as well as logic to select 
external memory devices. 
The (optional) external EEPROM (U0104 or U0107) as well as the  
mP’s own internal EEPROM 
space contain the information in the radio which is customer specific, referred to as the codeplug. 
This information consists of items such as: 1) what band the radio operates in, 2) what frequencies 
are assigned to what channel, and 3) tuning information. In general tuning information and other 
more frequently accessed items are stored in the internal EEPROM (space within the 68HC11K1), 
while the remaining data is stored in the external EEPROM. (See the particular device subsection 
for more details.) 
The external SRAM (U0103) as well as the mP’s own internal RAM space are used for temporary 
calculations required by the software during execution. All of the data stored in both of these 
locations is lost when the radio powers off (See the particular device subsection for more details).
The FLASH EEPROM contains the actual Radio Operating Software. This software is common to all 
open architecture radios within a given model type. For example Securenet radios may have a 
different version of software in the FLASH EEPROM than a non-secure radio (See the particular 
device subsection for more details). 
The K1mP provides an address bus of 16 address lines (A0-A15), and a data bus of 8 data lines (D0-
D7). There are also three control lines; CSPROG (U0101-29) to chip select U0102-30 (FLASH 
EEPROM), CSGP2 (U0101-28) to chip select U0103-20 (SRAM) and PG7_R_W to select whether 
to read or to write. All other chips (ASFIC/PENDULLUM/DAC/FRACN/LCD/LED/optional EEPROM/
OPTION BOARD) are selected by 3 lines of the mP using address decoder U0105. When the mP is 
functioning normally, the address and data lines should be toggling at CMOS logic levels.  
						

							Open Controller
Introduction/Theory of Operation3.1-7
Specifically, the logic high levels should be between 4.8 and 5.0 V, and the logic low levels should be 
between 0 and 0.2 V. No other intermediate levels should be observed, and the rise and fall times 
should be 
						

							Open Controller
3.1-8Introduction/Theory of Operation
2.13 FLASH Electronically Erasable Programmable Memory 
(FLASH EEPROM)
The 512 KByte FLASH EEPROM (U0102) contains the radio operating software. This software is 
common to all open architecture radios within a given model type. This is, as opposed to the 
codeplug information stored in EEPROM (U0104) which could be different from one user to another 
in the same company.
In normal operating mode, this memory is only read, not written to. The memory access signals (CE, 
OE and WE) are generated by the mP.  
To upgrade/reprogram the FLASH software, the mP must be set in bootstrap operating mode, and 
the FLASH device pin (U0102-9) V
pp must be between 11.4 and 12.6 V. This voltage switches 
Q0102 on and in turn Q0103 off. The low state at collector of Q0102 pulls MODA LIR (U0101-77) 
and MODB VSTBY (U0101-76) via diode D0101 to low which enables the bootstrap operating mode 
after power up. The high state at collector of Q0103 enables the mP to control the FLASH EN OE 
(U0102-32) input via U0106-4. Chip select (U102-30) and read or write operation (U102-7) are 
controlled by mP pins 29 and 33. In normal operating mode V
PP is below 5V which switches Q0102 
off and Q0103 on.
The FLASH device may be reprogrammed 1,000 times without issue. It is not recommended to 
reprogram the FLASH device at a temperature below 0°C. 
Capacitor C0131 serves to filter out any AC noise which may ride on +5V at U0101, and C0132 
filters out any AC noise on V
pp.
2.14 Electrically Erasable Programmable Memory (EEPROM)
The optional EEPROM (U0104 or U0107) contains additional radio operating parameters such as 
operating frequency and signalling features, commonly known as the codeplug. It is also used to 
store radio operating state parameters such as current mode and volume. U0104 can have up to 
8kbyte and U0107 up to 16 kbyte. This memory can be written to in excess of 100,000 times and will 
retain the data when power is removed from the radio. The memory access signals (SI, SO and 
SCK) are generated by the mP and chip select (CS) is generated by address decoder U0105-4. 
Additional EEPROM is contained in the mP (U0101). This EEPROM is used to store radio tuning and 
alignment data. Like the external EEPROM this memory can be programmed multiple times and will 
retain the data when power is removed from the radio.
Note:The external EEPROM plus the 640 bytes of internal EEPROM in the 68HC11K1 comprise
the complete codeplug. 
						

							General
Introduction/Theory of Operation3.1-9
2.15 Static Random Access Memory (SRAM)
The SRAM (U0103) contains temporary radio calculations or parameters that can change very 
frequently, and which are generated and stored by the software during its normal operation. The 
information is lost when the radio is turned off. The device allows an unlimited number of write 
cycles. SRAM accesses are indicated by the CS signal U103-20 (which comes from U101-CSGP2) 
going low. U0103 is commonly referred to as the external RAM as opposed to the internal RAM 
which is the 768 bytes of RAM which is part of the 68HC11K1. Both RAM spaces serve the purpose. 
However, the internal RAM is used for the calculated values which are accessed most often. 
Capacitor C0133 serves to filter out any ac noise which may ride on +5V at U0103.
CONTROLLER BOARD AUDIO AND SIGNALLING CIRCUITS
3.0 General
3.1 Audio Signalling Filter IC (ASFIC)
The ASFIC (U0201) used in the controller has 4 functions;
n nRX/TX audio shaping, i.e. filtering, amplification, attenuation
n nRX/TX signalling, PL/DPL/HST/MDC/MPT
n nSquelch detection
n nMicroprocessor clock signal generation (see Microprocessor Clock Synthesizer Description 
Block).
The ASFIC is programmable through the SPI BUS (U0201-E3/F1/F2), normally receiving 21 bytes. 
This programming sets up various paths within the ASFIC to route audio and/or signalling signals 
through the appropriate filtering, gain and attenuator blocks. The ASFIC also has 6 General Control 
Bits GCB0-5 which are CMOS level outputs and used for AUDIO PA ENABLE (GCB0) to switch the 
audio PA on and off, EXTERNAL ALARM (GCB1) and B+ CONTROL (GCB2) to switch the voltage 
regulators (and the radio) on and off. GCB3 controls output GPI/O (accessory connector J0400-12), 
HIGH LOW BAND (GCB4) can be used to switch between band splits and GCB5 is available on the 
option board connector J0102-3. Output GCB4 controls gate U0171 via U0172-1 which enables the 
mP to receive data from the control head. The supply voltage for the ASFIC has additional filtering 
provided by Q0200, D0200, R0200, L0200 and C0200. Diode D0200 increases the voltage at the 
base of Q0200 about 0.6 volts above the 5 volt supply voltage to compensate the base - emiter 
voltage drop of Q0200.
3.2 Audio Ground
VAG is the dc bias used as an audio ground for the op-amps that are external to the Audio Signalling 
Filter IC (ASFIC). U0251-1 form this bias by dividing 9.3V with resistors R0251, R0252 and buffering 
the 4.65V result with a voltage follower. VAG emerges at pin 1 of U0251-1. C0253 is a bypass 
capacitor for VAG. The ASFIC generates its own 2.5V bias for its internal circuitry. C0221 is the 
bypass for the ASFIC’s audio ground dc bias. Note that while there are ASFIC VAG, and BOARD 
VAG (U0201-1) each of these are separate; they do not connect together. 
						

							Transmit Audio Circuits
3.1-10Introduction/Theory of Operation
4.0 Transmit Audio Circuits
Refer to Figure 3-1 for reference for the following sections.
4.1 Mic Input Path 
The radio supports two distinct microphone paths known as internal (from Control Head) and 
external mic (from accessory connector J0400-2) and an auxiliary path (FLAT TX AUDIO). The 
microphones used for the radio require a DC biasing voltage provided by a resistive network.
These two microphone audio inputs are connected together through R0413; resistors R0414 and 
R0415 are not placed. Following the internal mic path; the microphone is plugged into the radio 
control head and is connected to the controller board via J101-16. 
From here the signal is routed to R0206. R0204 and R0205 provide the 9.3VDC bias and R0206 
provides input protection for the CMOS amplifier input. R0205 and C0209 provide a 1kW AC path to 
ground that sets the input impedance for the microphone and determines the gain based on the 
emitter resistor in the microphone’s amplifier circuit.
Figure 3-1  Transmit Audio Paths
Filter capacitor C0210 provides low-pass filtering to eliminate frequency components above 3 kHz, 
and C0211 serves as a DC blocking capacitor. The audio signal at U0201-B8 should be 
approximately 80mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25 kHz channel spacing. 
The FLAT TX AUDIO signal from accessory connector J0400-5 is buffered by op-amp U0202-1 and 
fed to the ASFIC U0201-D7 through C0205.
MIC 
IN
MOD IN
TO
RF
SECTION
(SYNTHESIZER)
C7 A6
J0103-3
E8
C8H8
J0400
ACCESSORY
CONNECTOR
J0101
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
FLAT TX
AUDIOD7J0103-1
5A7
B8 16
GEPD 5426-1
2
IN
OUTOPTION
BOARD
FILTERS AND
PREEMPHASIS
LS SUMMER
SPLATTER
FILTER
HS SUMMER
LIMITER
ATTENUATORVCO 
ATN TX IN
MIC AMP OUT
MIC
IN
EXT 
MIC
IN
AUX 
TX IN
PRE EMP OUTLIM IN
ASFIC  U0201
GEPD5426-1