Motorola Gm1200e Detailled 68p64115b15 Manual

							Transmit Audio Circuits
Introduction/Theory of Operation3.1-11
4.2 External Mic Path
The external microphone signal enters the radio on accessory connector J0400 pin 2 and connects 
to the standard microphone input through R0413. Components R0414 - R0416, C0413, C0414, 
C0417 are not used.
4.3 PTT Sensing and TX Audio Processing
Mic PTT coming from the Control Head via connector J101-4 is sensed by the mP U0101 pin 22. An 
external PTT can be generated by grounding pin 3 on the accessory connector. When microphone 
PTT or externalPTT is sensed, the mP will always configure the ASFIC for the ”internal” mic audio 
path. 
Inside the ASFIC, the MIC audio is filtered to eliminate frequency components outside the 300-
3000Hz voice band, pre-emphasized if pre-emphasis is enabled. The capacitor between ASFIC pre-
emphasis out U0201-C8 and ASFIC limiter in U0201-E8 AC couples the signal between ASFIC 
blocks and prevents the DC bias at the ASFIC output U0201-H8 from shifting when the ASFIC 
transmit circuits are powered up. The signal is then limited to prevent the transmitter from over 
deviating. The limited MIC audio is then routed through a summer which, is used to add in signalling 
data, and then to a splatter filter to eliminate high frequency spectral components that could be 
generated by the limiter. The audio is then routed to two attenuators, which are tuned in the factory 
or the field to set the proper amount of FM deviation. The TX audio emerges from the ASFIC at 
U0201-H8 MOD IN, at which point it is routed to the RF section.
4.4 TX Secure Audio (optional)
The audio follows the normal transmit audio processing until it emerges from the ASFIC MIC AMP 
OUT pin (U0201-A6), which is fed to the Secure board residing at option connector J0103-3. The 
Secure board contains circuitry to amplify, encrypt, and filter the audio. The encrypted signal is then 
fed back from J0103-1 to the ASFIC TX IN input (U0201-C7). The signal level at this pin should be 
about 80mVrms. The signal is then routed through the TX path in the ASFIC and emerges at VCO 
ATN pin H8. 
						

							Transmit Signalling Circuits
3.1-12Introduction/Theory of Operation
5.0 Transmit Signalling Circuits
Refer to Figure 3-2 for reference for the following sections. From a hardware point of view, there are 
three types of signalling:
1.Sub-audible data (PL/DPL/Connect Tone) that gets summed with transmit voice or signalling,
2.DTMF data for telephone communication in trunked and conventional systems, and
3.Audible signalling including Select 5, MPT-1327, MDC, High speed Trunking.
NOTE: All three types are supported by the hardware while the radio software determines which 
signalling type is available.
Figure 3-2  Transmit Signalling Paths
5.1 Sub-audible Data (PL/DPL)
Sub-audible data implies signalling whose bandwidth is below 300Hz. PL and DPL waveforms are 
used for conventional operation and connect tones for trunked voice channel operation. The trunking 
connect tone is simply a PL tone at a higher deviation level than PL in a conventional system. 
Although it is referred to as ”sub-audible data,” the actual frequency spectrum of these waveforms 
may be as high as 250 Hz, which is audible to the human ear. However, the radio receiver filters out 
any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U0201 (ASFIC) at any one time. The 
process is as follows, using the SPI BUS, the mP programs the ASFIC to set up the proper low-
speed data deviation and select the PL or DPL filters. The mP then generates a square wave which 
strobes the ASFIC PL / DPL encode input PL CLK U0201-C3 at twelve times the desired data rate. 
For example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U0201 which generates a staircase approximation to a PL sine 
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice 
or data. The resulting summed waveform then appears on U0201-H8 (MOD IN), where it is sent to 
the RF board as previously described for transmit audio. A trunking connect tone would be 
generated in the same manner as a PL tone.
G1
C3 G2
H8
MOD INTO RF
SECTION
(SYNTHESIZER)
GEPD 5433 6 7 5HIGH SPEED
CLOCK IN
LOW SPEED 
CLOCK DTMF 
CLOCK
ASFIC   U0201
MICRO
CONTROLLER
U0101
HS
SUMMER
5-3-2 STATE 
ENCODER
DTMF 
ENCODERSPLATTER
FILTER
PL
ENCODERLS
SUMMER
ATTENUATOR
GEPD5433 
						

							Transmit Signalling Circuits
Introduction/Theory of Operation3.1-13
5.2 High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signalling Words 
(ISWs) used in a trunking system for high speed communication between the central controller and 
the radio. To generate an ISW, the mP first programs the ASFIC (U0201) to the proper filter and gain 
settings. It then begins strobing U0201-G1 (TRK CLK IN) with a pulse when the data is supposed to 
change states. U0201’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the post-
limiter summer block and then the splatter filter. 
From that point it is routed through the modulation attenuators and then out of the ASFIC to the RF 
board. MPT 1327 and MDC are generated in much the same way as Trunking ISW. However, in 
some cases these signals may also pass through a data pre-emphasis block in the ASFIC. Also 
these signalling schemes are based on sending a combination of 1200 Hz and 1800 Hz tones only. 
Microphone audio is muted during High Speed Data signalling.
5.3 Dual Tone Multiple Frequency (DTMF) Data 
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type of 
tones which are heard when using a ”Touch Tone” telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high 
group (1209, 1336, 1477Hz).
The high-group tone is generated by the mP (U0101-5) strobing U0201-G1 at six times the tone 
frequency for tones less than 1440Hz or twice the frequency for tones greater than 1440Hz. The low 
group tone is generated by the mP (U0101-7) strobing U0201-G2 (DTMF CLCK) at six times the tone 
frequency. Inside U0201 the low-group and high-group tones are summed (with the amplitude of the 
high group tone being approximately 2 dB greater than that of the low group tone) and then pre-
emphasized before being routed to the summer and splatter filter. The DTMF waveform then follows 
the same path as was described for high-speed data. 
						

							Receive Audio Circuits
3.1-14Introduction/Theory of Operation
6.0 Receive Audio Circuits
Refer to Figure 3-3 for reference for the following sections.
Figure 3-3  Receive Audio Paths.
6.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator U5201-28 (UHF) / 
U5201-28 (VHF) / U2201-28 (MB). This signal (DET AUDIO) is routed to the ASFIC’s squelch detect 
circuitry input SQ IN (U0201-H7). All of the squelch detect circuitry is contained within the ASFIC. 
Therefore from a user’s point of view, DET AUDIO enters the ASFIC, and the ASFIC produces two 
CMOS logic outputs based on the result. They are CH ACT (U0201-H2) and SQ DET (U0201-H1).
The squelch signal entering the ASFIC is amplified, filtered, attenuated, and rectified. It is then sent 
to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to produce 
SQ DET (U0201-H1) from CH ACT. The state of CH ACT and SQ DET is high (logic 1) when carrier 
is detected, otherwise low (logic 0).
FLT RX AUDIO
J040011
16
1EXTERNAL
SPEAKER
INTERNAL
SPEAKER
ACCESSORYCONNECTOR
CONTROL
HEAD
CONNECTOR
HANDSET
AUDIO 141 2
J0101 INT
SPKR-
SPKR +
SPKR -
1
9
ATTEN.
J0103-2
H6
J7 J6 J0103-4
J0103-5
DET AUDIO
 (DISCRIMINATOR  AUDIO)
GEPD 5428-2
H7J4
B2
INT
SPKR+
4
6
RX IN
PL INAUX RX IN
SQ IN
ASFIC
U0201
AUDIO 
PA
U0401
IN 2
OPTION
BOARD
IN 1 OUT
VOLUME
ATTEN.
FILTER AND
DEEMPHASIS
H1
MICRO 
CONTROLLER
U010110 FROM
RF
SECTION
(IF IC)
LIMITER, RECTIFIER
FILTER, COMPARATOR
SQ DET
UNAT RX OUT
SQUELCH
CIRCUIT
H2
PL  FILTER 
LIMITER
CH ACT
EXP AUDIO  INJ5
A4
PL
LIM
H5
UNIV IO
RX AUD OUT
*43
*Version before 0102726B09         PIN no is 25
Version 0102726B09/10               PIN no is 40
GEPD5428-2 
						

							Receive Audio Circuits
Introduction/Theory of Operation3.1-15
CH ACT is routed to the mP pin 40 while SQ DET adds up with LOCK DET, weighted by resistors 
R0113, R0114, and is routed to one of the mP´s ADC inputs U0101-43. From the voltage weighted 
by the resistors the mP determines whether SQ DET, LOCK DET or both are active.
SQ DET is used to determine all audio mute/unmute decisions except for Conventional Scan. In this 
case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.
6.2 Audio Processing and Digital Volume Control
The receiver audio signal enters the controller section from the IF IC U5201-28 (UHF) / U5201-28 
(VHF) / U2201-28 (MB) on DET AUDIO and passes through RC filter, R0203 and C0208 which 
filters out IF noise. The signal is AC coupled by C0207 and enters the ASFIC via the PL IN pin 
U0201-J7.
Inside the ASFIC, the signal goes through 2 paths in parallel, the audio path and the PL/DPL path. 
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth 
being received, then a LPF filter to remove any frequency components above 3000Hz and then an 
HPF to strip off any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis filter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects 
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level 
is set depending on the value of the volume control. Finally the filtered audio signal passes through 
an output buffer within the ASFIC. The audio signal exits the ASFIC at RX AUDIO (U0201-J4).
The mP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum /
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signalling is summed with voice information on transmit, it must be separated 
from the voice information before processing. Any sub-audible signalling enters the ASFIC from the 
IF IC at PL IN U0201-J7. Once inside it goes through the PL/DPL path. 
The signal first passes through one of 2 low pass filters, either PL low pass filter or DPL/LST low 
pass filter. Either signal is then filtered and goes through a limiter and exits the ASFIC at PL LIM 
(U0201-A4). At this point the signal will appear as a square wave version of the sub-audible signal 
which the radio received. The microprocessor (U0101-10) will decode the signal directly to 
determine if it is the tone/code which is currently active on that mode.
6.3 Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC’s digital volume pot, U0201-J4 is routed through a voltage divider formed 
by R0401 and R0402 to set the correct input level to the audio PA (U0401). This is necessary 
because the gain of the audio PA is 46 dB, and the ASFIC output is capable of overdriving the PA 
unless the maximum volume is limited.
The audio then passes through C0401 which provides AC coupling and low frequency roll-off. 
C0402 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the audio 
power amplifier U0401.
The audio power amplifier has one inverted and one non-inverted output that produces the 
differential audio output SPK+ / SPK- (U0401-4/6). The inputs for each of these amplifiers are pins 1 
and 9 respectively; these inputs are both tied to the received audio. The audio PA’s DC biases are 
not activated until the audio PA is enabled at pin 8. 
						

							Receive Audio Circuits
3.1-16Introduction/Theory of Operation
The audio PA is enabled via AUDIO PA ENABLE signal from the ASFIC (U0201-B5). When the base 
of Q0401 is low, the transistor is off and U0401-8 is high, using pull up resistor R0406, and the Audio 
PA is ON. The voltage at U0401-8 must be above 8.5VDC to properly enable the device. If the 
voltage is between 3.3 and 6.4V, the device will be active but has its input (U0401-1/9) off. This is a 
mute condition which is not employed in this radio design. R0404 ensures that the base of Q0401 is 
high on power up. Otherwise there may be an audio pop due to R0406 pulling U0401-8 high before 
the software can switch on Q0401.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT 
A+ (U0401-7). FLT A+ of 11V yields a DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V. 
If either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ 
and SPK- are routed to the accessory connector (J400-16 and 1) and to the control head (connector 
J0101-1 and 2).
6.4 Handset Audio
Certain hand held accessories have a speaker within them which require a different voltage level 
than that provided by U0401. For those devices HANDSET AUDIO is available at J0101-14.
The received audio from the output of the ASFIC’s digital volume attenuator is also routed to U0202-
4 pin 9 where it is amplified 15 dB; this is set by the 10k/68k combination of R0233 and R0232. This 
signal is routed from the output of the op amp U202-4 pin 8 to J0101-14. The control head sends this 
signal directly out to the microphone jack. The maximum value of this output is 6.6Vp-p.
6.5 Filtered Audio
The ASFIC has an audio whose output at U0201-B2 has been filtered and de-emphasized, but has 
not gone through the digital volume attenuator. From ASFIC U0201-B2 the signal is AC coupled to 
U0202-2 by capacitor C0230. R0224 and R0225 determine the gain of op-amp U0202-2. The output 
of U0202-2 is the routed to J0400-11.Note that any volume adjustment of the signal on this path 
must be done by the accessory.
6.6 RX Secure Audio (optional)
Discriminator audio, which is now encrypted audio, enters the Secure board at connector J0103-5. 
On the Secure board, the encrypted signal is converted back to normal audio format, and then fed 
back through (J0103-2) to RX IN of the ASFIC (U0201-H6). From then on it follows a path identical 
to conventional receive audio, where it is filtered (0.3 - 3kHz) and de-emphasized. The signal UNAT 
RX OUT from the ASFIC (U0201-H5), also routed to option connector J0103-4, is not used for the 
Secure board but for other option boards. 
						

							Receive Signalling Circuits
Introduction/Theory of Operation3.1-17
7.0 Receive Signalling Circuits
Refer to Figure 3-4 for reference for the following sections.
Figure 3-4  Receive Signalling Path.
7.1 Sub-audible Data (PL/DPL) and High Speed Data Decoder
The ASFIC (U0201) is used to filter and limit all received data. The data enters the ASFIC at U0201-
J7. Inside U0201 the data is filtered according to data type (HS or LS), then it is limited to a 0-5V 
digital level. The MDC and trunking high speed data appear at U0201-G4, where it connects to the 
mP U0101-11
The low speed limited data output (PL, DPL, and trunking LS) appears at U0201-A4, where it 
connects to the mP U0101-10. While receiving low speed data, the mP may output a sampling 
waveform, depending on the sampling technique, to U0201-C3 between 1 and 2 kHz.
The low speed data is read by the mP at twice the frequency of the sampling waveform; a latch 
configuration in the ASFIC stores one bit every clock cycle. The external capacitors C0226, C0225, 
and C0223 set the low frequency pole for a zero crossings detector in the limiters for PL and HS 
data. The hysteresis of these limiters is programmed based on the type of received data. Note that 
during HS data the mP may generate a sampling waveform seen at U0201-G1.
7.2 Alert Tone  Circuits
When the software determines that it needs to give the operator an audible feedback (for a good key 
press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures), it 
sends an alert tone to the speaker.
It does so by sending SPI BUS data to U0201 which sets up the audio path to the speaker for alert 
tones. The alert tone itself can be generated in one of two ways: internally by the ASFIC, or 
externally using the mP and the ASFIC.
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF  IC)G4
A4
GEPD 5431C5J3
G1C3
J7
11
1065
LOW SPEED
CLOCK
PL
IN
RX LIM
CAPPL
LIMRX
LIM
OUT
LOW SPEED
LIM CAP HIGH SPEED
CLOCK
DATA FILTER
AND DEEMPHASISLIMITER
FILTER
LIMITER
ASFIC
U0201
MICRO
CONTROLLER
U0101
GEPD5431 
						

							Receiver Front-End
3.1-18Introduction/Theory of Operation
The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained 
within the SPI BUS load to the ASFIC sets up the path and determines the tone frequency, and at 
what volume level to generate the tone. (It does not have to be related to the voice volume setting).
For external alert tones, the mP can generate any tone within the 100-3000Hz audio band. This is 
accomplished by the mP generating a square wave which enters the ASFIC at U0201-C3.
Inside the ASFIC, this signal is routed to the alert tone generator. The output of the generator is 
summed into the audio chain just after the RX audio de-emphasis block. Inside U0201 the tone is 
amplified and filtered, then passed through the 8-bit digital volume attenuator, which is typically 
loaded with a special value for alert tone audio. The tone exits at U0201-J4 and is routed to the 
audio PA like receive audio.
UHF (403-470MHz) SPECIFIC CIRCUIT DESCRIPTION
8.0 Receiver Front-End
The receiver is able to cover the UHF range from 403 to 470 MHz. It consists of four major blocks: 
front-end, mixer, first IF section and IF IC. Antenna signal pre-selection is performed by two varactor 
tuned bandpass filters. A double balanced shottky diode mixer converts the signal to the first IF at 
45.1 MHz. 
Two crystal filters in the first IF section and two ceramic filters in the second IF section provide the 
required selectivity. The second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The 
processing of the demodulated audio signal is performed by an audio processing IC located in the 
controller section.
8.1 Front-End Band-Pass Filter & Pre-Amplifier
A two pole pre-selector filter tuned by the varactor diodes D5301 and D5302 pre-selects the 
incoming signal (PA RX) from the antenna switch to reduce spurious effects to following stages. The 
tuning voltage (FE CNTL VLTG) ranging from 2 volts to 8 volts is controlled by a Digital to Analogue 
(D/A) converter (U0731-11) in the controller section. A dual hot carrier diode (D5303) limits any 
inband signal to 0 dBm to prevent damage to the pre-amplifier.
The RF pre-amplifier is an SMD device (Q5301) with collector base feedback to stabilize gain, 
impedance, and intermodulation. The collector current of approximately 11-16 mA is drawn from the 
voltage 9V3 via L5302 and R5302. A 3dB pad (R5306 - R5308 and R5317 - R5319) stabilizes the 
output impedance and intermodulation performance. 
A second two pole varactor tuned bandpass filter provides additional filtering to the amplified signal. 
The varactor diodes D5304 and D5305 are controlled by the same signal which controls the pre-
selector filter. A following 1 dB pad (R5310, R5314, R5316) stabilizes the output impedance and 
intermodulation performance
If the UHF radio is configured for a base station application, R5319 is not placed and TP5301 and 
TP5302 are shorted. 
						

							Transmitter Power Amplifier (PA) 5-25W
Introduction/Theory of Operation3.1-19
8.2 Mixer and Intermediate Frequency (IF) Section
The signal coming from the front-end is converted to the first IF (45.1 MHz) using a double balanced 
schottky diode mixer (D5401). Its ports are matched for incoming RF signal conversion to the 
45.1MHz IF using low side injection. The injection signal (VCO MIXER) coming from the mixer buffer 
(Q5771) is filtered by the lowpass consisting of (L5403, L5404, C5401 - C5403) and has a level of 
approximately 10 dBm.
The mixer IF output signal (RX IF) from transformer T5401 pin 2 is fed to the first two pole crystal 
filter Y5201. The filter output in turn is matched to the following IF amplifier.
The IF amplifier Q5201 is actively biased by a collector base feedback (R5201, R5202) to a current 
drain of approximately 5 mA drawn from the voltage 5V STAB. Its output impedance is matched to 
the second two pole crystal filter Y5202. A dual hot carrier diode (D5201) limits the filter output 
voltage swing to reduce overdrive effects at RF input levels above -27 dBm.
8.3 IF IC (U5201)
The first IF signal from the crystal filters feeds the IF IC (U5201) at pin 6. Within the IF IC the 
45.1MHz first IF signal mixes with the second local oscillator (LO) at 44.645MHz to the second IF at 
455 kHz. The second LO uses the external crystal Y5211. The second IF signal is amplified and 
filtered by two external ceramic filters (FL5201, FL5202). Back in the IF IC the signal is demodulated 
in a phase-lock detector and fed from IF IC pin 28 to the audio processing circuit ASFIC U0201 
located in the controller section (line DET AUDIO).
The squelch circuit of the IF IC is not used. Instead the squelch circuit inside the audio processing 
IC ASFIC (U0201) determines the squelch performance and sets the squelch threshold. The 
detector output signal from IF IC (U5201) pin 28 (DET_AUDIO) is fed to the ASFIC pin H7.At IF IC 
pin 11 an RSSI signal is available with a dynamic range of 70 dB. 
The RSSI signal is interpreted by the microprocessor (U0101 pin 44) and in addition after buffering 
by op-amp U0202-3 available at accessory connector J0400-15.
9.0 Transmitter Power Amplifier (PA) 5-25W
The radio’s 5-25 W PA is a four stage amplifier used to amplify the output from the exciter to the 
radio transmit level. It consists of the following four stages in the line-up. The first (Q5510) is a 
bipolar stage that is controlled via the PA control line (line PWR CNTL). It is followed by another 
bipolar stage (Q5520), a MOS FET stage (Q5530) and a final bipolar stage (Q5536).
Devices Q5510 and Q5520 are surface mounted. Bipolar Transistor Q5536 and MOS FET Q5530 
are directly attached to the heat sink.
9.1 Power Controlled Stage 
The first stage (Q5510) amplifies the RF signal from the VCO (line EXCITER PA) and controls the 
output power of the PA. The output power of the transistor Q5510 is proportional to its collector 
current which is adjusted by a voltage controlled current source consisting of Q5612, Q5611 and 
Q5621. The whole stage operates off the K9V1 source which is 9.1V in transmit mode and nearly 0V 
in receive mode. 
						

							Transmitter Power Amplifier (PA) 5-25W
3.1-20Introduction/Theory of Operation
The collector current of Q5510 causes a voltage drop across the resistors R5623 and R5624. 
Transistor Q5612 adjusts the voltage drop across R5621 controlled through the PA control line 
(PWR CNTL). The current source Q5621 adjusts the collector current of Q5510 by modifying its 
base voltage via (R5502, L5501) until the voltage drop across R5623 and R5624 plus V
BE (0.6V) 
equals the voltage drop across R5621 plus V
BE (0.6V) of Q5611. If the voltage of PWR CNTL is 
raised, the base voltage of Q5612 will also rise causing more current to flow to the collector of 
Q5612 and a higher voltage drop across R5621. This in turn results in more current driven into the 
base of Q5510 by Q5621 so that the collector current of Q5510 is increased. The collector current 
settles when the voltage over the series configuration of R5623 and R5624 plus V
BE (0.6V) of 
Q5621 equals the voltage over R5621 plus V
BE (0.6V) of Q5611. 
By controlling the output power of Q5510 and in turn the input power of the following stages the ALC 
loop is able to regulate the output power of the transmitter. Q5611 is used for temperature 
compensation of the PA output power.
In receive mode the PA control line (PWR CNTL) is at ground level and switches off the collector 
current of Q5612 which in turn switches off the current source transistor Q5621 and the RF 
transistor Q5510. 
9.2 PA Stages 
The bipolar transistor Q5520 is driven by Q5510. To reduce the collector - emitter voltage and in turn 
the power dissipation of Q5510 its collector current is drawn from the antenna switch circuit.
In transmit mode the base of Q5520 is slightly positive biased by a divided K9V1 signal. This bias 
along with the RF signal from Q5510 allows a collector current to be drawn from the antenna switch 
circuit and in turn switches the antenna switch to transmit, while in receive mode the low K9V1 
signal with no RF signal present cuts off the collector current and in turn switches the antenna 
switch to receive. 
The following stage uses an enhancement mode N-Channel MOS FET device (Q5530) and requires 
a positive gate bias and a quiescent current flow for proper operation. The voltage of the line BIAS 
VLTG is set in transmit mode by a Digital to Analogue (D/A) converter (U0731-4) and fed to the gate 
of Q5530 via the resistive network R5521, R5522 and R5523. The bias voltage is tuned in the 
factory. If the transistor is replaced, the bias voltage must be tuned with the Dealer Programming 
Software (DPS). Care must be taken, not to damage the device by exceeding the maximum allowed 
bias voltage. The collector current is drawn from the supply voltage A+ via L5532.
The final stage uses the bipolar device Q5536 and operates off the A+ supply voltage. For class C 
operation the base is DC grounded by two series inductors (L5533, L5534). A matching network 
consisting of C5541-C5544 and two striplines transforms the impedance to 50 Ohms and feeds the 
directional coupler.
9.3 Directional Coupler 
The directional coupler is a microstrip printed circuit which couples a small amount of the forward 
power off the RF power from Q5536. The coupled signal is rectified to an output power proportional 
negative DC voltage by the diode D5553 and sent to the power control circuit in the controller 
section via the line PWR DETECT for output power control. The power control circuit holds this 
voltage constant, thus ensuring the forward power out of the radio to be held to a constant value.