Motorola Gm1200e Detailled 68p64115b15 Manual

							 
Theory of Operation
Introduction/Theory of Operation2.1-5
 
When the host radio needs to communicate to the control head  
m  
P it brings the control head select 
line (CNTL HD CE) to a logic ‘0’ and then sends the proper data and clock signals. After the data has 
been sent the control head select line is returned to a logic ‘1’. When the control head  
m  
P wants to 
communicate to the host radio the  
m 
P brings request line CNTL HD REQ to a logic ‘0’ by switching 
on transistor Q0931 via  
m 
P pin 11. The host radio then starts communication by activating the 
control head select line (CNTL HD CE), sending the clock signal and sending data via SPI MOSI or 
receiving data via SPI MISO and buffer U0931-1. 
3.7 Keypad Keys 
The control head keypad is a 26 - key keypad. All keys are configured as 6 analogue lines (AN 0 - 5) 
to the control head  
m 
P. Lines AN 0 - 3 each control four keys, lines AN 4, 5 each control five keys. 
The voltage on the analogue lines varies between 0V and +5V depending on which key has been 
pressed. If a button is pressed, it will connect one of the 6 lines AN 0 - 5 to a resistive voltage divider 
R0807 - R0811 connected to +5V. The voltages of the lines are A/D converted inside the  
m  
P (ports 
PE 0 - 5) and specify the pressed button. 
3.8 Status LED and Back Light Circuit 
All the indicator LEDs (D0881 - D0884) are driven by current sources Q0881 - Q0883. To change 
the LED status the host radio sends a data message via SERIAL PERIPHERAL INTERFACE (SPI) 
to the control head  
m 
P. The control head  
m 
P determines the LED status from the received message 
and switches the LEDs on or off via pins 5, 6, 7. The LED status is stored in the  
m  
P’s memory. The 
LED current is determined by the resistor at the emitter of the respective current source transistor.
The backlight for the LCD and the keypad is controlled by the host radio the same way as the 
indicator LEDs using  
m 
P pins 8, 9, 10. The keypad backlight current is drawn from the FLT A+ source 
and controlled by transistor Q0851. The current flowing through the LEDs cause a proportional 
voltage drop across the parallel resistors R0861, R0862. This voltage drop is amplified by the op-
amp U0831-2. U0831-2 and Q0852 form a differential amplifier. The voltage difference between the 
base of Q0852 and the output of U0831-2 determines the current from the base of the LED control 
transistor Q0851 and in turn the brightness of the LEDs. The  
m 
P can switch the LEDs on and off by 
a logic high or low level at the port connected to the base of Q0852. If the base of Q0852 is at 
ground level, Q0852 is switched off and no current flows through Q0851 and the LEDs. If the  
m  
P port 
changes to +5V a current flows through Q0852 and in turn through Q0851 causing the LEDs to turn 
on and a rising voltage drop across R0861, R0862. The rising voltage causes the output of the op-
amp to rise and to reduce the base to emitter voltage of Q0852. This decreases the current of 
Q0852 until the loop has settled. The backlight for the LCD uses a similar circuit. By using two  
m  
P 
ports (pin 8, 9) and different weighting resistors R0837 and R0838 the base of Q0832 can be set to 
four different voltage levels. This allows to switch the LEDs off or to select among three levels of 
brightness. 
3.9 Liquid Crystal Display (LCD) 
The LCD module U0902 consists of the display and the display driver. The display is a single layer 
super twist nematic (STN) LCD display. It has a dot matrix of 24 x120 dots for displaying graphics 
and alpha - numerical information, a line with 19 pre - defined icons below the dot matrix and line 
with 11 bars below the icon line. Six of the bars can be used to display the status of the keys located 
below. 
						

							 
Theory of Operation
2.1-6Introduction/Theory of Operation
 
The display driver is fixed on the flex which connects the display to the PC board. The driver 
contains a data interface to the  
m 
P, an LCD segment driver, an LCD power circuit, an oscillator, data 
RAM and control logic. At power up the driver’s control logic is reset by a logic ‘0’ at input RES 
(U0902-9). Resistor R0946 sets the driver’s internal oscillator to about 18 kHz. By connecting U0902 
pin 12 to +5V the driver’s  
m 
P interface is configured to accept 8 bit parallel data input (U0902-D0-D7) 
from the control head  
m 
P (U0901 port PC0-PC7). Pin 15 connected to +5V sets the 6800  
m  
P control 
mode.
To write data to the driver’s RAM the  
m 
P sets chip select (U0902-14) to logic ‘1’ via U0901-59 and R/
W (U0902-17) to logic ‘0’ via U0901-56. With input A0 (U0902-16) set to logic ‘0’ via U0901-58 the  
m 
P writes control data to the driver. Clock signal E at pin 18 generated by  
m 
P pin 57, shifts 8 bit 
parallel data into the driver. Control data includes the RAM start address for the following display 
data. With input A0 set to logic ‘1’ the  
m 
P then writes the display data to the display RAM. When data 
transfer is complete the  
m 
P terminates the chip select and the clock activities.
The voltage supply for the display is provided by the display driver power circuit. This circuit consists 
of a voltage multiplier, voltage regulator and a voltage follower. To use an external voltage supply the 
built-in power circuit can be turned off by a control command. The settings of the inputs T1 (U0902-
36) and T2 (U0902-35) select among the various functions of the power circuit. With both inputs set 
to ground level by resistors R0955 and R0956 the voltage multiplier, the voltage regulator and the 
voltage follower are activated and no external voltage supply is required for the LCD. The external 
capacitors C0951 - C0953 configure the multiplier to triple the supply voltage. If R0957 is used 
instead of C0952 the multiplier doubles the supply voltage. In this configuration the multiplier output 
VOUT (U0902-42) supplies a voltage of -5V (2* -5V below VDD). The multiplied voltage VOUT is 
sent to the internal voltage regulator. To set the voltage level of the regulator output V5 (U0902-43) 
this voltage is divided by the resistors R0958 and R0959 and feed back to the reference input VR 
(U0902-44). In addition the regulator output voltage V5 can be controlled electronically by a control 
command sent to the driver. With the used configuration the voltage V5 is about -3V. The voltage V5 
is resistively divided by the driver’s voltage follower to provide the voltages V1 - V4. These voltages 
are needed for driving the liquid crystals. The driver circuit can be configured to use externally 
generated voltages for VOUT and V1 - V5. In this case the +5V supply voltage is multiplied by the  
m  
P 
(U0901-62) along with the multiplier circuit D0911, C0911, C0912, R0911 and R0913. The  
m  
P 
provides a square wave signal at pin 62 to drive the multiplier circuit. The voltages V1-V4 are 
generated from VOUT or V5 by the resistive divider R0941 - R0945 and supplied to the driver ports 
V1 - V5. Dependent on the configuration the level of VOUT or V5 can be measured by one of the  
m 
P’s analogue to digital converters (U0901-20) via resistive divider R0914, R0915. To stabilize the 
display brightness over a large temperature range the  
m 
P measures the temperature via analogue to 
digital converter (U0901-18) using thermistor R0918 and resistor R0917. Dependent on the 
measured temperature the  
m 
P adjusts the driver output voltage V5, and in turn the display 
brightness, via parallel interface. 
3.10 Microphone Connector 
Signals BUS+, PTT, HOOK, MIC HI, HANDSET AUDIO and FLT A+ available at the microphone 
connector J0903, are connected to the radio’s controller section via connector J0901. 
3.11 Electrostatic Transient  Protection 
Electrostatic transient protection is provided for the sensitive components in the control head by 
diodes VR0901 - VR0905, VR0931 - VR0935. The diodes limit any transient voltages to tolerable 
levels. The associated capacitors provide Radio Frequency Interference (RFI) protection. 
						

							 
PCB/Schematic Diagram and Parts List2.2-i 
Chapter 2.2 
PCB/Schematic Diagram and Parts List 
Table of Contents 
Table of Contents 
Description Page 
Display/Keypad Radio Control Head (K6) - Diagrams and Parts Lists 
PCB Layout Top Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PCB Layout Bottom Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Schematic Diagram  1 of 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Schematic Diagram  2 of 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 
						

							 
Table of Contents
2.2-iiPCB/Schematic Diagram and Parts List 
						

							 
UHF/VHF Radio - Level 3 Information3-i 
Chapter 3 
UHF/VHF Radio - Level 3 Information 
Table of Contents 
Table of Contents 
Chapter 
3.1 Introduction/Theory of Operation
3.2 PCB/Schematic Diagrams and Parts Lists 
						

							 
Table of Contents
3-iiUHF/VHF Radio - Level 3 Information 
						

							 
Introduction/Theory of Operation3.1-i 
Chapter 3.1 
Introduction/Theory of Operation 
Table of Contents 
Table of Contents 
Paragraph Page 
1.0 Introduction  
................................................................................................  1  
2.0 Open Controller  
..........................................................................................  1
2.1 General ........................................................................................................  1
2.2 Voltage Regulators ......................................................................................  1
2.3 Electronic On/Off .........................................................................................  2
2.4 Emergency...................................................................................................  2
2.5 Mechanical On/Off .......................................................................................  3
2.6 Ignition .........................................................................................................  3
2.7 Hook RSS ....................................................................................................  3
2.8 Microprocessor Clock Synthesizer ..............................................................  4
2.9 Serial Peripheral Interface ( 
SPI 
) ...................................................................  4
2.10 SPEB Serial Interface ..................................................................................  5
2.11 General Purpose Input/Output .....................................................................  6
2.12 Normal Microprocessor Operation ...............................................................  6
2.13 FLASH Electronically Erasable Programmable Memory ( 
FLASH EEPROM 
).. 8
2.14 Electrically Erasable Programmable Memory ( 
EEPROM 
) .............................  8
2.15 Static Random Access Memory ( 
SRAM 
).......................................................  9  
Controller Audio and Signalling Circuits
3.0 General 
.......................................................................................................  9
3.1 Audio Signalling Filter IC ( 
ASFIC 
) .................................................................  9
3.2 Audio Ground...............................................................................................  9 
4.0 Transmit Audio Circuits 
...........................................................................  10
4.1 Mic Input Path ............................................................................................  10
4.2 External Mic Path.......................................................................................  11
4.3 PTT Sensing and TX Audio Processing ....................................................  11
4.4 TX Secure Audio (optional)........................................................................  11 
						

							 
Table of Contents
3.1-iiIntroduction/Theory of Operation
 
Paragraph Page 
5.0 Transmit Signalling Circuits 
...................................................................  12
5.1 Sub-audible Data (PL/DPL) .......................................................................  12
5.2 High Speed Data .......................................................................................  13
5.3 Dual Tone Multiple Frequency (DTMF) Data .............................................  13 
6.0 Receive Audio Circuits 
............................................................................  14
6.1 Squelch Detect ..........................................................................................  14
6.2 Audio Processing and Digital Volume Control ...........................................  15
6.3 Audio Amplification Speaker (+) Speaker (-) .............................................  15
6.4 Handset Audio ...........................................................................................  16
6.5 Filtered Audio ............................................................................................  16
6.6 RX Secure Audio (optional) .......................................................................  16 
7.0 Receive Signalling Circuits 
.....................................................................  17
7.1 Sub-audible Data (PL/DPL) and High Speed Data Decoder .....................  17
7.2 Alert Tone Circuits .....................................................................................  17 
UHF (403-470MHz) SPECIFIC CIRCUIT DESCRIPTION
8.0 Receiver Front-End 
..................................................................................  18
8.1 Front-End Band-Pass Filter & Pre-Amplifier ..............................................  18
8.2 Mixer and Intermediate Frequency (IF) Section ........................................  19
8.3 IF IC (U5201) .............................................................................................  19 
9.0 Transmitter Power Amplifier (PA) 5-25W 
...............................................  19
9.1 Power Controlled Stage.............................................................................  19
9.2 PA Stages..................................................................................................  20
9.3 Directional Coupler ....................................................................................  20
9.4 Antenna Switch..........................................................................................  21
9.5 Harmonic Filter ..........................................................................................  21
9.6 Power Control ............................................................................................  21 
10.0 Frequency Synthesis 
...............................................................................  23
10.1 Reference Oscillator ..................................................................................  23
10.2 Fractional-N Synthesizer (U5701) .............................................................  23
10.3 Voltage Controlled Oscillator (VCO) ..........................................................  24
10.4 Synthesizer Operation ...............................................................................  24 
						

							 
Table of Contents
Introduction/Theory of Operation3.1-iii  
 
Paragraph Page 
VHF (136-174MHz) SPECIFIC CIRCUIT DESCRIPTION
11.0 Receiver Front-End 
.................................................................................  25
11.1 Front-End Band-Pass Filter and Pre-Amplifier ..........................................  25
11.2 Mixer and Intermediate Frequency (IF) Section ........................................  26
11.3 IF IC (U5201) ............................................................................................  26 
12.0 Transmitter Power Amplifier (PA) 5-25W 
...............................................  26
12.1 Power Controlled Stage ............................................................................  27
12.2 PA Stages .................................................................................................  27
12.3 Directional Coupler ...................................................................................  27
12.4 Antenna Switch .........................................................................................  28
12.5 Harmonic Filter ..........................................................................................  28
12.6 Power Control ...........................................................................................  28 
13.0 Frequency Synthesis 
..............................................................................  30
13.1 Reference Oscillator .................................................................................  30
13.2 Fractional-N Synthesizer (U3701) .............................................................  30
13.3 Voltage Controlled Oscillator (VCO) .........................................................  30
13.4 Synthesizer Operation ..............................................................................  31 
						

							 
Table of Contents
3.1-ivIntroduction/Theory of Operation