Motorola Gm Series Detailed 6864115b62 A Manual

							VHF (136-174MHz) Frequency Synthesis2-7
A voltage of 5V applied to the super filter input (U3201 pin 30) supplies an output voltage of 4.5 VDC 
(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R3363) and the synthesizer 
charge pump resistor network (R3251, R3252). The synthesizer supply voltage is provided by the 
5V regulator U3211.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U3201-47), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry 
(D3201, C3202, C3203). This voltage multiplier is basically a diode capacitor network driven by two 
(1.05MHz) 180 degrees out of phase signals (U3201-14 and -15).
Output LOCK (U3201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U3201 provides the 16.8 MHz reference frequency at 
pin 19.
The serial interface (SRL) is connected to the microprocessor via the data line DATA (U3201-7), 
clock line CLK (U3201-8), and chip enable line CSX (U3201-9).
4.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U3301), the TX 
and RX tank circuits, the external RX buffer stages, and the modulation circuitry.
Figure 2-1 VHF VCO Block Diagram
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U3211 Pin1)
VCC Buffers
TX RF Injection U3201 Pin 32 AUX3 (U3201 Pin2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U3301
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15 Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6RX
TX
(U3201 Pin28)Rx-SW
Tx-SW
Vcc-Logic
(U3211 Pin1) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION
Q3304
Q3301 
						

							2-8THEORY OF OPERATION
The VCOBIC together with the Fractional-N synthesizer (U3201) generates the required frequencies 
in both the transmit and receive modes. The TRB line (U3301 pin 19) determines which tank circuits 
and internal buffers are to be enabled. A high level on TRB enables the TX tank and TX output (pin 
10), and a low enables the RX tank and RX output (pin 8). A sample of the signal from the enabled 
RF output is routed from U3301 pin 12 (PRESC_OUT), via a low pass filter, to pin 32 of U3201 
(PREIN).
A steering line voltage (VCTRL) between 2.5V and 11V at varactor diode D3361 will tune the full TX 
frequency range (TXINJ) from 136 MHz to 174 MHz, and at varactor diode D3341 will tune the full 
RX frequency range (RXINJ) from 181 MHz to 219 MHz. The RX tank circuit uses a Hartley 
configuration for wider bandwidth. For the RX tank circuit, an external transistor Q3304 is used for 
better side-band noise.
The external RX buffers (Q3301 and Q3302) are enabled by a high at U3301 pin 7 (RX_SWITCH) 
via transistor switch Q3303. In the TX mode, the modulation signal (VCOMOD) from the LVFRAC-N 
synthesizer IC (U3201 pin 41) is applied to varactor diode D3362, which modulates the TX VCO 
frequency via capacitor C3362. Varactor D3362 is biased for linearity from VSF.
4.4 Synthesizer Operation
The complete synthesizer subsystem consists of the low voltage FRAC-N (LVFRACN), the 
reference oscillator (a crystal oscillator with temperature compensation), charge pump circuitry, loop 
filter circuitry and a DC supply. The output signal PRESC from the VCOBIC (U3301 pin 12) is fed to 
U3201 pin 32  (PREIN) via a low pass filter (C3318, L3318 and C3226) which attenuates harmonics 
and provides the correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U3201) is a dual modulus type with selectable divider ratios. The 
divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs via the 
SRL. The output of the pre-scaler is applied to the loop divider. The output of the loop divider is 
connected to the phase detector, which compares the loop divider´s output signal with the reference 
signal. The reference signal is generated by dividing down the signal of the reference oscillator 
(Y3261 or Y3263).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump. 
The charge pump outputs a current at U3201 pin 43 (IOUT). The loop filter (which consists of 
R3221-R3223 and C3221-C3224) transforms this current into a voltage that is applied to the 
varactor diodes (D3361 for transmit, D3341 for receive) to alter the output frequency of the 
appropriate VCO. The current can be set to a value fixed within the LVFRAC-N IC, or to a value 
determined by the currents flowing into BIAS 1 (U3201-40) or BIAS 2 (U3201-39). The currents are 
set by the value of R3251 and R3252 respectively. The selection of the three different bias sources is 
done by software programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer, the 
magnitude of the loop current is increased by enabling the IADAPT pin (U3201-45) for a certain 
software programmable time (adapt mode). The adapt mode timer is started by a low to high 
transient of the CSX line. When the synthesizer is within the lock range, the current is determined 
only by the resistors connected to BIAS 1 and BIAS 2, or by the internal current source. A settled 
synthesizer loop is indicated by a high level signal at U3201-4 (LOCK).
The LOCK signal is routed to one of the µP´s ADC inputs (U0101-56). From the measured voltage, 
the µP determines whether LOCK is active.
In order to modulate the PLL, the two spot modulation method is utilized. Via U3201 pin 10 (MODIN), 
the audio signal is applied to both the A/D converter (low frequency path) as well as the balance 
attenuator (high frequency path). The A/D converter changes the low frequency analog modulating  
						

							VHF (136-174MHz) Transmitter Power Amplifier (PA) 45 W 2-9
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The 
balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency modulating 
signals. The output of the balance attenuator is present at the MODOUT port (U3201-41) and 
connected to the VCO modulation diode D3362 via R3364.
5.0 VHF (136-174MHz) Transmitter Power Amplifier (PA) 45 W
The radio’s 45 W PA is a four stage amplifier used to amplify the output from the VCOBIC to the 
radio transmit level. The line-up consists of three stages which utilize LDMOS technology, followed 
by a final stage using a bipolar device. The gain of the first stage (U3401) is adjustable, controlled by 
pin 4 of PCIC (U3501) via Q3501 and Q3502 (VCONT). It is followed by an LDMOS pre-driver stage 
(Q3421), an LDMOS driver stage (Q3431) and a bipolar final stage (Q3441).
Figure 2-1 VHF Transmitter Block Diagram 
Devices U3401 and Q3421 are surface mounted. The remaining devices are directly attached to the 
heat sink.
5.1 Power Controlled Stage
The first stage (U3401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier 
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U3401 is 
controlled by a DC voltage applied to pin 1 from the power control circuit (U3501 pin 4, with 
transistors Q3501 and Q3502 providing current gain and level-shifting). The control voltage 
simultaneously varies the bias of two FET stages within U3401. This biasing point determines the 
overall gain of U3401 and therefore its output drive level to Q3421, which in turn controls the output 
power of the PA.
In receive mode the voltage control line is at ground level and turns off Q3501-2, which in turn 
switches off the biasing voltage to U3401.
Antenna
To Microprocessor
PCIC
Pin Diode 
Antenna 
Switch
RF Jack
Harmonic 
Filter
PowerSensePA-FinalStagePADriver From VCOControlledStage
VcontrolBias 1Bias 2
To Microprocessor
Temperature
Sense SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
PreDriver 
						

							2-10THEORY OF OPERATION
5.2 Pre-Driver Stage
The next stage is an LDMOS device (Q3421) providing a gain of 13 dB. This device requires a 
positive gate bias and a quiescent current flow for proper operation. The voltage of the line 
PCIC_MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q3421 
via the resistive network R3410, R3415, and R3416. The bias voltage is tuned in the factory.
5.3 Driver Stage
The following stage is an enhancement-mode N-Channel MOSFET device (Q3431) providing a gain 
of 10dB. This device also requires a positive gate bias and a quiescent current flow for proper 
operation. The voltage of the line MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the 
gate of Q3431 via the resistive network R3404, R3406, and R3431-5. This bias voltage is also tuned 
in the factory. If the transistor is replaced, the bias voltage must be tuned using the Customer 
Programming Software (CPS). Care must be taken not to damage the device by exceeding the 
maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply 
voltage input, PASUPVLTG, via L3431 and L3432.
5.4 Final Stage
The final stage uses the bipolar device Q3441. The device’s collector current is also drawn from the 
radio’s DC supply voltage input. To maintain class C operation, the base is DC-grounded by a series 
inductor (L3441) and a bead (L3442).   A matching network consisting of C3446-52, C3467, L3444-5, 
and two striplines, transforms the impedance to approximately 50 ohms and feeds the directional 
coupler.
5.5 Directional Coupler
The directional coupler is a microstrip printed circuit, which couples a small amount of the forward 
and reflected power delivered by Q3441. The coupled signals are rectified by D3451-2 and 
combined by R3463-4. The resulting DC voltage is proportional to RF output power and feeds the 
RFIN port of the PCIC (U3501 pin 1). The PCIC controls the gain of stage U3401 as necessary to 
hold this voltage constant, thus ensuring the forward power out of the radio to be held to a constant 
value.
An abnormally high reflected power level, such as may be caused by a damaged antenna, also 
causes the DC voltage applied to the PCIC to increase, and this will cause a reduction in the gain of 
U3401, reducing transmitter output power to prevent damage to the final device due to an improper 
load. 
						

							VHF (136-174MHz) Transmitter Power Amplifier (PA) 45 W 2-11
5.6 Antenna Switch
The antenna switch consists of two PIN diodes, D3471 and D3472. In the receive mode, both diodes 
are off. Signals applied at the antenna jack J3401 are routed, via the harmonic filter, through 
network L3472, C3474 and C3475, to the receiver input. In the transmit mode, K9V1 turns on Q3471 
which enables current sink Q3472, set to 96 mA by R3473 and VR3471. This completes a DC path 
from PASUPVLTG, through L3473, D3471, L3477, L3472, D3472, L3471, R3474 and the current 
sink, to ground. Both diodes are forward biased into conduction. The transmitter RF from the 
directional coupler is routed via D3471 to the harmonic filter and antenna jack. D3472 also 
conducts, shunting RF power and preventing it from reaching the receiver port (RXIN). L3472 is 
selected to appear as a broadband lambda/4 wave transmission line, making the short circuit 
presented by D3472 appear as an open circuit at the junction of D3472 and the receiver path.
5.7 Harmonic Filter
Components L3491-L3494 and C3489-C3498 form a nine-pole Chebychev low-pass filter to 
attenuate harmonic energy of the transmitter to specifications level. R3490 is used to drain 
electrostatic charge that might otherwise build up on the antenna. The harmonic filter also prevents 
high level RF signals above the receiver passband from reaching the receiver circuits, improving 
spurious response rejection.
5.8 Power Control
The transmitter uses the Power Control IC (PCIC, U3501) to control the power output of the radio. A 
portion of the forward and reflected RF power from the transmitter is sampled by the directional 
coupler, rectified and summed, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is 
proportional to the sampled RF power. 
The ASFIC contains a digital to analog converter (DAC) which provides a reference voltage of the 
control loop to the PCIC via R3517. The reference voltage level is programmable through the SPI line 
of the PCIC. This reference voltage is proportional to the desired power setting of the transmitter, and 
is factory programmed at several points across the frequency range of the transmitter to offset 
frequency response variations of the transmitter’s power detector circuitry.
The PCIC provides a DC output voltage at pin 4 (INT) which is amplified and shifted in DC level by 
stages Q3501 and Q3502. The 0 to 4 volt DC range at pin 4 of U3501 is translated to a 0 to 8.5 volt 
DC range at the output of Q3501, and applied as VCONT to the power-adjust input pin of the first 
transmitter stage U3401. This adjusts the transmitter power output to the intended value. Variations 
in forward or reflected transmitter power cause the DC voltage at pin 1 to change, and the PCIC 
adjusts the control voltage above or below its nominal value to raise or lower output power.
Capacitors C3502-4, in conjunction with resistors and integrators within the PCIC, control the 
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into 
adjacent channels.
U3502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity 
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29) 
proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the 
transmitter output power will be reduced so as to reduce the transmitter temperature. 
						

							2-12THEORY OF OPERATION 
						

							Chapter 3
TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)
Bad SINAD
Bad 20dB Quieting
No Recovered AudioSTART
Audio at 
pin 8 of 
U3101 ?Check Controller
(in the case of no audio)
OR ELSE go to “B” Ye s
No
Spray or inject 44.85MHz 
into XTAL Filter FL3101
Audio heard ?BYe s
No
Check 2nd LO 
(44.395MHz) at C3135 
LO present ?BYe s
 Check voltages on 
U3101Biasing OK ?
No
No
A
Ye s
Check Q3102  bias 
for faults
Replace Q3102
Go to B
Ye s
No
Check circuitry 
around U3101.
Replace 
U3101 if defectCheck circuitry around Y3101 Re-
place Y3101 if defectVoltages
 OK? 
						

							3-2TROUBLESHOOTING CHARTS
1.1Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
IF Signal at 
C3035?
No
RF Signal at 
T3001?
RF Signal at 
C3012?
No
RF Signal at 
C3008?
No
RF Signal at 
C3474?
No or 
Check Harmonic Filter 
J3401 and
Antenna Switch 
D3471,D3472,L3472
Check filter between C3474 
& C3008. Check tuning 
voltage at R3019
Inject RF into J3401
Is tuning 
voltage OK?
No
Ye s
Check RF amp 
(Q3001) Stage
Check filter between 
C3012 & T3001
Ye s
Check T3001, T3002, 
D3031, R3030-R3034, 
L3032, C3034 and C3035
Ye s1st 
LO level OK? 
Locked?
Ye s
Check FGU
Ye s
Trace IF signal from 
C3035 to Q3101. 
Check for bad XTAL 
filter
No
Ye s
IF signal at Q3102 
collector?
Before replacing 
U3101, check 
U3101 voltages
Ye s
Check for 5VDC
Is 9V3 present?
Check Supply Voltage 
circuitry.  Check Q0681, 
U3211 and U0641
No
No
No
Check U3501
Check varactor filter
NoYe s
Ye s
Ye s
A
A
B
weak RF 
						

							Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) 3-3
2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)
Current 
increase 
when keyed?
NO YES
START
Check if Pressure Pad closes S3440
Check Components between 
Q3441 and RF Output, 
Antenna Switch 
D3471,D3472,Q3472 >500mA & 4A
1V
Short TP3403 to 
Ground
NO
YES
Voltage at 
TP3402 
rises?Check PA StagesNO
YES
PCIC U3501 
Pin 14 9.3V 
DC?Check 9.3 V Regulator 
U0641
NO
YESPCIC U3501 
Pin 16 >4V 
DCReplace PCIC U3501
NO
YESTP3404  
9.1V DC
If U3201 Pin 2 is high,  
replace PCIC 
U3501,otherwise 
check controller and 
FGU
YES
NOTP3403 
>0.5V DC?Replace PCIC U3501
Check Forward Power 
Sense Circuit (D3451)
Check Forward Power 
Sense Circuit (D3451)
NO
YESPCIC U3501 
Pin 5 > 1V 
DC?
Check Power Setting, 
Tuning & Components 
between PCIC Pin 5 
and ASFIC (U0221) 
Pin 4 before replacing 
ASFIC
No or too low Power when keyed 
						

							3-4TROUBLESHOOTING CHARTS
2.1Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3)
Check PA Stages
No or too low Power when keyed
Measure DC Voltage at Pin 2 & 3 of U3401>6 YESDC Voltage 
at U3501 
Pin 23 =0?
2-6DC Voltage 
at U3402-1 
Pin 1?
YES Pin 2 Voltage 
0.62 * 
Voltage at 
Pin 1?
If U3201 Pin 2 is high,  
replace PCIC
NOReplace U3401
YES NODC
Voltage at 
U3402-1 Pin 
3 = 8.8V?
Check S3440, 
R3442 and R3443
YES Pin 3 Voltage 
0.51 * 
Voltage at 
Pin 1?
NOReplace U3401
6V
Check Components 
between U3402-2 Pin7 
and Q3421. Check 
Resistive Network at 
Pins 5 & 6 before repla-
cing Q3421
YES DC Voltage at 
U3402-2 Pin 
5