Motorola Cdm And Pro Series Detailed 68p81091c63 O Manual

							Theory of Operation2-27
2.7.1 Front-End Band-Pass Filters and Pre-Amplifier
The received signal from the radio’s antenna connector is first routed through the harmonic filter and 
antenna switch, which are par t of the RF power amplifier circuits, before being applied to the receiver 
pre-selector filter (C3001, C3002, D3001 and associated components). The 2-pole pre-selector filter 
tuned by the dual varactor diode D3001 pre-selects the incoming signal (RXIN) from the antenna 
switch to reduce spurious effects to following stages. The tuning voltage (FECTRL_1) ranging from 2 
volts to 8 volts is controlled by pin 20 of PCIC (U3501) in the Transmitter section. A dual hot carrier 
diode (D3003) limits any inband signal to 0 dBm to prevent damage to the pre-amplifier.
The RF pre-amplifier is a surface mount device (SMD) Q3001 with collector-base feedback to 
stabilize gain, impedance, and intermodulation. Transistor Q3002 compares the voltage drop across 
resistor R3002 with a fixed base voltage from divider R3011, R3000 and R3012, and adjusts the 
base current of Q3001 as necessary to maintain its collector current constant at approximately 15-20 
mA. Operating voltage is from the regulated 9.3V supply (9V3). During transmit, 9.1 volts (K9V1) 
turns off both transistors Q3002 and Q3001. This protects the RF pre-amplifier from excessive 
dissipation during transmit mode. A following 3dB pad (R3006 – R3008 and R3016 – R3018) 
stabilizes the output impedance and intermodulation performance.
A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal. 
The dual varactor diode D3004 is controlled by the same signal FECTRL_1, which controls the pre-
selector filter.
2.7.2 First Mixer and 1st Intermediate Frequency (IF)
The signal coming from the front-end is converted to the 1st IF frequency of 44.85 MHz using a cross 
over quad diode mixer (D3031). Its por ts are matched for incoming RF signal conversion to the 44.85 
MHz IF using high side injection. The high-side injection signal (RXINJ) from the frequency 
synthesizer circuit has a level of approximately +13 dBm and is injected via matching transformer 
T3002.
The IF output signal (IF) from transformer T3001 pin 2 is fed to the first 2- pole crystal filter FL3101. 
The filter output in turn is matched to IF amplifier Q3101 which is actively biased by a collector base 
feedback (R3101, R3106) to a current drain of approximately 5 mA drawn from the 5 volt supply. Its 
output impedance is matched to the second 2-pole crystal filter FL3102. The signal is fur ther 
amplified by a preamplifier (Q3102) before going into pin 1 of IFIC (U3101).
A dual hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at 
RF input levels above -27 dBm.
2.7.3 2nd Intermediate Frequency (IF) and Receiver Back-End
The 44.85 MHz 1st IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the 
IF IC, the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO) to 
produce the 2nd IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The 
2nd IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters FL3112, FL3114 
for 20/25 kHz channel spacing or FL3111, FL3113/F3115 for 12.5 kHz channel spacing. These pairs 
are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter 
input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide 
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% 
deviation) from U3101 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (par t of the 
Controller circuits). 
A received signal strength indicator (RSSI) signal is available at U3101, pin 5, having a dynamic 
range of 70 dB. The RSSI signal is interpreted by the µP (U0101, pin 63) and in addition is available 
at accessory connector J0501-15. 
						

							2-28Theory of Operation
2.8 Transmitter Power Amplifier (PA) 45 W
The radio’s 45 W PA is a four-stage amplifier used to amplify the output from the VCOBIC to the radio 
transmit level. The line-up consists of three stages which utilize LDMOS and VMOS technology, 
followed by a final stage using a bipolar device. The gain of the first stage (U3401) is adjustable, 
controlled by pin 4 of PCIC (U3501) via Q3501 and Q3502 (VCONT). It is followed by an LDMOS 
pre-driver stage (Q3421), a VMOS driver stage (Q3431) and a bipolar final stage (Q3441).
Figure 2-12.   VHF Transmitter Block Diagram 
Devices U3401 and Q3421 are surface mounted. The remaining devices are directly attached to the 
heat sink.
2.8.1 Power Controlled Stage 
The first stage (U3401) is a 20 dB gain integrated circuit containing two LDMOS FET amplifier 
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U3401 is 
controlled by a dc voltage applied to pin 1 from the power control circuit (U3501 pin 4, with transistors 
Q3501 and Q3502 providing current gain and level-shifting). The control voltage simultaneously 
varies the bias of two FET stages within U3401. This biasing point determines the overall gain of 
U3401 and therefore its output drive level to Q3421, which in turn controls the output power of the 
PA .
In receive mode the voltage control line is at ground level and turns off Q3501-2, which in turn 
switches off the biasing voltage to U3401.
2.8.2 Pre-Driver Stage
The next stage is an LDMOS device (Q3421) providing a gain of +13 dB. This device requires a 
positive gate bias and a quiescent current flow for proper operation. The voltage of the line 
PCIC_MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q3421 via 
the resistive network R3410, R3415, and R3416. The bias voltage is factory tuned. PCIC
Pin Diode 
Antenna 
Switch
RF JackAntenna
Harmonic 
Filter
Pow erSensePA - F i n a lStagePADriver Fr o m V COControlledStage
VcontrolBias 1Bias 2
To Microprocessor
Temperature
Sense SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor 
						

							Theory of Operation2-29
2.8.3 Driver Stage
The following stage is an enhancement-mode N-Channel MOSFET device (Q3431) providing a gain 
of 10 dB. This device also requires a positive gate bias and a quiescent current flow for proper 
operation. The voltage of the line MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the 
gate of Q3431 via the resistive network R3404, R3406, and R3431-5. This bias voltage is also tuned 
in the factory. If the transistor is replaced, the bias voltage must be tuned using the Customer 
Programming Software (CPS). Care must be taken not to damage the device by exceeding the 
maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s dc supply 
voltage input, PASUPVLTG, via L3431 and L3432.
2.8.4 Final Stage
The final stage uses bipolar device Q3441. The device’s collector current is also drawn from the 
radio’s dc supply voltage input. To maintain class C operation, the base is dc-grounded by a series 
inductor (L3441) and a bead (L3442).   A matching network consisting of C3446-52, C3467, L3444-
5, and two striplines, transforms the impedance to approximately 50 ohms and feeds the directional 
coupler.
2.8.5 Directional Coupler 
The directional coupler is a microstrip printed circuit, which couples a small amount of the forward 
and reflected power delivered by Q3441. The coupled signals are rectified by D3451-2 and 
combined by R3463-4. The resulting dc voltage is propor tional to RF output power and feeds the 
RFIN por t of the PCIC (U3501, pin 1). The PCIC controls the gain of stage U3401 as necessary to 
hold this voltage constant, thus ensuring the forward power out of the radio to be held to a constant 
value.
An abnormally high reflected power level, such as may be caused by a damaged antenna, also 
causes the dc voltage applied to the PCIC to increase, and this will cause a reduction in the gain of 
U3401, reducing transmitter output power to prevent damage to the final device due to an improper 
load.
2.8.6 Antenna Switch
The antenna switch consists of two PIN diodes, D3471 and D3472. In the receive mode, both diodes 
are off. Signals applied at the antenna jack J3401 are routed, via the harmonic filter, through network 
L3472, C3474 and C3475, to the receiver input. In the transmit mode, the keyed 9 volts turns on 
Q3471 which enables current sink Q3472, set to 96 mA by R3473 and VR3471. This completes a dc 
path from PASUPVLTG, through L3473, D3471, L3477, L3472, D3472, L3471, R3474 and the 
current sink, to ground. Both diodes are forward biased into conduction. The transmitter RF from the 
directional coupler is routed via D3471 to the harmonic filter and antenna jack. D3472 also conducts, 
shunting RF power and preventing it from reaching the receiver por t (RXIN). L3472 is selected to 
appear as a broadband guar ter-wave transmission line, making the short circuit presented by D3472 
appear as an open circuit at the junction of D3472 and the receiver path.
2.8.7 Harmonic Filter 
Components L3491-L3494 and C3490-C3498 form a nine-pole Chebychev low-pass filter to 
attenuate harmonic energy of the transmitter. R3490 is used to drain electrostatic charge that might 
otherwise build up on the antenna. The harmonic filter also prevents high level RF signals above the 
receiver passband from reaching the receiver circuits, improving spurious response rejection. 
						

							2-30Theory of Operation
2.8.8 Power Control 
The transmitter uses the power control IC (PCIC, U3501) to control the power output of the radio. A 
portion of the forward and reflected RF power from the transmitter is sampled by the directional 
coupler, rectified and summed, to provide a dc voltage to the RFIN por t of the PCIC (pin 1) which is 
propor tional to the sampled RF power. 
The ASFIC contains a digital to analog converter (DAC) which provides a reference voltage of the 
control loop to the PCIC via R3517. The reference voltage level is programmable through the SPI 
line of the PCIC. This reference voltage is propor tional to the desired power setting of the transmitter, 
and is factory programmed at several points across the frequency range of the transmitter to offset 
frequency response variations of the transmitter’s power detector circuit.
The PCIC provides a dc output voltage at pin 4 (INT) which is amplified and shifted in dc level by 
stages Q3501 and Q3502. The 0 to 4 Vdc range at U1503, pin 4 is translated to a 0 to 8.5 Vdc range 
at the output of Q3501, and applied as VCONT to the power-adjust input pin of the first transmitter 
stage U3401. This adjusts the transmitter power output to the intended value. Variations in forward or 
reflected transmitter power cause the dc voltage at pin 1 to change, and the PCIC adjusts the control 
voltage above or below its nominal value to raise or lower output power.
Capacitors C3502-4, in conjunction with resistors and integrators within the PCIC, control the 
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into 
adjacent channels.
U3502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity 
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29) 
propor tional to temperature. If the dc voltage produced exceeds the set threshold in the PCIC, the 
transmitter output power is reduced so as to reduce the transmitter temperature.
2.9 Frequency Synthesis
The frequency synthesizer subsystem consists of the reference oscillator (Y3261 or Y3262), the Low 
Voltage Fractional-N synthesizer (LVFRAC-N, U3201), and the voltage-controlled oscillators and 
buffer amplifiers (U3301, Q3301-2 and associated circuits).
2.9.1 Reference Oscillator
The reference oscillator (Y3262) contains a temperature compensated crystal oscillator with a 
frequency of 16.8 MHz. An analog-to-digital (A/D) conver ter internal to U3201 (LVFRAC-N) and 
controlled by the µP via serial interface (SRL) sets the voltage at the warp output of U3201 (pin 25) to 
set the frequency of the oscillator. The output of the oscillator (U3262 pin 3) is applied to pin 23 
(XTAL1) of U3201 via R3263 and C3235.
In applications were less frequency stability is required, the oscillator inside U3201 is used along 
with an external crystal Y3261, varactor diode D3261, C3261, C3262 and R3262. In this case, 
Y3262, R3263, C3235 and C3251 are not used. When Y3262 is used, Y3261, D3261, C3261, 
C3262 and R3262 are not used, and C3263 is increased to 0.1 uF.
2.9.2 Fractional-N Synthesizer 
The LVFRAC-N synthesizer IC (U3201) consists of a pre-scaler, a programmable loop divider, control 
divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital 
modulation, a balance attenuator to balance the high frequency analog modulation and low 
frequency digital modulation, a 13 volt positive voltage multiplier, a serial interface for control, and 
finally a super filter for the regulated 5 volts. 
						

							Theory of Operation2-31
Figure 2-13.   VHF Synthesizer Block Diagram
A voltage of 5V applied to the super filter input (U3201 pin 30) supplies an output voltage of 4.5 Vdc 
(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R3363) and the synthesizer 
charge pump resistor network (R3251, R3252). The synthesizer supply voltage is provided by the 5V 
regulator U3211.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U3201-47), a voltage of 13 Vdc is being generated by the positive voltage multiplier circuits 
(D3201, C3202, C3203). This voltage multiplier is basically a diode capacitor network driven by two 
signals (1.05MHz) 180 degrees out of phase signals (U3201-14 and -15).
Output LOCK (U3201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U3201 provides the 16.8 MHz reference frequency at 
pin 19.
The serial interface (SRL) is connected to the µP via the data line DATA (U3201-7), clock line CLK 
(U3201-8), and chip enable line CSX (U3201-9).
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U3211 PIN 1)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
        1540FILTERED 5VSTEERING LOCK (U0101 PIN 56)
PRESCALER INFREF (U0221 PIN 34)
39 BIAS2
41
 48 5, 20, 34, 36
+5V (U3211 PIN 1)
AUX1 VDD, DC5VMODOUT
U3201 
LOW VOLTAGEFRACTIONAL-N
SYNTHESIZER
AUX2
TRBTX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
2-POLE
LOOP
FILTER
1 
						

							2-32Theory of Operation
2.9.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U3301), the TX 
and RX tank circuits, the external RX buffer stages, and the modulation circuits.
Figure 2-14.   VHF VCO Block Diagram
The VCOBIC together with the Fractional-N synthesizer (U3201) generates the required frequencies 
in both the transmit and receive modes. The TRB line (U3301, pin 19) determines which tank circuits 
and internal buffers are to be enabled. A high level on TRB enables the TX tank and TX output (pin 
10), and a low enables the RX tank and RX output (pin 8). A sample of the signal from the enabled 
RF output is routed from U3301, pin 12 (PRESC_OUT), via a low pass filter, to U3201, pin 32 
(PREIN).
A steering line voltage (VCTRL) between 2.5 volts and 11 volts at varactor diode D3361 tune the full 
TX frequency range (TXINJ) from 136 MHz to 174 MHz, and varactor diode D3341 tunes the full RX 
frequency range (RXINJ) from 181 MHz to 219 MHz. The RX tank circuit uses a Har tley 
configuration for wider bandwidth. For the RX tank circuit, an external transistor Q3304 is used for 
better side-band noise.
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U3211 Pin1)
VCC Buffers
TX RF Injection U3201 Pin 32 AUX3 (U3201 Pin2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U3301
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15 Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6RX
TX
(U3201 Pin28)Rx-SW
Tx-SW
Vcc-Logic
(U3211 Pin1) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION
Q3304
Q3301 
						

							Theory of Operation2-33
The external RX buffers (Q3301 and Q3302) are enabled by a high at U3301, pin 7 (RX_SWITCH) 
via transistor switch Q3303. In the TX mode, the modulation signal (VCOMOD) from the LVFRAC-N 
synthesizer IC (U3201 pin 41) is applied to varactor diode D3362, which modulates the TX VCO 
frequency via capacitor C3362. Varactor D3362 is biased for linearity from the VSF.
2.9.4 Synthesizer Operation
The complete synthesizer subsystem consists of the low voltage FRAC-N (LVFRACN), reference 
oscillator (a crystal oscillator with temperature compensation), charge pump circuit, loop filter circuit 
and a dc supply. The output signal PRESC from the VCOBIC (U3301 pin 12) is fed to U3201 pin 32 
(PREIN) via a low pass filter (C3318, L3318 and C3226) which attenuates harmonics and provides 
the correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U3201) is a dual modulus type with selectable divider ratios. The 
divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs via the 
SRL. The output of the pre-scaler is applied to the loop divider. The output of the loop divider is 
connected to the phase detector, which compares the loop divider´s output signal with the reference 
signal. The reference signal is generated by dividing down the signal of reference oscillator Y3261 or 
Y3262.
The output signal of the phase detector is a pulsed dc signal which is routed to the charge pump. The 
charge pump outputs a current at U3201 pin 43 (IOUT). The loop filter (which consists of R3221-
R3223 and C3221-C3224) transforms this current into a voltage that is applied to the varactor diodes 
(D3361 for transmit, D3341 for receive) to alter the output frequency of the appropriate VCO. The 
current can be set to a value fixed within the LVFRAC-N IC, or to a value determined by the currents 
flowing into BIAS 1 (U3201-40) or BIAS 2 (U3201-39). The currents are set by the value of R3251 
and R3252 respectively. The selection of the three different bias sources is done by software 
programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer, the 
magnitude of the loop current is increased by enabling the IADAPT pin (U3201-45) for a cer tain 
software programmable time (adapt mode). The adapt mode timer is star ted by a low to high 
transient of the CSX line. When the synthesizer is within the lock range, the current is determined 
only by the resistors connected to BIAS 1 and BIAS 2, or by the internal current source. A settled 
synthesizer loop is indicated by a high level signal at U3201-4 (LOCK).
The LOCK signal is routed to one of the µP´s ADC inputs (U0101-56). From the measured voltage, 
the µP determines whether LOCK is active.
To modulate the PLL, the two spot modulation method is utilized. Via U3201, pin 10 (MODIN), the 
audio signal is applied to both the A/D conver ter (low frequency path) as well as the balance 
attenuator (high frequency path). The A/D conver ter changes the low frequency analog modulating 
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The 
balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency modulating 
signals. The output of the balance attenuator is present at the MODOUT port (U3201-41) and 
connected to the VCO modulation diode D3362 via R3364. 
						

							2-34Theory of Operation
2.10 Control Head (PRO3100, CDM750)
ThE Control Head Contains the internal speaker, the on/off/volume knob, the microphone connector, 
several buttons to operate the radio and several indicator Light Emitting Diodes (LED) to inform the 
user about the radio status. To control the LED’s and to communicate with the host radio the control 
head uses the Motorola 68HC11E9 µP.
2.10.1 Power Supplies
The power supply to the control head is taken from the host radio’s FLT A+ voltage via connector 
J0801, pin 3 and the regulated +5V via connector J0801 pin 7. The voltage FLT A+ is at battery level 
and is used for the LED’s, the back light and to power up the radio via on / off / volume knob. The 
stabilized +5 volt is used for µP and the keypad buttons. The voltage USW 5V derived from the FLT 
A+ voltage and stabilized by the series combination of R0822, VR0822 is used to buffer the internal 
RAM of the µP (U0831). C0822 allows the battery voltage to be disconnected for a couple of 
seconds without losing RAM parameters. Dual diode D0822 prevents radio circuits from discharging 
this capacitor. When the supply voltage is applied to the radio, C0822 is charged via R0822 and 
D0822. To avoid the µP entering the wrong mode if the radio is switched on while the voltage across 
C0822 is still too low, the regulated 5 volt supply charges C0822 via diode D0822.
2.10.2 Power On/Off
The on/off/Volume knob, when pressed, switches the radio’s voltage regulators on by connecting line 
ON OFF CONTROL to line UNSW 5V via D0821. Additionally, 5 volts at the base of digital transistor 
Q0822 informs the control head’s µP about the pressed knob. The µP asser ts pin 62 and line CH 
REQUEST low to hold the line ON OFF CONTROL at 5 volts via Q0823 and D0821. The high line 
ON OFF CONTROL also informs the host radio that the control head’s µP wants to send data via the 
SBEP bus. When the radio returns a data request message, the µP informs the radio about the 
pressed knob. If the radio is switched off, the radio’s µP switches it on and vice versa. If the on/off/
volume knob is pressed while the radio is on, the software detects a low state on line ON OFF 
SENSE, the radio is alerted via line ON OFF CONTROL and sends a data request message. The 
control head µP informs the radio about the pressed knob and the radio’s µP switches the radio off.
2.10.3 Microprocessor Circuit
The control head uses the Motorola 68HC11E9 microprocessor (µP) (U0831) to control the LED’s 
and to communicate with the host radio. RAM and ROM are contained within the µP.
The µP generates it’s clock using the oscillator inside the µP along with a 8 MHz ceramic resonator 
(U0833) and R0920.
The µP’s RAM is always powered to maintain parameters such as the last operating mode. This is 
achieved by maintaining 5V at uP, pin 25. Under normal conditions, when the radio is off, USW 5V is 
formed by FLT A+ running to D0822. Capacitor C0822 allows the battery voltage to be disconnected 
for a couple of seconds without losing RAM parameters. Diode D0822 prevents radio circuits from 
discharging this capacitor.
There are eight analog-to-digital converter por ts (A/D) on the uP. They are labeled within the device 
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5 volts of the input line and 
conver t that level to a number ranging from 0 to 255 which can be read by the software to take 
appropriate action.
The Pin VRH Pin is the high reference voltage for the A/D por ts on the uP. If this voltage is lower than 
+5V the A/D reading is incorrect. The VRL signal is the low reference for the A/D por ts. This line is 
normally tied to ground. If this line is not connected to ground, the A/D readings could be incorrect. 
						

							Theory of Operation2-35
The µP determines the used keypad type and the control head ID by reading the levels at por ts PC0 
– PC7. Connections JU0852/3/4 are provided by the individual keypads.
The MODB / MODA input of the µP must be at a logic 1 to start executing correctly. The XIRQ and 
the IRQ pins should also be at a logic 1.
Voltage sense device U0832 provides a reset output that goes to 0 volts if the regulated 5 volts goes 
below 4.5 volts. This is used to reset the controller to prevent improper operation.
2.10.4 SBEP Serial Interface
The host radio (master) communicates to the control head µP (slave) through its SBEP bus. This bus 
uses only line BUS+ for data transfer. The line is bi-directional meaning that either the radio or the 
control head µP can drive the line. The µP sends serial data via pin 50 and D0831 and it reads serial 
data via pin 47. Whenever the µP detects activity on the BUS+ line, it star ts communication.
When the host radio needs to communicate to the control head uP, it sends data via line BUS+. Any 
transition on this line generates an interrupt and the µP star ts communication. The host radio may 
send data like LED and back light status or it may request the control head ID or the keypad ID.
When the control head µP wants to communicate to the host radio, the uP brings the request line CH 
REQUEST to a logic 0 via µP pin 62. This switches on Q0823, which pulls line ON OFF CONTROL 
high through diode D0821. A low to high transition on this line informs the radio, that the control head 
requires service. The host radio then sends a data request message via BUS+ and the control head 
uP replies with the data it wanted to send. This data can be information like which key has been 
pressed or that the volume knob has been rotated.
The control head uP monitors all messages sent via BUS+, but ignores any data communication 
between the host radio and CPS or universal tuner.
2.10.5 Keypad Keys
The control head keypad is a 6-key design. All keys are configured as two analog lines read by µP 
pins 13 and 15. The voltage on the analog lines varies between 0 volts and +5 volts depending on 
which key has been pressed. If no key is pressed, the voltage at both lines is 5 volts. The key 
configuration can be thought of as a matrix, where the two lines represent one row and one column. 
Each line is connected to a resistive divider powered by +5 volts. If a button is pressed, it will connect 
one specific resistor of each divider line to ground level and thereby reduce the voltages on the 
analog lines The voltages of the lines are A/D converted inside the µP (por ts PE 0 - 1) and specify 
the pressed button. To determine which key is pressed, the voltage of both lines must be considered.
An additional pair of analog lines and A/D µP ports (PE 3 – 2) are available to support a keypad 
microphone, connected to the microphone connector J0811. Any microphone key press is processed 
the same way as a key press on a control head.
2.10.6 Status LED and Back Light Circuit
All indicator LED’s (red, yellow, green) are driven by current sources. To change the LED status the 
host radio sends a data message via SBEP bus to the control head µP. The control head µP 
determines the LED status from the received message and switches the LED’s on or off via por t PB 
7 – 0 and port PA4. The LED status is stored in the µP’s memory. The LED current is determined by 
the resistor at the emitter of the respective current source transistor.
The back light for the keypad is controlled by the host radio the same way as the indicator LED’s 
using uP port PA 5. The µP can switch the back light on and off under software control. The keypad 
back light current is drawn from the FLT A+ source and controlled by 2 current sources. The LED 
current is determined by the resistor at the emitter of the respective current source transistor. 
						

							2-36Theory of Operation
2.10.7 Microphone Connector Signals
Signals BUS+, PTT IRDEC, HOOK, MIC, HANDSET AUDIO, FLT A+, +5V, and two A/D converter 
inputs are available at the microphone connector J0811. Signal BUS+ (J0811-7) connects to the 
SBEP bus for communication with the CPS or the Universal Tuner. Line MIC (J0811-5) feeds the 
audio from the microphone to the radio’s controller via connector J0801-4. The Line HANDSET 
AUDIO (J0811-8) feeds the receiver audio from the controller (J0801-6) to a connected handset. FLT 
A+, which is at supply voltage level, and +5V are used to supply any connected accessory like a 
microphone or a handset.
The two A/D converter inputs (J0811-9/10) are used for a microphone with keypad. A pressed key 
changes the dc voltage on both lines. The voltages depend on which key is pressed. The µP 
determines from the voltage on these lines which key is pressed and sends the information to the 
host radio.
Line PTT IRDEC (J0811-6) is used to key µP the radio’s transmitter. While the PTT button on a 
connected microphone is released, line PTT IRDEC is pulled to +5 volts level by R0843. Transistor 
Q0843 is switched on and causes a low at µP port PA2. When the PTT button is pressed, signal PTT 
IRDEC is pulled to ground level. This switches off Q0843 and the resulting high level at µP por t PA2 
informs the µP about the pressed PTT button. The µP informs the host radio about any status 
change on the PTT IRDEC line via SBEP bus.
When line PTT IRDEC is connected to FLT A+ level, transistor Q0821 is switched on through diode 
VR0821 and thereby pulls the level on line ON OFF CONTROL to FLT A+ level. This switches on the 
radio and puts the radio’s µP in bootstrap mode. Bootstrap mode loads the firmware into the radio’s 
flash memory.
The HOOK input (J0811-3) informs the µP when the microphone´s hang-up switch is engaged. 
Depending on the CPS programming, the µP may take actions like turning the audio PA on or off. 
While the hang µp switch is open, the line HOOK is pulled to +5 volts level by R0841. Transistor 
Q0841 is switched on and causes a low at µp por t PA1. When the HOOK switch is closed, the HOOK 
signal is pulled to ground level. This switches off R0841and the resulting high level at µp port PA1 
informs the µp about the closed hang µp switch. The µp informs the host radio about any status 
change on the HOOK line via SBEP bus.
2.10.8 Speaker
The control head contains a speaker for the receiver audio. The receiver audio signal from the 
differential audio output of the audio amplifier located on the radio’s controller, is fed via connector 
J0801-10, 11 to the speaker connector P0801, pins 1 and 2. The speaker is connected to the 
speaker connector P0801. The control head speaker can be disconnected only if an external 
speaker, connected on the accessory connector, is used.
2.10.9 Electrostatic Transient Protection
Electrostatic transient protection is provided for the sensitive components in the control head by 
diodes VR0811 VR00812 VR0816 - VR0817. The diodes limit any transient voltages. The associated 
capacitors provide radio frequency interference (RFI) protection.