Motorola Cdm And Pro Series Detailed 68p81091c63 O Manual

							Theory of Operation2-17
2.3.6.3  Voice Storage Option
The Voice Storage (VS) option can be used to store audio signals coming from the receiver or from 
the microphone. Any stored audio signal can be played back over the radio’s speaker or sent out via 
the radio’s transmitter.
The Voice Storage option can by placed on the controller section or on an additional option board 
which resides on option board connector J0551. Voice Storage IC U0301 provides all required 
functionality and is powered from 3.3 volts regulator U0351 which is powered from the regulated 5 
volts. Dual shottky diode D0301 reduces the supply voltage for U0301 to 3 volts. The µP controls 
U0301 via SPI bus lines CLK (U0301-8), DATA (U0301-10) and MISO (U0301-11). To transfer data, 
the µP first selects the U0301 via address decoder U0141, line VS CS and U0301 pin 9. Then the µP 
sends data through line DATA and receives data through line MISO. Pin 2 (RAC) of U0301 indicates 
the end of a message row by a low state for 12.5 ms and connects to µP pin 52. A low at pin 5 (INT), 
which is connected to µP pin 55 indicates that the Voice Storage IC requires service from the µP.
Audio, either from the radio’s receiver or from one of the microphone inputs, emerges the ASFIC 
CMP (U0221) at pin 43, is buffered by op-amp U0341-1, then enters the voice storage IC U0301 at 
pin 25. During playback, the stored audio emerges U0301 at pin 20. To transmit the audio signal, it is 
fed through resistive divider R0344 / R0345 and line VS MIC to input selector IC U0251. When this 
path is selected by the µP via ASFIC CMP por t GCB 4, the audio signal enters the ASFIC CMP at 
pin 48 and is processed like normal transmit audio. To play the stored audio over the radio’s speaker, 
the audio from U0301 pin 20 is buffered by op-amp U0341-2 and fed via switch U0342 and line FLAT 
RX SND to ASFIC CMP pin 10 (UIO). In this case, this ASFIC CMP pin is programmed as input and 
feeds the audio signal through the normal receiver audio path to the speaker or handset. Switch 
U0342 is controlled by the µP via ASFIC CMP por t GCB 4 and feeds the stored audio only to the 
ASFIC CMP por t UIO when it is programmed as input.
2.4 UHF (403-470 MHz) Receiver Front-End
The receiver is able to cover the UHF range from 403 to 470 MHz. It consists of four major blocks: 
front-end bandpass filters and preamplifier, 
•First mixer
• 1st IF
• 2nd IF 
• Receiver back-end
Two varactor tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode 
mixer converts the signal to the 1st IF of 44.85 MHz. Low side first injection is used. 
						

							2-18Theory of Operation
Figure 2-7.   UHF Receiver Block Diagram
The 2-pole 44.85 MHz crystal filters in the 1st IF section and two pairs of 455 kHz ceramic filters in 
the 2nd IF section provide the required adjacent channel selectivity. The correct pair of ceramic filters 
for 12.5 or 25 kHz channel spacing is selected via control line BWSELECT. The 2nd IF at 455 kHz is 
mixed, amplified, and demodulated in the IF IC. The processing of the demodulated audio signal is 
performed by an audio processing IC located in the controller section.
Demodulator
1. Crystal 
Filter Mixer Va r a c t o r  
Tuned Filter RF Amp Va r a c t o r  
Tuned Filter Pin Diode 
Antenna 
Switch
RF Jack
Control Voltage
from PCICFirst LO
from FGU
Recovered Audio
RSSI
Second LO
2. Crystal 
Filter
455kHz Filter
(25kHz)455kHz Filter
(25kHz)
455kHz Filter
(12.5kHz)455kHz Filter
(12.5kHz)SwitchSwitchSwitchSwitch
Limiter
1. IF Amp
2. IF Amp
Filter Bank Selection
from Synthesizer IC
   Harmonic 
   Filter
BWSELECT 
						

							Theory of Operation2-19
2.4.1 Front-End Band-Pass Filters and Pre-Amplifier
The received signal from the radio’s antenna connector is first routed through the harmonic filter and 
antenna switch, which are par t of the RF power amplifier circuits, before being applied to the receiver 
pre-selector filter (C4001, C4002, D4001 and associated components). The 2-pole pre-selector filter 
tuned by the varactor diodes D4001 and D4002 pre-selects the incoming signal (RXIN) from the 
antenna switch to reduce spurious effects to following stages. The tuning voltage (FECTRL_1) 
ranging from 2 volts to 8 volts is controlled by pin 20 of PCIC (U4501) in the Transmitter section. A 
dual hot carrier diode (D4003) limits any inband signal to 0 dBm to prevent damage to the pre-
amplifier.
The RF pre-amplifier is an SMD device (Q4003) with collector base feedback to stabilize gain, 
impedance, and intermodulation. The collector current of approximately 11-16 mA is drawn from the 
9.3 volt supply via L4003 and R4002. A 3dB pad (R4006,R4007,R4011 and R4008 - R4010) 
stabilizes the output impedance and intermodulation performance. 
A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal. 
The varactor diodes D4004 and D4005 are controlled by the same signal FECTRL_1, which controls 
the pre-selector filter. A following 1 dB pad (R4013 - R4015) stabilizes the output impedance and 
intermodulation performance.
2.4.2 First Mixer and 1st Intermediate Frequency (IF) 
The signal coming from the front-end is converted to the first IF (44.85 MHz) using a cross over quad 
diode mixer (D4051). Its ports are matched for incoming RF signal conversion to the 44.85 MHz IF 
using low side injection via matching transformers T4051 and T4052. The injection signal (RXINJ) 
coming from the RX VCO buffer (Q4332) is filtered by the lowpass filter consisting of (L4053, L4054, 
C4053 - C4055) followed by a matching transformer T4052 and has a level of approximately 15dBm.
The mixer IF output signal (IF) from transformer T4501pin 2 is fed to the first two pole crystal filter 
FL3101. The filter output in turn is matched to the following IF amplifier.
The IF amplifier Q3101 is actively biased by a collector base feedback (R3101, R3106) to a current 
drain of approximately 5 mA drawn from the 5 volt supply. Its output impedance is matched to the 
second two pole crystal filter FL3102. The signal is fur ther amplified by a preamplifier (Q3102) before 
going into pin 1 of IFIC (U3101).
A dual hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at 
RF input levels above -27 dBm.
2.4.3 2nd Intermediate Frequency (IF) and Receiver Back-End
The 44.85 MHz 1st IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the 
IF IC the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO) to 
produce the low IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The 
2nd IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters (FL3112, FL3114) 
for 20/25 kHz channel spacing or FL3111 and FL3113/F3115 for 12.5 kHz channel spacing. These 
pairs are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the 
limiter input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide 
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% 
deviation) from U3103 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (par t of the 
Controller circuits). 
A received signal strength indicator (RSSI) signal is available at U3101 pin 5, having a dynamic 
range of 70 dB. The RSSI signal is interpreted by the µP (U0101 pin 63) and is available at 
accessory connector J0501-15. 
						

							2-20Theory of Operation
2.5 Transmitter Power Amplifier (PA) 40 W
The radio’s 40W power amplifier (PA) is a four stage amplifier used to amplify the output from the 
VCOBIC to the radio transmit level. It consists of the following four stages in the line-up. The first 
stage is a LDMOS predriver (U4401) that is controlled by pin 4 of PCIC (U4501) via Q4473 
(CNTLVLTG). It is followed by another LDMOS stage (Q4421), an LDMOS stage (Q4431), and a 
bipolar final stage (Q4441).
Figure 2-8.   UHF Transmitter Block Diagram 
Device Q4401 is surface mounted. Q4421, Q4431 and Q4441 are directly attached to the heat sink.
2.5.1 Power Controlled Stage 
The first stage (U4401) amplifies the RF signal from the VCO (TXINJ) and controls the output power 
of the PA. The output power of the transistor U4401 is controlled by a voltage control line feed from 
the PCIC pin4(U4501). The control voltage simultaneously varies the bias of two FET stages within 
U4401. This biasing point determines the overall gain of U4401 and therefore its output drive level to 
Q4421, which in turn controls the output power of the PA. 
In receive mode the voltage control line is at ground level and turns off Q4473 which in turn switches 
off the biasing voltage to U4401.
2.5.2 Pre-Driver Stage
The next stage is a 13dB gain LDMOS device (Q4421) which requires a positive gate bias and a 
quiescent current flow for proper operation. The voltage of the line PCIC_MOSBIAS_1 is set in 
transmit mode by PCIC pin 24 and fed to the gate of Q4421 via the resistive network R4407, R4408, 
R4416 and R4415. The bias voltage is tuned in the factory.PCIC
Pin Diode 
Antenna 
Switch
RF JackAntenna
Harmonic 
Filter
Pow erSensePA - F i n a lStagePADriver Fr o m V COControlledStage
VcontrolBias 1Bias 2
To Microprocessor
Temperature
Sense SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor 
						

							Theory of Operation2-21
2.5.3 Driver Stage
The following stage is an enhancement-mode N-Channel MOSFET device (Q4431) providing a gain 
of 10dB. This device also requires a positive gate bias and a quiescent current flow for proper 
operation. The voltage of the line Bias_2_UHF_PA_1 is set in transmit mode by the ASFIC and fed to 
the gate of Q4431 via the resistive network R4630, R4631, and R4632. This bias voltage is also 
tuned in the factory. If the transistor is replaced, the bias voltage must be tuned using the Customer 
Programming Software (CPS). Care must be taken not to damage the device by exceeding the 
maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s dc supply 
voltage input, A+, via L4421.
2.5.4 Final Stage
The final stage uses the bipolar device Q4441. The device’s collector current is also drawn from the 
radio’s dc supply voltage input. To maintain class C operation, the base is dc-grounded by a series 
inductor (L4441) and a bead (L4440). A matching network consisting of C5541-C5544 and two 
striplines transform the impedance to 50 Ohms and feeds the directional coupler.
2.5.5 Bi-Directional Coupler 
The Bi-directional coupler is a microstrip printed circuit, which couples a small amount of the forward 
and reverse power of the RF power from Q4441. The coupled signal is rectified to an output power 
propor tional dc voltage by the diodes D4451 & D4452 and sent to the RFIN of the PCIC. The PCIC 
controls the gain of stage U4401 as necessary to hold this voltage constant. This ensures the 
forward power out of the radio is held to a constant value.
2.5.6 Antenna Switch
The antenna switch utilizes the existing dc feed (A+) to the last stage device (Q4441).   Basic 
operation is to have both PIN diodes D4471 and D4472 turns on during key-up by forward biasing 
them.   It is achieve by pulling down the voltage at the cathode end of D4472 to around 11.8V (0.7V 
drop across each diode). The current through the diodes needs to be set around 80mA to fully open 
the transmit path through resistor R4496.   Q4472 is a current source controlled by Q4471 and is 
eventually connected to pin ANO of PCIC. VR4471 ensures the voltage at the resistor R4511 never 
exceeds 5.6V 
2.5.7 Harmonic Filter 
Inductors L4491, L4492, L4493 and capacitors C4448, C4493,C4494, C4496 and C4498 form a low-
pass filter to attenuate harmonic energy from the transmitter. R4491 is used to drain any electrostatic 
charges that might otherwise build up on the antenna. The harmonic filter also prevents high level RF 
signals above the receiver passband from reaching the receiver circuits, improving spurious 
response rejection.
2.5.8 Power Control
The transmitter uses the Power Control IC (PCIC, U4501) to control the power output of the radio. A 
portion of the forward RF power from the transmitter is sampled by the bi-directional coupler and 
rectified, to provide a dc voltage to the RFIN port of the PCIC (pin 1) which is propor tional to the 
sampled RF power. 
The PCIC has internal digital to analog converters (DACs) which provide the reference voltage of the 
control loop. The reference voltage level is programmable through the SPI line of the PCIC. This 
reference voltage is proportional to the desired power setting of the transmitter, and is factory 
programmed at several points across the frequency range of the transmitter to offset frequency 
response variations of the transmitter’s power detector circuits. 
						

							2-22Theory of Operation
The PCIC provides a dc output voltage at pin 4 (INT) and applied as CNTLVLTG to the power-adjust 
input pin of the first transmitter stage U4401. This adjusts the transmitter power output to the 
intended value. Variations in forward or reflected transmitter power cause the dc voltage at pin 1 to 
change, and the PCIC adjusts the control voltage above or below its nominal value to raise or lower 
output power.
Capacitors C4502-4, in conjunction with resistors and integrators within the PCIC, control the 
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into 
adjacent channels.
U4502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity 
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29) 
propor tional to temperature. If the dc voltage produced exceeds the set threshold in the PCIC, the 
transmitter output power is reduced so as to reduce the transmitter temperature.
2.6 Frequency Synthesis
The synthesizer subsystem consists of the reference oscillator (Y4261 or Y4262), the low voltage 
fractional-N synthesizer (LVFRAC-N, U4201), and the Voltage Controlled Oscillator VCO.
2.6.1 Reference Oscillator
The reference oscillator (Y4262) contains a temperature compensated crystal oscillator with a 
frequency of 16.8 MHz. An Analog-to-Digital (A/D) converter internal to U4201 (LVFRAC-N) and 
controlled by the µP via serial interface (SRL) sets the voltage at the warp output of U4201, pin 25 to 
set the frequency of the oscillator. The output of the oscillator (pin 3 of Y4262) is applied to pin 23 
(XTAL1) of U4201 via an RC series combination.
In applications where less frequency stability is required the oscillator inside U4201 is used along 
with an external crystal Y4261, varactor diode D4261, C4261, C4262 and R4262. In this case, 
Y4262, R4263, C4235 and C4251 are not used. When Y4262 is used, Y4261, D4261, C4261, 
C4262 and R4262 are not used, and C4263 is increased to 0.1 uF.
2.6.2 Fractional-N Synthesizer 
The LVFRAC-N synthesizer IC (U4201) consists of a pre-scaler, a programmable loop divider, control 
divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital 
modulation, a balanced attenuator to balance the high frequency analog modulation and low 
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and 
finally a super filter for the regulated 5 volts.
A voltage of 5V applied to the super filter input (U4201 pin 30) supplies an output voltage of 4.5 Vdc 
(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R4322) and the synthesizer 
charge pump resistor network (R4251, R4252). The synthesizer supply voltage is provided by the 5V 
regulator U4211.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U5701-32), a voltage of 13 Vdc is being generated by the positive voltage multiplier circuitry 
(D4201, C4202, C4203). This voltage multiplier is basically a diode capacitor network driven by two 
signals (1.05MHz) 180 degrees out of phase (U4201-14 and -15). 
						

							Theory of Operation2-23
Figure 2-9.   UHF Synthesizer Block Diagram
Output LOCK (U4201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U4201 provides the 16.8 MHz reference frequency at 
pin 19.
The serial interface (SRL) is connected to the µP via the data line DATA (U4201-7), clock line CLK 
(U4201-8), and chip enable line CSX (U4201-9).
2.6.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO buffer IC (VCOBIC, U4301), the TX and 
RX tank circuits, the external RX buffer stages, and the modulation circuits.
The VCOBIC together with Fractional-N synthesizer (U4201) generates the required frequencies in 
both transmit and receive modes. The TRB line (U4301 pin 19) determines which tank circuits and 
internal buffers are to be enabled. A high level on TRB enables TX tank and TX output (pin 10), and 
a low enables RX tank and RX output (pin 8). A sample of the signal from the enabled output is 
routed from U4301 pin 12 (PRESC_OUT), via a low pass filter, to pin 32 of U4201 (PREIN).
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U4211 PIN 1)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
        1540FILTERED 5VSTEERING LOCK (U0101 PIN 56)
PRESCALER INFREF (U0221 PIN 34)
39 BIAS2
41
 48 5, 20, 34, 36
+5V (U4211 PIN 1)
AUX1 VDD, DC5VMODOUT
U4201 
LOW VOLTAGEFRACTIONAL-N
SYNTHESIZER
AUX21 (NU)
BWSELECTVCO Bias
TRB
To IF
SectionTX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
2-POLE
LOOP
FILTER 
						

							2-24Theory of Operation
A steering line voltage (VCTRL) between 3.0V and 10.0V at varactor diode CR4311 will tune the full 
TX frequency range (TXINJ) from 403 MHz to 470 MHz, and at varactor diodes CR4301, CR4302 
and CR4303 will tune the full RX frequency range (RXINJ) from 358 MHz to 425 MHz. The tank 
circuits uses the Hartley configuration for wider bandwidth. For the RX tank circuit, an external 
transistor Q4301 is used in conjunction with the internal transistor for better side-band noise.
Figure 2-10.   UHF VCO Block Diagram
The external RX buffers (Q4332) are enabled by a high at U4201 pin 3 (AUX4) via transistor switch 
Q4333. In TX mode the modulation signal (VCOMOD) from the LVFRAC-N synthesizer IC (U4201 
pin41) is applied to the modulation circuits CR4321, R4321, R4322 and C4324. These modulate the 
TX VCO frequency via coupling capacitor C4321. Varactor CR4321 is biased for linearity from the 
VSF.
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U4201 Pin28)
VCC Buffers
TX RF Injection U4201 Pin 32 AUX3 (U4201 Pin2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U4301
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U4201 Pin28)Rx-SW
Tx-SW
Vcc-Logic
(U4201 Pin28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION
Q4301
Q4332 
						

							Theory of Operation2-25
2.6.4 Synthesizer Operation
The complete synthesizer subsystem comprises mainly of a low voltage FRAC-N (LVFRACN) IC, 
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuits, loop 
filter circuits, and dc supply. The output signal (PRESC_OUT) of the VCOBIC (U4301, pin12) is fed 
to of U4201, pin 32 (PREIN) via a low pass filter (C4229,L4225,C4226) which attenuates harmonics 
and provides correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U4201) is basically a dual modulus pre-scaler with selectable 
divider ratios. The divider ratio of the pre-scaler is controlled by the loop divider, which in turn 
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output 
of the loop divider is connected to the phase detector, which compares the loop divider´s output 
signal with the reference signal.The reference signal is generated by dividing down the signal of the 
reference oscillator (Y4261 or Y4262).
The output signal of the phase detector is a pulsed dc signal which is routed to the charge pump. The 
charge pump outputs a current at pin 43 of U4201 (IOUT). The loop filter (which consists of R4221-
R4223, C4221-C4225,L4221) transforms this current into a voltage that is applied to the varactor 
diodes CR4311 for transmit, CR4301, CR4302 & CR4303 for receive and alters the output frequency 
of the VCO.The current can be set to a value fixed in the LVFRAC-N IC or to a value determined by 
the currents flowing into BIAS 1 (U4201-40) or BIAS 2 (U4201-39). The currents are set by the value 
of R4251 or R4252 respectively. The selection of the three different bias sources is done by software 
programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the 
magnitude of the loop current is increased by enabling the IADAPT (U4201-45) for a cer tain software 
programmable time (Adapt Mode). The adapt mode timer is started by a low to high transient of the 
CSX line. When the synthesizer is within the lock range the current is determined only by the 
resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled synthesizer loop is 
indicated by a high level of signal LOCK (U4201-4). 
LOCK (U4201-4) signal is routed to one of the µP´s ADCs input U101-56. From the voltage the µP 
determines whether LOCK is active.
In order to modulate the PLL the two spot modulation method is utilized Via pin 10 (MODIN) on 
U4201. The audio signal is applied to both the A/D converter (low frequency path) as well as the 
balanced attenuator (high frequency path). The A/D conver ter conver ts the low frequency analog 
modulating signal into a digital code which is applied to the loop divider, thereby causing the carrier 
to deviate. The balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency 
modulating signals. The output of the balance attenuator is present at the MODOUT port (U4201-41) 
and connected to the VCO modulation diode CR4321 via R4321, C4325. 
						

							2-26Theory of Operation
2.7 VHF (136-174MHz) Receiver Front-End
The receiver is able to cover the VHF range from 136 to 174 MHz. It consists of four major blocks: 
front-end bandpass filters and pre-amplifier, first mixer, 1st IF, 2nd IF, and receiver back-end. Two 
varactor-tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode mixer 
conver ts the signal to the first IF of 44.85 MHz. High-side injection is used.
Figure 2-11.   VHF Receiver Block Diagram
There are two 2-pole 44.85 MHz crystal filters in the 1st IF section and 2 pairs of 455 kHz ceramic 
filters in the 2nd IF section to provide the required adjacent channel selectivity. The correct pair of 
ceramic filters for 12.5 or 25kHz channel spacing is selected via control line BWSELECT. The 
second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The processing of the 
demodulated audio signal is performed by an audio processing IC located in the controller section.
Demodulator
1. Crystal 
Filter Mixer Va r a c t o r  
Tuned Filter RF Amp Va r a c t o r  
Tuned Filter Pin Diode 
Antenna 
Switch
RF Jack
Control Voltage
from PCICFirst LO
from FGU
Recovered Audio
RSSI
IF
Second LO
2. Crystal 
Filter
455kHz Filter
(25kHz)455kHz Filter
(25kHz)
455kHz Filter
(12.5kHz)455kHz Filter
(12.5kHz)SwitchSwitchSwitchSwitch
Limiter
1. IF Amp
2. IF Amp
Filter Bank Selection
from Synthesizer IC