Motorola Cdm And Pro Series Detailed 68p81091c63 O Manual

							Theory of Operation2-7
2.2.10 Normal Microprocessor Operation
The µP is configured to operate in one of two modes: expanded or bootstrap. In expanded mode, the 
µP uses external memory devices to operate. In bootstrap mode, the µP uses only its internal 
memory. 
During normal operation of the radio, the µP is operating in expanded mode and the µP (U0101) has 
access to three external memory devices: U0121 (EEPROM), U0122 (SRAM), and U0111 
(EEPROM). Also, within the µP there are three KBs of internal RAM, as well as logic to select 
external memory devices.
The external EEPROM (U0111) space contains the information in the radio which is customer 
specific, referred to as the codeplug. This information consists of items such as: 
nBand in which the radio operates 
nWhat frequencies are assigned to what channel
nTuning information. 
The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary 
calculations required by the software during execution. All of the data stored in both of these 
locations is lost when the radio powers off (See the par ticular device subsection for more details).
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of eight 
data lines (DATA 0 - DATA 7). There are also three control lines: CSPROG (U0101, pin 38) to chip 
select U0121, pin 30 (EEPROM), CSGP2 (U0101, pin 41) to chip select U0122, pin 20 (SRAM) and 
PG7 R W (U0101, pin 4) to select whether to read or to write. The external EEPROM (U0111,pin 1), 
the OPTION BOARD and EXPANSION BOARD are selected by three lines of the µP using address 
decoder U0141. The chips ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101, pin 2).
When the µP is functioning normally, the address and data lines are toggling at CMOS logic levels. 
Specifically, the logic high levels should be between 4.8 to 5.0 volts, and the logic low levels should 
be between 0 to 0.2 volts. No other intermediate levels should be observed, and the rise and fall 
times should be 
						

							2-8Theory of Operation
U0101-69 is the high reference voltage for the A/D por ts on the µP. Capacitor C0101 filters the +5 
volt reference. If this voltage is lower than +5 volt, the A/D reading is incorrect. Likewise U0101, pin 
68 is the low reference for the A/D ports. This line is normally tied to ground. If this line is not 
connected to ground, the A/D readings could be incorrect.
2.2.11 Static Random Access Memory (SRAM)
The SRAM (U0121) contains temporary radio calculations or parameters that can change very 
frequently, and which are generated and stored by the software during its normal operation. The 
information is lost when the radio is turned off. 
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS 
signal U0122, pin 20 which is the result of U0101-CSGP2 going low. U0122 is commonly referred to 
as the external RAM as opposed to the internal RAM which is the 3 KBs of RAM (par t of the 
68HC11FL0). Both RAM spaces serve the purpose. However, the internal RAM is used for the 
calculated values which are accessed most often.
Capacitor C0122 filters out any ac noise which may ride on +5V at U0122.
2.3 Controller Board Audio and Signalling Circuits
2.3.1 Audio Signalling Filter IC with Compander (ASFIC CMP)
The ASFIC CMP (U0221) used in the controller has the four following functions:
nRX/TX audio shaping, i.e. filtering, amplification, attenuation 
nRX/TX signalling, PL/DPL/HST/MDC/MPT
nSquelch detection
nµP clock signal generation 
The ASFIC CMP is programmable through the SPI BUS (U0221-20/21/22), normally receiving 19 
bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or 
signalling signals through the appropriate filtering, gain, and attenuator blocks. The ASFIC CMP also 
has six general control bits (GCB0-5) which are CMOS level outputs and used for NOISE BLANKER 
(GCB0) in low band radios, EXTERNAL ALARM (GCB1), and DC POWER ON (GCB2) to switch the 
voltage regulators (and the radio) on and off. GCB3 controls U0251, pin 11 to output either RX FLAT 
AUDIO or RX FILTERED AUDIO on the accessory connector, pin 11. GCB4 controls U0251, pin 10 
to use either the external microphone input or the voice storage playback signal. GCB5 switches the 
audio PA on and off. 
						

							Theory of Operation2-9
2.3.2 Transmit Audio Circuits
Refer to Figure 2-3 for the descriptions that follow.
Figure 2-3.   Transmit Audio Paths
2.3.3 Microphone Input Path
The radio supports two microphone input paths. One from the control head external microphone 
accessory connector J0501, pin 2, and one from the microphone auxiliary path (FLAT TX AUDIO) via 
accessory connector J0501, pin 5. The microphones require a DC biasing voltage provided by a 
resistive network.
The two microphone audio input paths enter the ASFIC CMP at U0221, pin 48 (external microphone) 
and U0221, pin 46 (auxiliary microphone). 
The microphone is plugged into the radio control head which is connected to the controller board via 
J0401, pin 9. The signal is then routed via R0409 and line INT MIC to R0205. Resistors R0201 and 
R0202 provide 9.3Vdc bias. Resistive divider R0205/R0207 divide the input signal by 5.5 and provide 
input protection for the CMOS amplifier input. R0202 and C0201 provide a 560 ohm AC path to 
ground that sets the input impedance for the microphone and determines the gain based on the 
emitter resistor in the microphone’s amplifier circuit.
Capacitor C0204 provides dc blocking. The audio signal at U0221, pin 46 (TP0221) is approximately 
14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The external microphone signal enters the radio on accessory connector J0501, pin 5, then it is 
routed via line EXT MIC to resistor R0206. Resistors R0201 and R0204 provide a 9.3Vdc bias. 
Resistive divider R0206 / R0208 divide the input signal by 5.5 and provide input protection for the 
CMOS amplifier input. R0204 and C0201 provide a 560 ohm AC path to ground that sets the input 
impedance for the microphone and determines the gain based on the emitter resistor in the 
microphone’s amplifier circuit. Capacitor C0254 provides dc blocking. 
MIC 
IN
MOD IN
TO
RF
SECTION
(SYNTHESIZER)
36 44
33
40
J0501
ACCESSORY
CONNECTOR
J0401
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
FLAT TX
AUDIO4232
548
46 9
2
IN
OUTOPTION
BOARD
FILTERS AND
PREEMPHASIS
HS SUMMER
SPLATTER
FILTER
LS SUMMERLIMITER
ATTENUATORVCO 
ATN TX RTN TX SND
MIC
INT
AUX 
TX
ASFIC_CMP 
 U0221
TP0221
TP0222MIC
EXT
J0451J0551
18 FLAT
TX RTN
EXPANSION BOARD31
IN
39
OUT 
						

							2-10Theory of Operation
Multi switch U0251 controlled by ASFIC CMP por t GCB4 selects either the external microphone 
input signal or the voice storage playback signal for entering the ASFIC CMP at pin 48. The audio 
signal at U0221-48 (TP0222) is approximately 14mVrms for 1.5kHz or 3kHz of deviation with 
12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO signal from accessory connector J0501-5 is fed to the ASFIC CMP (U0221, pin 
42) through C0541 and line FLAT TX RTN.
The ASFIC has an internal AGC that controls the gain in the microphone audio path. The AGC can 
be disabled/enabled by the µP. Another feature that can be enabled/disabled in the ASFIC is the 
VOX. This circuit, along with the capacitor at U0221, pin 7, provides a dc voltage allows the µP to 
detect microphone audio. The ASFIC can also be programmed to route the microphone audio to a 
speaker for public address operation.
2.3.3.1  PTT Sensing and TX Audio Processing
The microphone PTT signal coming from the control head is sent via the SBEP bus to the µP. An 
external PTT can be generated by grounding pin 3 on the accessory connector if this input is 
programmed for PTT by the CPS. When microphone PTT is sensed, the µP always configures the 
ASFIC CMP for the internal microphone audio path, and external PTT results in the external 
microphone audio path being selected.
Inside the ASFIC CMP, the microphone audio is filtered to eliminate frequency components outside 
the 300-3000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then 
limited to prevent the transmitter from over deviating. The limited microphone audio is then routed 
through a summer, which is used to add in signalling data, and then to a splatter filter to eliminate 
high frequency spectral components that could be generated by the limiter. The audio is then routed 
to an attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. 
The TX audio emerges from the ASFIC CMP at U0221-40 MOD IN, at which point it is routed to the 
RF section.
2.3.3.2  TX Secure Audio (optional)
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX 
SND pin (U0221-44), which is fed to the Secure board residing at option connector J0551-33. The 
Secure board contains circuits to amplify, encrypt, and filter the audio. The encrypted signal is then 
fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin 
should be about 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and 
emerges at MOD IN pin 40.
2.3.3.3  Option Board Transmit Audio
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX 
SND pin (U0221-44), which is fed to the option board residing at option connector J0551-33. The 
option board contains circuits to process the audio. The processed signal is then fed back from 
J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin is approximately 
65mVrms. The signal is then routed through the TX path in the ASFIC CMP and out at MOD IN, pin 
40. 
						

							Theory of Operation2-11
2.3.4 Transmit Signalling Circuits
Refer to Figure 2-4 for the descriptions that follow.
Figure 2-4.   Transmit Signalling Paths
The three types of transmit signalling paths are as follows:
• Sub-audible data (PL/DPL/connect tone) summed with transmit voice or signalling
• DTMF data for telephone communication between trunked and conventional systems
• Audible signalling 
2.3.4.1  Sub-Audible Data (PL/DPL)
Sub-audible data implies signalling whose frequency/data rate is below 300Hz. PL and DPL 
waveforms are used for conventional operation and connect tones for trunked voice channel 
operation. The trunking connect tone is simply a PL tone at a higher deviation level than PL in a 
conventional system. Although it is referred to as sub-audible data, the actual frequency spectrum 
of these waveforms may be as high as 250 Hz, which is audible to the human ear. However, the radio 
receiver filters out any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U0221 (ASFIC CMP) at any one time. The 
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper low-
speed data deviation and select the PL or DPL filters. The µP then generates a square wave which 
strobes the ASFIC PL / DPL encode input LSIO U0221-18 at twelve times the desired data rate. For 
example, for a PL frequency of 103Hz, the frequency of the square wave is 1236Hz.
This drives a tone generator inside U0221 which generates a staircase approximation to a PL sine 
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice or 
data. The resulting summed waveform then appears on U0221-40 (MOD IN), where it is sent to the 
RF board as previously described for transmit audio. A trunking connect tone would be generated in 
the same manner as a PL tone. NOTE
All three types are supported by the hardware while the radio software determines which 
signalling type is available. 
						

							2-12Theory of Operation
2.3.4.2  High Speed Data
High speed data refers to the 3600 baud data waveforms, known as inbound signalling words (ISWs) 
used in a trunking system for high speed communication between the central controller and the 
radio. To generate an ISW, the µP first programs the ASFIC CMP (U0221) to the proper filter and 
gain settings. It then begins strobing U0221-19 (HSIO) with a pulse when the data is supposed to 
change states. U0221’s 5-3-2 state encoder, which is in a 2-state mode, is then fed to the post-limiter 
summer block and then the splatter filter. From that point, it is routed through the modulation 
attenuators and then out of the ASFIC CMP to the RF board. MPT 1327 and MDC are generated in 
much the same way as trunking ISW. However, in some cases these signals may also pass through 
a data pre-emphasis block in the ASFIC CMP. Also these signalling schemes are based on sending 
a combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during high speed 
data signalling.
2.3.4.3  Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type of 
tones which are heard when using a Touch Tone telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high 
group (1209, 1336, 1477Hz).
The high-group tone is generated by the µP (U0101-44) strobing U0221-19 at six times the tone 
frequency for tones less than 1440Hz or twice the frequency for tones greater than 1440Hz. The low 
group tone is generated by the ASFIC CMP, controlled by the µP via SPI bus. Inside U0221 the low-
group and high-group tones are summed (with the amplitude of the high group tone being 
approximately 2 dB greater than that of the low group tone) and then pre-emphasized before being 
routed to the summer and splatter filter. The DTMF waveform then follows the same path as 
described for high-speed data 
						

							Theory of Operation2-13
2.3.5 Receive Audio Circuits
Refer to Figure 2-5 for the descriptions that follow.
Figure 2-5.   Receive Audio Paths
2.3.5.1  Squelch Detect
The squelch detect circuits are all contained within the ASFIC CMP as shown in Figure 2-5. The 
radio’s RF circuits are constantly producing an output (DISC AUDIO) at the discriminator IF IC. The 
output signal is applied to the ASFIC CMP’s squelch detect circuits DISC input (U0221, pin 2). The 
squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then sent 
to a comparator to produce an active high signal (CH ACT). The squelch circuit produces the SQ 
DET signal at U0221, pin 17 from the CH ACT input signal. The state of CH ACT and SQ DET go 
from a low (logic 0) to a high (logic 1) when an RF carrier is detected. The CH ACT and SQ DET 
signals from the squelch circuit are applied to the µP pins 84 and 83 respectively.
SQ DET is used to determine all audio mute/unmute decisions except for conventional scan. In this 
case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.
FLT RX AUDIOJ050111
16
1EXTERNAL
SPEAKER
INTERNAL
SPEAKER ACCESSORY
CONNECTOR
CONTROLHEAD
CONNECTOR
HANDSET
AUDIO 7 2 3
J0401 INT
SPKR-
SPKR +
SPKR -1
9
2
J0551
41 10
INT
SPKR+
4
6
DISC
ASFIC_CMP
U0221
AUDIO 
PA
U0271
IN
OPTION
BOARD
IN OUT
VOLUME
ATTEN.
FILTER AND
DEEMPHASIS
17
MICRO 
CONTROLLER
U010180 FROM
RF
SECTION
(IF IC)
LIMITER, RECTIFIER
FILTER, COMPARATOR
SQ DETSQUELCH
CIRCUIT
16
PL  FILTER 
LIMITER
CH ACT
AUX RX43
18
LS IO
U IOAUDIO
8384
39URX OUT
17
J0451
EXPANSION
BOARDDISC
AUDIO34 28
35
85
IN
7 
						

							2-14Theory of Operation
2.3.5.2  Audio Processing and Digital Volume Control
The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is AC 
coupled by C0227 before entering the ASFIC CMP via the DISC input at U0221, pin 2. The signal is 
then applied to both the audio and the PL/DPL paths.
The signal on the audio path is applied to a programmable amplifier, whose setting is based on the 
channel bandwidth being received, an LPF filter to remove any frequency components above 
3000Hz, and HPF filter to strip off any sub-audible data below 300Hz. The recovered audio passes 
through a de-emphasis filter, if it is enabled, to compensate for pre-emphasis which is used to reduce 
the effects of FM noise. The audio then goes through the 8-bit programmable attenuator whose level 
is set depending on the value of the volume control. The resulting filtered audio signal is passed 
through an output buffer within the ASFIC CMP and exits the ASFIC CMP at the AUDIO output 
(U0221, pin 41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum/
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signalling is summed with voice information on transmit, it must be separated from 
the voice information before processing. Any sub-audible signal enters the ASFIC CMP from the IF 
IC at DISC U0221, pin 2, then through the PL/DPL path. The signal first passes through one of two 
low pass filters, either PL low pass filter, or DPL/LST low pass filter. Either signal is then filtered, goes 
through a limiter, and exits the ASFIC CMP at LSIO (U0221, pin 18). At this point the signal appears 
as a square wave version of the sub-audible signal the radio received. The µP (U0101, pin 80) 
decodes the signal directly to determine if it is the tone/code currently active on that mode.
2.3.5.3  Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot (U0221, pin 41) is routed through dc blocking 
capacitor C0256 to a buffer formed by U0211, pin 1. Resistors R0256 and R0268 set the correct 
input level to the audio PA (U0271). This is necessary because the gain of the audio PA is 46 dB and 
the ASFIC CMP output is capable of overdriving the PA unless the maximum volume is limited. 
Resistor R0267 and capacitor C0267 increase frequency components below 350 Hz.
The audio then passes through R0269 and C0272 which provides AC coupling and low frequency 
roll-off. C0273 provides high frequency roll-off as the audio signal is routed to audio power amplifier 
U0271, pins 1 and 9 which are both tied to the received audio. The audio power amplifier has one 
inverted and one non-inver ted output that produces the differential audio output SPK+/SPK- (U0271, 
pins 4 and 6). 
The audio PA’s dc biases are not activated until the audio PA is enabled at pin 8. The audio PA is 
enabled via the ASFIC CMP (U0221, pin 38). When the base of Q0271 is low, the transistor is off and 
U0271-8 is high via pull-up resistor R0273, and the audio PA is ON. The voltage at U0273-8 must be 
above 8.5Vdc to properly enable the device. If the voltage is between 3.3 and 6.4V, the device is 
active, but has its input (U0273, pins 1 and 9) off. This is a mute condition used to prevent an audio 
pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA are dc biased and vary proportionately with FLT A+ 
(U0271, pin 7). FLT A+ of 11V yields a dc offset of 5V, and FLT A+ of 17V yields a dc offset of 8.5V. If 
either of these lines is shor ted to ground, it is possible that the audio PA could be damaged. SPK+ 
and SPK- are routed to the accessory connector (J0501, pins 1 and 16) and to the control head 
connector (J0401, pins 2 and 3). 
						

							Theory of Operation2-15
2.3.5.4  Handset Audio
Certain accessories have a self contained speaker which requires a different voltage level than that 
provided by U0271. For those devices, HANDSET AUDIO is available at control head connector 
J0401, pin 7.
The received audio from the output of the ASFIC CMP’s digital volume attenuator and buffered by 
U0211, pin 1, is also routed to U0211, pin 9 where it is amplified by 20 dB. This is set by the 10k/
100k combination of R0261 and R0262. This signal is routed from the output of the op amp U0211 to 
J0401-7. The control head sends this signal directly out to the microphone jack. The maximum value 
of this output is 6.6Vp-p.
2.3.5.5  Filtered Audio and Flat Audio
The ASFIC CMP audio output at U0221, pin 39 is filtered and de-emphasized, but has not yet gone 
through the digital volume attenuator. From ASFIC CMP U0221, pin 39 the signal is routed via 
R0251 through gate U0251, pin 12 and AC coupled to U0211, pin 2. The gate controlled by ASFIC 
CMP port GCB3 (U0221, pin 35) selects between the filtered audio signal from the ASFIC CMP at 
pin 39 (URXOUT) or the unfiltered flat audio signal from the ASFIC CMP, U10, pin 10. Resistors 
R0251 and R0253 determine the gain of op amp U0211, pin 2 for the filtered audio while R0252 and 
R0253 determine the gain for the flat audio.The output of U0253, pin 7 is then routed to J0501, pin 
11 via dc blocking capacitor C0542. Note that any volume adjustment of the signal on this path must 
be done by the accessory.
2.3.5.6  RX Secure Audio Option
Discriminator audio, which is now encrypted audio, follows the normal receive audio processing until 
it is output from the ASFIC CMP UIO (U0221, pin 10), which is fed to the secure audio board at 
option connector J0551, pin 35. On the secure board, the encrypted signal is converted back to 
normal audio format, then fed back through J0551, pin 34 to AUX RX of the ASFIC CMP (U0221, pin 
43). The signal then follows a path identical to the conventional receive audio, where it is filtered (0.3 
- 3kHz) and deemphasized. The signal URX SND from the ASFIC CMP (U0221-39) also routed to 
option connector J0551, pin 28, is not used for the secure board, but for other option boards.
2.3.5.7  Option Board Receive Audio
Unfiltered audio from the ASFIC CMP (U0221, pin 10) enters the option board at connector J0551, 
pin 35. Filtered audio from the ASFIC CMP URXOUT (U0221, pin 39) enters the option board at 
connector J0551, pin 28. On the option board, the signal is processed, then fed back through (J0551, 
pin 34) to AUX RX of the ASFIC CMP (U0221, pin 43). The signal then follows a path identical to 
conventional receive audio, where it is filtered (0.3 - 3kHz) and de-emphasized. 
						

							2-16Theory of Operation
2.3.6 Receive Signalling Circuits
Refer to Figure 2-6 for the descriptions that follow.
Figure 2-6.   Receive Signalling Paths
2.3.6.1  Sub-Audible Data (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U0221) filters and limits all received data. The data enters the ASFIC CMP at input 
DISC (U0221, pin 2). Inside U0221 the data is filtered according to data type (HS or LS), then it is 
limited to a 0-5V digital level. The MDC and trunking high speed data appear at U0221, pin 19, where 
it connects to the µP U0101, pin 82
The low speed limited data output (PL, DPL, and trunking LS) appears at U0221, pin 18, where it 
connects to the µP U0101, pin 80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch 
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C0236, and 
C0244 set the low frequency pole for a zero crossings detector in the limiters for PL and HS data. 
The hysteresis of these limiters is programmed based on the type of received data.
2.3.6.2  Aler t Tone Circuits
When the software determines that it needs to give the operator an audible feedback for a good key 
press, or for a bad key press, or radio status (trunked system busy, phone call, circuit failures), it 
sends an aler t tone to the speaker. It does so by sending SPI BUS data to U0221 which sets up the 
audio path to the speaker for aler t tones. The aler t tone itself can be generated in one of two ways: 
internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.
The allowable internal aler t tones are 304, 608, 911, and 1823Hz. In this case a code contained 
within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency, and 
at what volume level to generate the tone. (It does not have to be related to the voice volume setting).
For external aler t tones, the µP can generate any tone within the 100-3000Hz audio band. This is 
accomplished by the µP generating a square wave which enters the ASFIC CMP at U0221-19. Inside 
the ASFIC CMP this signal is routed to the alert tone generator
The output of the generator is summed into the audio chain just after the RX audio de-emphasis 
block. Inside U0221 the tone is amplified and filtered, then passed through the 8-bit digital volume 
attenuator, which is typically loaded with a special value for alert tone audio. The tone exits at U0221-
41 and is routed to the audio PA like receive audio.
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF  IC)19
18
25
2
82
80
DISC
PLCAP2LSIO HSIO DATA FILTER
AND DEEMPHASISLIMITER
FILTER
LIMITERASFIC_CMP
U0221
MICRO
CONTROLLER
U0101
85 44
8 PLEAP